DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 – 10 are pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over KR1020180048938 hereinafter KR in view of JP2020521195 hereinafter JP.
As to claim 1 KR discloses a hardware accelerator (Fig. 2, module 200) comprising: a control part (Fig. 2, and module 206);
and a data operation part (Fig. 2, and module 222) receiving and processing an input array composed of a plurality of non-compressed data groups NCG (Fig. 2, 202 (1) – 202 (n), wherein the control part is configured to perform, a process of sequentially reading the plurality of non-compressed data groups or a plurality of compressed data groups (Fig. 2, 224 (1) – 224 (n) corresponding to the plurality of non- compressed data groups from a memory (Fig. 2, 226 (1) – 226 (n), (paras. 0031, 0032).
KR does not explicitly disclose if it is determined that elements should be sequentially input to the data operation part by taking priority in a first direction of dimension over a second direction of dimension of the input array, by taking priority in the first direction of dimension over the second direction of dimension, and if all of a series of elements of the input array disposed along the first direction of dimension are prepared, a process of inputting the series of elements to the data operation part.
JP teaches that elements should be sequentially input to the data operation part by taking priority in a first direction of dimension over a second direction of dimension of the input array, by taking priority in the first direction of dimension over the second direction of dimension, and if all of a series of elements of the input array disposed along the first direction of dimension are prepared, a process of inputting the series of elements to the data operation part (para. 0021). One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the directed graph scheme of JP in the system of KR to enable an efficient implementation leveraging it sequencing of super layers for energy efficiency (para. 0016)
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over KR/JP in further view of KR102038390 hereinafter KR2.
As to claim 2, KR/JP does not explicitly disclose the hardware accelerator, wherein two or more data groups are defined in the input array along the second direction of dimension.
KR2 teaches wherein two or more data groups are defined in the input array along the second direction of dimension (Table 1, and para. 24 illustrating a 3-dimensional matrix. One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use scheme of KR2 in the system of KR/JP to enable complex, high performance operations (para. 0005).
Allowable Subject Matter
Claims 3 – 5 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 6- 9 are allowed.
The following is an examiner’s statement of reasons for allowance: Independent claim 6, and its dependents thereof are allowed because the prior art either alone or in combination fail to anticipate or render obvious, the claimed limitation of
“ the control part is configured to perform a process of inputting the plurality of groups stored in the memory to the data operation part by reading the plurality of groups as an input array for input to the data operation part in a second time period, and in the process of inputting, the control part is configured to sequentially read the plurality of groups stored in the memory from the memory by taking priority in the first direction of dimension over the second direction of dimension and input a series of elements of the input array disposed along the first direction of dimension to the data operation part if all of the series of elements are prepared”.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US11989631, US20240220259, and US20140357526, among others teach the management (such as compression) of data into groups to further boast the efficiency of accelerators.
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/C.A.D/Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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