DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 12/10/2025, 09/12/2024, 03/01/2024, and 03/07/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in an application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Regarding claim 1, claim includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: the control unit is configured to individually control supply of power to the first region, the second region, the third region, and the plurality of fourth regions.
In particular, the claim limitation “unit” is a generic placeholder that is coupled with functional language “control” and “is configured to individually control supply of power to the first region, the second region, the third region, and the plurality of fourth regions” without reciting sufficient structure to perform the recited function and the generic placeholder “control unit” is not preceded by a structural modifier.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. In this case, the control unit being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents as disclosed para 0041 “The control unit C0 is electrically connected to the magnetron oscillator 13, the solenoid coil 14, the load impedance variable box 16, the load matching unit 17, and the high-frequency power source 18, and controls their operation”, para 0050 “The control unit C0 is electrically connected to the high-frequency power source 70, the direct-current power source 71, the DC power source 72, and the DC power source 73, and controls their operation”, para 0057 “A temperature sensor 52 electrically connected to the control unit C0 is provided inside the basement 50, which is located below the heater HT1. The control unit C0 maintains the temperature detected by the temperature sensor 52 during plasma processing of the wafer WF. Note that a plurality of temperature sensors 52 are provided in accordance with the number of regions HT1d of the heater HT1 described later”, para 0063 “The regions HT2a to HT2c are individually electrically connected to the direct-current power source 72 illustrated in FIG. 3, respectively. Therefore, the control unit C0 is capable of individually controlling the supply of power to the regions HT2a to HT2c. As a result, the temperature of the regions of the wafer WF corresponding to the regions HT2a to HT2c is individually adjusted” such that the control unknit is construed as a generic controller.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Kosakai (US 20190088517 A1) in view of Kusumoto (US 20140216657 A1) and in further view of Pease (US 20130220989 A1).
Regarding claim 1, Kosakai discloses, a plasma processing apparatus (see an electrostatic chuck device 501 in Fig. 7 and Fig. 12, wherein in para 0007 disclosed “An electrostatic chuck device using an electrostatic chuck (ESC) is used in an etching apparatus using plasma, a CVD (Chemical Vapor Deposition) apparatus”) comprising:
a processing chamber (see chamber disclosed in para 0294 “If the plate-shaped sample W is supplied to an etching apparatus or a film forming apparatus and exposed to a plasma atmosphere or a film formation atmosphere, a temperature difference occurs in the plate-shaped sample W according to a plasma generation state, a temperature distribution in a film formation chamber, or the like”);
a cylindrical sample stage (see combination of a disk-shaped electrostatic chuck part 502 and a thick disk-shaped temperature controlling base part 503 in Fig. 7 and Fig. 12) provided to the processing chamber (see Fig. 7 and Fig. 12 and para 0294); and
a control unit (see combination of a temperature measurement unit 522 with control part 525 and temperature sensors 520 in Fig. 7, thermo-camera 530 in Fig. 12, and a switch element such as voltage control, voltage application time control, or current value control as disclosed in para 0273, 0287, and 0296 “energization and heat generation control of each of the main heaters can be performed with respect to each of the main heaters 505A, 505B, 505C, and 505D according to the operation of the switch element and the power source […] energization and heat generation control can be performed with respect to each of the heater split bodies 506a, 506b, 506c, and 506d according to the operation of the switch element and the power source […] Temperature control at the time of heating can be performed by application voltage control, voltage application time control, current value control, or the like when energizing each of the heater split bodies 506a, 506b, 506c, and 506d”),
wherein the sample stage includes a basement (thick disk-shaped temperature controlling base part 503) and an electrostatic chuck (disk-shaped electrostatic chuck part 502) that is provided on a top surface of the basement (see Fig. 7 and Fig. 12),
the electrostatic chuck (disk-shaped electrostatic chuck part 502) has a first heater (see second heater element 506 in Fig. 7 and Fig. 12 and Fig. 9) and a second heater (see first heater element 505 in Fig. 7 and Fig. 12 and Fig. 8), each covered by a dielectric film (see layers 509A, 509B, 507, 508 and 510 in Fig. 7 and Fig. 12 and disclosed in para 0242, 0246 “The adhesion layer 509A is made of the same adhesive resin as the adhesive layer 509B, and a sheet-shaped or film-shaped adhesive resin can be used […] the adhesion layer 509A made of a sheet-shaped or film-shaped silicon resin, acrylic resin, or the like having uniform thickness and having heat resistance and insulating properties”, para 0248 “Each of the insulation plates 507 and 508 is made of a thin plate, a sheet, or a film of heat-resistant resin such as polyimide resin, epoxy resin, or acrylic resin” and para 0250 “the wiring layer 504 is formed on the upper surface of the insulation plate 507, the second heater element 506 is formed on the upper surface of the insulation plate 508, and the peripheries of these elements are covered with the insulating part 510, whereby a laminated structure shown in FIG. 7 AND FIG. 12 is realized”, wherein it is known that a dielectric material is defined as an electrical insulator and made from non-metallic substances such as ceramics, glass, and plastics),
the second heater (505) is provided above the first heater (506 and see Fig. 7 and Fig. 12),
the second heater (505) is divided into a first region (see 505A in Fig. 8) having a circular shape in plan view (see Fig. 8), a second region (see 505B in Fig. 8) surrounding an outer periphery (see Fig. 8) of the first region (505A) in plan view (see Fig. 8), and a third region (see 505C in Fig. 8) surrounding an outer periphery (see Fig. 8) of the second region (505B) in plan view (see Fig. 8),
the first heater (506) is divided into a plurality of fourth regions (see 506A-D and 506a-d in Fig. 9), each having a fan shape in plan view (see Fig. 9),
the first region (505A), the second region (505B), the third region (505C), and the plurality of fourth regions (506A-D and 506a-d) are electrically connected to the control unit, and
the control unit (see combination of a temperature measurement unit 522 with control part 525 and temperature sensors 520 in Fig. 7, thermo-camera 530 in Fig. 12, and a switch element such as voltage control, voltage application time control, or current value control as disclosed in para 0273, 0287, and 0296) is configured to individually control supply of power to the first region, the second region, the third region, and the plurality of fourth regions (disclosed in para 0293 “temperature control can be performed by heating the plate-shaped sample W by causing the main heaters 505A to 505D to individually generate heat by feeding electric power from the power source to each of the main heaters 505A to 505D through the power supply terminal 517. Further, by individually energizing the heater split bodies 506a to 506d, it is possible to finely adjust the temperatures of the regions corresponding to the heater split bodies 506a to 506d”).
However, Kosakai does not explicitly disclose,
a vacuum vessel so as the processing chamber provided inside the vacuum vessel; and
each of the plurality of fourth regions of the first heater having a rectangular shape in plan view.
Nonetheless, Kusumoto teaches, a vacuum vessel (see vacuum vessel 101 in Fig. 1) so as the processing chamber (see processing chamber 103 in Fig. 1) provided inside the vacuum vessel (see Fig. 1).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the plasma processing apparatus of Kosakai to further comprises the vacuum vessel so as the processing chamber is provided inside the vacuum vessel as taught/suggested by Kusumoto in order to exhaust gases and particles from inside the processing chamber. Doing so would help to adjust the interior of the processing chamber to a desired degree of vacuum for the plasma processing apparatus (see para 0017 of Kusumoto “The evacuation section is disposed under the vacuum vessel 101 and has a vacuum pump for exhausting gases and particles from inside the processing chamber 103. The evacuation section adjusts the interior of the processing chamber 103 to a desired degree of vacuum”).
Kosakai and Kusumoto does not explicitly teach, each of the plurality of fourth regions of the first heater having a rectangular shape in plan view.
Pease teaches, each of a plurality of heating regions of a first heater (see primary heaters 601 in Fig. 9) having a rectangular shape in plan view (disclosed in para 0028 “The primary heaters may be arranged in any desired pattern such as a rectangular grid, concentric annular zones, radial zone or combination of annular zones and radial zones”).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the shape of each of the plurality of fourth regions of the first heater of Kosakai wherein each of the plurality of fourth regions of the first heater having a rectangular shape in plan view as taught/suggested by Pease in order to obtain each of the plurality of fourth regions of the first heater having a rectangular shape is of similar size to or smaller than a single device die or group of device dies on the substrate/wafer so that the substrate/wafer temperature, and consequently the plasma etching process, can be controlled for each device die position to maximize the yield of devices from the substrate/wafer (disclosed in para 0030 of Pease).
Regarding claim 2, Kosakai in view of Kusumoto and in further view of Pease discloses the plasma processing apparatus according to claim 1, Kosakai further discloses, wherein the first heater (506) and the second heater (505) are provided in order to adjust a temperature of a wafer (see plate-shaped semiconductor wafer W in Fig. 7 and Fig. 12) when the wafer (W) is placed on a top surface of the electrostatic chuck (see Figs. 7 and 12), and, when the control unit (see combination of a temperature measurement unit 522 with control part 525 and temperature sensors 520 in Fig. 7, thermo-camera 530 in Fig. 12, and a switch element such as voltage control, voltage application time control, or current value control as disclosed in para 0273, 0287, and 0296) is configured to individually control the supply of power to the plurality of fourth regions, a temperature of the plurality of wafer regions is individually adjusted (disclosed in para 0293 “temperature control can be performed by heating the plate-shaped sample W by causing the main heaters 505A to 505D to individually generate heat by feeding electric power from the power source to each of the main heaters 505A to 505D through the power supply terminal 517. Further, by individually energizing the heater split bodies 506a to 506d, it is possible to finely adjust the temperatures of the regions corresponding to the heater split bodies 506a to 506d”).
However, Kosakai in view of Kusumoto does not explicitly disclose, the wafer has a scribe region, and a plurality of chip regions each surrounded by the scribe region and each having a rectangular shape in plan view, and, when the control unit is configured to individually control the supply of power to the plurality of fourth regions, a temperature of the plurality of chip regions is individually adjusted.
Pease further teaches, the primary heaters may be arranged in any desired pattern such as a rectangular grid (see para 0028) and wherein each planar heater zone of the heating plate is of similar size to or smaller than a single device die or group of device dies on the substrate so that the substrate temperature, and consequently the plasma etching process, can be controlled for each device die position to maximize the yield of devices from the substrate (see para 0030).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the wafer substrate of Kosakai wherein the wafer has a scribe region, and a plurality of chip regions each surrounded by the scribe region and each having a rectangular shape in plan view, and, when the control unit is configured to individually control the supply of power to the plurality of fourth regions, a temperature of the plurality of chip regions is individually adjusted as taught/suggested by Pease in order to obtain each of the plurality of fourth regions of the first heater having a rectangular shape is of similar size to or smaller than a single device die or group of device dies on the substrate/wafer so that the substrate/wafer temperature, and consequently the plasma etching process, can be controlled for each device die position to maximize the yield of devices from the substrate/wafer (disclosed in para 0030 of Pease).
Regarding claim 3, Kosakai in view of Kusumoto and in further view of Pease discloses the plasma processing apparatus according to claim 2, Kosakai further discloses, wherein the plurality of fourth regions (506A-D and 506a-d) are provided such that one of the fourth regions is located below one of the wafer regions (see Figs. 7 and 12) when the wafer (W) is placed on the top surface of the electrostatic chuck (see Fig. 7 and Fig. 12).
However, Kosakai in view of Kusumoto does not explicitly disclose, the plurality of fourth regions are provided such that one of the fourth regions is located below one of the chip regions when the wafer is placed on the top surface of the electrostatic chuck.
Pease further teaches, the primary heaters may be arranged in any desired pattern such as a rectangular grid (see para 0028) and wherein each planar heater zone of the heating plate is of similar size to or smaller than a single device die or group of device dies on the substrate so that the substrate temperature, and consequently the plasma etching process, can be controlled for each device die position to maximize the yield of devices from the substrate (see para 0030).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the wafer substrate and each of the plurality of fourth regions of the first heater of Kosakai wherein the plurality of fourth regions are provided such that one of the fourth regions is located below one of the chip regions when the wafer is placed on the top surface of the electrostatic chuck as taught/suggested by Pease in order to obtain each of the plurality of fourth regions of the first heater having a rectangular shape is of similar size to or smaller than a single device die or group of device dies on the substrate/wafer so that the substrate/wafer temperature, and consequently the plasma etching process, can be controlled for each device die position to maximize the yield of devices from the substrate/wafer (disclosed in para 0030 of Pease).
Regarding claim 4, Kosakai in view of Kusumoto and in further view of Pease discloses the plasma processing apparatus according to claim 2, Kosakai further discloses, further comprising: a plurality of temperature sensors (see temperature sensors 520 in Figs. 7 and 12, each of which is provided inside the basement (see Figs. 7 and 12) located below the plurality of heating regions of the second heater (505), and electrically connected to the control unit (see combination of a temperature measurement unit 522 with control part 525 and temperature sensors 520 in Fig. 7, thermo-camera 530 in Fig. 12, and a switch element such as voltage control, voltage application time control, or current value control as disclosed in para 0273, 0287, and 0296), the wafer (see plate-shaped sample W) is photographed by a temperature sensor (see a thermo-camera 530) and analyzed by a thermograph, and then, if a region having a low temperature is generated in the plate-shaped sample W, the surface temperature of the plate-shaped sample W can be uniformized by locally raising the surface temperature of each corresponding zone of the plate-shaped sample W above the individual regions of the heater split bodies 506a, 506b, 506c, and 506d by energizing and heating any one of the heater split bodies 506a, 506b, 506c, and 506d in the corresponding region (see para 0295), and wherein the control unit (see combination of a temperature measurement unit 522 with control part 525 and temperature sensors 520 in Fig. 7, thermo-camera 530 in Fig. 12, and a switch element such as voltage control, voltage application time control, or current value control as disclosed in para 0273, 0287, and 0296) is configured to individually control supply of power to the first region, the second region, the third region, and the plurality of fourth regions (disclosed in para 0293 “temperature control can be performed by heating the plate-shaped sample W by causing the main heaters 505A to 505D to individually generate heat by feeding electric power from the power source to each of the main heaters 505A to 505D through the power supply terminal 517. Further, by individually energizing the heater split bodies 506a to 506d, it is possible to finely adjust the temperatures of the regions corresponding to the heater split bodies 506a to 506d”).
However, Kosakai in view of Kusumoto does not explicitly disclose, further comprising: a plurality of temperature sensors, each of which is provided inside the basement located below the plurality of fourth regions, and electrically connected to the control unit, wherein the control unit is configured to compare a difference between temperatures detected by the plurality of temperature sensors during plasma processing on the wafer and target temperatures previously set for the plurality of fourth regions before the plasma processing is performed, and individually control the supply of power to the plurality of fourth regions so as to minimize the difference.
Nonetheless, Pease teaches, the substrate support assembly can include temperature sensors for monitoring substrate temperature, a power feed arrangement to power the ESC with desired clamping voltage, a lifting pin arrangement for raising and lowering a substrate, a heat transfer gas feed arrangement for supplying gas such as helium to the underside of the substrate, a temperature controlled liquid feed arrangement to supply heat transfer liquid to the cooling plate, a power feed arrangement to individually power primary heaters above or below the planar heater zones, a power feed arrangement to supply RF power at one or more frequencies to a lower electrode incorporated in the substrate support assembly, and the like (see para 0055).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the heating control unit of Kosakai to further comprise a plurality of temperature sensors, each of which is provided inside the basement located below the plurality of fourth regions, and electrically connected to the control unit as taught/suggested by Pease such that the control unit of Kosakai is configured to compare a difference between temperatures detected by the plurality of temperature sensors during plasma processing on the wafer and target temperatures previously set for the plurality of fourth regions before the plasma processing is performed, and individually control the supply of power to the plurality of fourth regions so as to minimize the difference. Doing so would help to accurately monitor and control the temperature of the plurality of fourth regions of the first heater so as obtain a desired temperature for each die/chip on the substrate/wafer.
Regarding claim 5, Kosakai in view of Kusumoto and in further view of Pease discloses the plasma processing apparatus according to claim 4, Kosakai further discloses, wherein the control unit (see combination of a temperature measurement unit 522 with control part 525 and temperature sensors 520 in Fig. 7, thermo-camera 530 in Fig. 12, and a switch element such as voltage control, voltage application time control, or current value control as disclosed in para 0273, 0287, and 0296) is configured to individually control the supply of power to the plurality of fourth regions without changing the supply of power to the first region, the second region, and the third region (disclosed in para 0300 “the thickness of each of the main heaters 505A to 505D and the thickness of each of the heater split bodies 506a, 506b, 506c, and 506d can be freely selected at the time of manufacturing, and therefore, it is possible to individually set the withstand voltage according to each heater and each wiring and it is possible to set a desirable individual withstand voltage value for each heater and each wiring”).
Regarding claim 6, Kosakai in view of Kusumoto and in further view of Pease discloses the plasma processing apparatus according to claim 1, Kosakai further discloses, wherein the first region (505A), the second region (505B), the third region (505C), and the plurality of fourth regions (506A-D and 506a-b) are each configured by arranging a heater wire made of a metallic material to fold plural times (disclosed in para 0300 “the thickness of each of the main heaters 505A to 505D and the thickness of each of the heater split bodies 506a, 506b, 506c, and 506d can be freely selected at the time of manufacturing, and therefore, it is possible to individually set the withstand voltage according to each heater and each wiring and it is possible to set a desirable individual withstand voltage value for each heater and each wiring”), and a thickness of the heater wires constituting the first region, the second region, and the third region (main heater 505 A-C) is larger than a thickness of the heater wires constituting the plurality of fourth regions (disclosed in para 0300 “by setting the thickness of the main heater made of a Ti thin plate to be 100 μm and setting the thickness of the heater split body made of a Mo thin plate to be 5 μm”).
Regarding claim 7, Kosakai in view of Kusumoto and in further view of Pease discloses the plasma processing apparatus according to claim 6, Kosakai further discloses, wherein a wire width of the heater wires constituting the first region, the second region, and the third region is larger than a wire width of the heater wires constituting the plurality of fourth regions (disclosed in para 0300 “it is possible to adjust the calorific value per unit area of the heater split body to ⅕ or less of the main heater”).
Conclusion
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/VY T NGUYEN/Examiner, Art Unit 3761