DETAILED ACTION
Claims 17, 20, 22, 25, 27, 30, 32, and 35-36 are pending.
The office acknowledges the following papers:
Claims and remarks filed on 1/2/2026.
New Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17, 20, 27, 30, and 36 are rejected under 35 U.S.C. 103 as being unpatentable over Yan et al. (U.S. 2020/0402514), view of Volpe et al. (U.S. 2004/0064649), in view of Li et al. (U.S. 2019/0325877), in view of Official Notice.
As per claim 17:
Yan disclosed a method of voice chip implementation, comprising:
constructing a voice chip comprising a first Digital Signal Processor (DSP) and a second DSP (Yan: Figures 1 and 3 elements 31-32 and 100, paragraphs 31 and 63)(The speech chip includes two DSP processors.), the first DSP and the second DSP corresponding to a same Digital Signal Processor core Identifier (DSP core IP) (Yan: Figures 1, 3, and 5 elements 20, 31-32 and 100, paragraphs 31, 63, and 82)(Official notice is given that chips can be given chip IDs for the advantage of routing data to chips over networks. Thus, it would have been obvious to one of ordinary skill in the art to implement a chip ID for the speech chip. In view of the official notice, the first and second DSPs have the same ID.) and adopting heterogeneous designs (Yan: Figures 1 and 3 elements 31-32 and 100, paragraphs 31, 34, and 63)(The two DSP processors complete different tasks.); and
completing a chip processing function in a corresponding intelligent voice product by using the voice chip, wherein different functions are completed by using the first DSP and the second DSP respectively (Yan: Figures 1 and 3 elements 31-32 and 100, paragraphs 31, 34, and 63)(The two DSP processors complete different tasks. The first DSP performs a wake-up task and the second DSP performs a signal processing task.).
wherein the first DSP is configured to realize a first function which requires a fixed and small storage capacity (Yan: Figures 1 and 3 elements 31-32 and 100, paragraphs 31, 34, 38-39, 42-43, 46-47, 49-52, 55, and 63)(The two DSP processors complete different tasks. The first DSP performs a wake-up task. SRAM storage for first DSP includes an exclusive region (i.e. fixed storage capacity). Official notice is given that smaller tasks can be performed that only require a subset of memory capacity for the advantage of allowing other tasks additional memory capacity. Thus, it would have been obvious to one of ordinary skill in the art that the wake-up task can be performed solely using the corresponding exclusion region of SRAM (i.e. small storage capacity) and not the shared region of SRAM.), and the second DSP is configured to realize a second function which requires a non-fixed and large storage capacity and the second DSP has a low requirement on real time performance for programs and data (Yan: Figures 1 and 3 elements 31-32 and 100, paragraphs 31, 34, 38-39, 42-43, 46-47, 49-52, 55, and 63)(The two DSP processors complete different tasks. The second DSP performs a signal processing task, including signal denoising and speech recognition on the speech signal, which isn’t implemented to meet real-time requirements (i.e. low requirement). SRAM storage for second DSP includes an exclusive region and shared region (i.e. non-fixed and large storage capacity). Additionally, official notice is given that signal processing tasks can be performed in soft or low real-time requirements for the advantage of ensuring quality metrics are met. Thus, it would have been obvious to one of ordinary skill in the art to implement soft/low real-time requirements on the signal processing task of Yan.).
Yan failed to teach the first DSP adopts a standard configuration with program and data memories, comprising: a first DSP core, a first program memory, a first data memory, a first program cache (Icache), a first data cache (Dcache), a first advanced extensible interface master (AXI_M) bus interface, and a first advanced extensible interface slave (AXI_S) bus interface, the second DSP adopts a non-standard configuration without program and data memories, comprising: a second DSP core, a second Icache, a second Dcache, and a second AXI_M bus interface; and the second DSP accesses an external device through the second Icache and the second Dcache to acquire required programs and data, the second DSP is further configured to share storage spaces of the first program memory and the first data memory through the second AXI_M bus interface and the first AXI_S bus interface, and first DSP has a high requirement on real time performance for programs and data.
However, Volpe combined with Yan disclosed the first DSP adopts a standard configuration with program and data memories, comprising: a first DSP core (Volpe: Figure 1 element 10, paragraph 23)(Yan: Figures 1 and 3 element 31, paragraphs 31 and 63)(Volpe disclosed a DSP processor that includes a DSP core. The combination implements a DSP core within the first processor of Yan.), a first program memory (Volpe: Figure 1 element 12, paragraphs 23 and 25)(Yan: Figures 1 and 3 element 31, paragraphs 31 and 63)(Volpe disclosed a L2 memory with a first block for storing program data. The combination implements the L2 memory of Volpe within the first processor of Yan.), a first data memory (Volpe: Figure 1 element 12, paragraphs 23 and 25)(Yan: Figures 1 and 3 element 31, paragraphs 31 and 63)(Volpe disclosed a L2 memory with a second block for storing program data. The combination implements the L2 memory of Volpe within the first processor of Yan.), a first program cache (Icache) (Volpe: Figure 1 element 34, paragraph 23)(Yan: Figures 1 and 3 element 31, paragraphs 31 and 63)(Volpe disclosed an instruction cache within the DSP core for storing instruction data. The combination implements the instruction cache of Volpe within the first processor of Yan.), a first data cache (Dcache) (Volpe: Figure 1 element 32, paragraph 23)(Yan: Figures 1 and 3 element 31, paragraphs 31 and 63)(Volpe disclosed an data cache within the DSP core for storing data. The combination implements the data cache of Volpe within the first processor of Yan.), a first advanced extensible interface master (AXI_M) bus interface (Yan: Figures 1 and 3 elements 20 and 31, paragraphs 31, 59, and 64-65)(The first processor includes an AXI bus interface.), and a first advanced extensible interface slave (AXI_S) bus interface (Volpe: Figure 1 elements 56-58, paragraph 23)(Yan: Figures 1 and 3 elements 20 and 31, paragraphs 31, 59, and 64-65)(Volpe includes multiple external buses within the DSP processor. Yan includes a first processor that has a single AXI bus interface. The combination allows for a second AXI bus interface.),
the second DSP adopts a non-standard configuration without program and data memories, comprising: a second DSP core (Volpe: Figure 1 element 10, paragraph 23)(Yan: Figures 1 and 3 element 32, paragraphs 31 and 63)(Volpe disclosed a DSP processor that includes a DSP core. The combination implements a DSP core within the second processor of Yan.), a second Icache (Volpe: Figure 1 element 34, paragraph 23)(Yan: Figures 1 and 3 element 32, paragraphs 31 and 63)(Volpe disclosed an instruction cache within the DSP core for storing instruction data. The combination implements the instruction cache of Volpe within the second processor of Yan.), a second Dcache (Volpe: Figure 1 element 32, paragraph 23)(Yan: Figures 1 and 3 element 32, paragraphs 31 and 63)(Volpe disclosed a data cache within the DSP core for storing data. The combination implements the data cache of Volpe within the second processor of Yan.), and a second AXI_M bus interface (Yan: Figures 1 and 3 elements 20 and 32, paragraphs 31, 59, and 64-65)(The second processor includes an AXI bus interface.); and the second DSP accesses an external device through the second Icache and the second Dcache to acquire required programs and data (Volpe: Figure 1 elements 32-34 and 72, paragraph 23-25)(Yan: Figures 1 and 3 elements 32 and 40, paragraphs 31 and 63)(The combination implements the instruction and data cache of Volpe within the second processor of Yan. Volpe disclosed an off-chip memory, but doesn’t explicitly state how data is brought on-chip. Official notice is given that cache hierarchies involve bring off-chip data on chip via caches for the advantage of faster data access speeds. Thus, it would have been obvious to one of ordinary skill in the art that the added caches hold data brought in off-chip for data and instruction accesses.).
the second DSP is further configured to share storage spaces of the first program memory and the first data memory through the second AXI_M bus interface and the first AXI_S bus interface (Volpe: Figure 1 elements 12 and 56-58, paragraphs 23 and 25)(Yan: Figures 1 and 3 elements 20 and 31, paragraphs 31, 59, and 63-65)(The combination implements the L2 memory of Volpe within the first processor of Yan. Official notice is given that processors can share caches for the advantage of reduced cache costs and higher access speeds for multiple processors. Thus, it would have been obvious to one of ordinary skill in the art to implement cache sharing by the DSP processors in Yan. In view of the above official notices, the AXI bus interfaces allow for the second DSP processor to access the shared cache.).
The advantage of implementing a cache hierarchy within processors is that processor data and instructions can be accessed faster compared to external accesses. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the cache elements of Volpe within the DSP processors of Yan.
Yan and Volpe failed to teach wherein the first DSP has a high requirement on real time performance for programs and data.
However, Li combined with Yan and Volpe disclosed wherein the first DSP has a high requirement on real time performance for programs and data (Li: Figure 4 elements 401-404, paragraphs 6, 51-52, and 72)(Yan: Figures 1 and 3 elements 31-32 and 100, paragraphs 31, 34, and 63)(Li disclosed a voice recognition method that allows for applications to meet high performance real-time requirements. Yan disclosed a first DSP that performs a wake-up task, which isn’t implemented to meet real-time requirements. The combination results in implementing the wake-up task in real-time, which is a higher requirement than the signal processing task.).
Li disclosed eliminating hard delays during voice recognition that allows for the advantage of applications meeting high real-time requirements. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the real-time methods of Li within the system of Yan for the above advantage.
As per claim 20:
Yan, Volpe, and Li disclosed the method according to claim 17, wherein
the external device is located in the voice chip (Yan: Figures 1 and 3 element 40, paragraphs 31, 42-43, and 66); and
the external device comprises: a Double Datarate (DDR) Synchronous Dynamic Random Access Memory (DRAM) controller and/or a Pseudo Static Random Access Memory (PSRAM) (Yan: Figures 1 and 3 element 40, paragraphs 31, 42-43, and 66)(Official notice is given that RAMs can be implemented as PSRAMs for the advantage of low power consumption, high access speeds, and lower costs. Thus, it would have been obvious to one of ordinary skill in the art to implement the memory array of Yan as a PSRAM.).
As per claim 27:
Claim 27 essentially recites the same limitations of claim 17. Claim 27 additionally recites the following limitations:
at least one processor (Yan: Figure 1 element 100, paragraph 31)(Official notice is given that general purpose processors can be added to systems for the advantage of allowing for general purpose processing outside of specialized processors. Thus, it would have been obvious to one of ordinary skill in the art to implement a general purpose processor within the speech chip of Yan.); and
a memory communicatively connected with the at least one processor (Yan: Figures 1 and 3 element 40, paragraphs 40, 42, 55, and 66);
wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform a method of voice chip implementation (Yan: Figures 1 and 3 element 40, paragraphs 40, 42, 55, and 66)(In view of the above official notice, the added processor accesses the memory subsystem for accessing program instructions.).
As per claim 30:
The additional limitation(s) of claim 30 basically recite the additional limitation(s) of claim 20. Therefore, claim 30 is rejected for the same reason(s) as claim 20.
As per claim 36:
Claim 36 essentially recites the same limitations of claim 17. Therefore, claim 36 is rejected for the same reasons as claim 17.
Claims 22, 25, 32, and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Yan et al. (U.S. 2020/0402514), in view of Volpe et al. (U.S. 2004/0064649), in view of Li et al. (U.S. 2019/0325877), in view of Official Notice, further in view of Zhao et al. (U.S. 2022/0269762) and Rofougaran et al. (U.S. 2008/0300006).
As per claim 22:
Yan, Volpe, and Li disclosed the method according to claim 17.
Yan, Volpe, and Li failed to teach the first function completed by the first DSP comprises: voice wake-up and voice recognition; and the second function completed by the second DSP comprises: an operating system, voice compression transmission, and extended wireless protocol connection.
However, Zhao combined with Yan, Volpe, and Li disclosed the first function completed by the first DSP comprises: voice wake-up and voice recognition (Zhao: Figure 1 element 110, paragraph 56)(Yan: Figures 1 and 3 element 31, paragraphs 31 and 34)(Zhao disclosed a processor/DSP chip that includes a voice wake-up module and a voice recognition module. Yan disclosed a first DSP that performs a wake-up task. The combination allows for the first DSP of Yan to include logic for voice recognition.).
The advantage of implementing voice wake-up and voice recognition in the same DSP is that all voice data can go to the same processor for faster processing, as opposed to trying to split up speech and wake-up words to different processors. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the voice recognition module of Zhao into the first DSP of Yan for the above advantage.
Yan, Volpe, Li, and Zhao failed to teach the second function completed by the second DSP comprises: an operating system, voice compression transmission, and extended wireless protocol connection.
However, Rofougaran combined with Yan, Volpe, Li, and Zhao disclosed the second function completed by the second DSP comprises: an operating system, voice compression transmission, and extended wireless protocol connection (Rofougaran: Figure 12 elements 382-384, paragraphs 107-111)(Yan: Figures 1 and 3 element 32, paragraphs 31 and 34)(Rofougaran disclosed second and third processing modules that includes performing wireless protocols, voice compression, and an operating system. Yan disclosed a second DSP that performs signal processing tasks. The combination allows for the second DSP of Yan to include logic for wireless protocols, voice compression, and an operating system. In addition, according to “In re Japikse” (181 F.2d 1019, 86 USPQ 70 (CCPA 1950)), shifting the location of parts doesn’t give patentability over prior art.).
The advantage of implementing wireless protocols and voice compression in speech chips is that it enables cloud computing of speech requests in smaller amounts of data. The advantage of implementing operating systems is that it allows users to run multiple applications at once and allows for better management of memory. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the wireless protocol, voice compression, and operating system elements of Rofougaran into the second DSP of Yan for the above advantages.
As per claim 25:
The additional limitation(s) of claim 25 basically recite the additional limitation(s) of claim 22. Therefore, claim 25 is rejected for the same reason(s) as claim 22.
As per claim 32:
The additional limitation(s) of claim 32 basically recite the additional limitation(s) of claim 22. Therefore, claim 32 is rejected for the same reason(s) as claim 22.
As per claim 35:
The additional limitation(s) of claim 35 basically recite the additional limitation(s) of claim 25. Therefore, claim 35 is rejected for the same reason(s) as claim 25.
Response to Arguments
The arguments presented by Applicant in the response, received on 1/2/2026 are partially considered persuasive.
Applicant argues for claims 17, 27, and 36:
“However, Yan only discloses the first and second processors are configured to complete different functions respectively, which does not describe the first DSP is configured to realize a first function which requires a fixed and small storage capacity and has a high requirement on real time performance for programs and data, and the second DSP is configured to realize a second function which requires a non-fixed and large storage capacity and has a low requirement on real time performance for programs and data, as defined in claim 17. Yan also does not describe the first DSP in a standard configuration and the second DSP in a non-standard configuration, as defined in claim 17.”
This argument is partially found to be persuasive for the following reason. The exclusive region of SRAM reads upon the smaller storage capacity memory for the first DSP. Additionally, the SRAM storage of the second DSP comprising both the exclusive region and shared region reads upon the larger storage capacity limitation.
The examiner agrees that Yan alone failed to teach the real-time performance limitations and configuration limitations. However, the combination of Yan and Volpe reads upon the configuration limitations. Additionally, a new ground of rejection has been given to read upon the real-time performance limitations.
Applicant argues for claims 17, 27, and 36:
“Volpe relates to digital processing systems. Volpe discloses a level one (L1) data memory 32 and an L1 instruction memory 34, which however does not describe the first DSP is configured to realize a first function which requires a fixed storage and small capacity and has a high requirement on real time performance for programs and data, and the second DSP is configured to realize a second function which requires a non-fixed and large storage capacity and has a low requirement on real time performance for programs and data, as defined in claim 17. Volpe also does not describe the first DSP in a standard configuration and the second DSP in a non-standard configuration, as defined in claim 17.”
This argument is partially found to be persuasive for the following reason. The combination of Yan and Volpe adds various elements from the DSP core of Volpe to the DSPs of Yan. The added elements to the first core reads upon the standard configuration and the different added elements to the second core reads upon the non-standard configuration.
The examiner agrees that Yan and Volpe alone failed to teach the real-time performance limitations and configuration limitations. However, a new ground of rejection has been given to read upon the real-time performance limitations.
Applicant argues for claims 17, 27, and 36:
“Li suggests modifying a processor to meet the requirements of real-time performance of the voice recognition. However, Li fails to disclose or suggest the claimed heterogeneous design of a first DSP which is configured to realize a first function requiring a fixed and small storage capacity and has a high requirement on real time performance for programs and data, and a second DSP which is configured to realize a second function requiring a non-fixed and large storage capacity and has a low requirement on real time performance for programs and data.”
This argument is partially found to be persuasive for the following reason. The combination of Yan and Li allows for the first DSP to be implemented in high real-time performance requirements for the wake-up word task. Additionally, Yan allows for no real-time performance requirements on the second DSP, which can broadly read upon the low requirement limitation. Lastly, an official notice was applied to the low requirement limitation to read upon it in a second manner due to the amendment.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The following is text cited from 37 CFR 1.111(c): In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A. PETRANEK whose telephone number is (571)272-5988. The examiner can normally be reached on M-F 8:00-4:30.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB PETRANEK/Primary Examiner, Art Unit 2183