Prosecution Insights
Last updated: April 19, 2026
Application No. 18/027,127

Display Substrate and Preparation Method therefor, and Display Apparatus

Final Rejection §112
Filed
Mar 20, 2023
Examiner
ASHBAHIAN, ERIC K
Art Unit
2891
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
BOE TECHNOLOGY GROUP CO., LTD.
OA Round
2 (Final)
67%
Grant Probability
Favorable
3-4
OA Rounds
2y 11m
To Grant
74%
With Interview

Examiner Intelligence

Grants 67% — above average
67%
Career Allow Rate
310 granted / 465 resolved
-1.3% vs TC avg
Moderate +7% lift
Without
With
+7.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
58 currently pending
Career history
523
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
51.3%
+11.3% vs TC avg
§102
17.1%
-22.9% vs TC avg
§112
25.1%
-14.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 465 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. The Examiner acknowledges the Applicant’s response to the previous rejection of claims 5-17 under 35 USC 112(b) and finds the Applicant’s arguments persuasive. Therefore, the previous rejection of claims 5-17 under 35 USC 112(b) have been withdrawn. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 1, claim 1 recites “…and multiple dummy units constituting at least one dummy row and/or at least one dummy column…” and “…form a mesh for transmitting a first initial signal, and/or, at least one unit row is provided with a second initial signal line extending along the first direction…”. The “and/or” language indicates that either both of the limitations or in the alternative only one of the limitations before and after the “and/or” is required by the claim. However, the amended in limitations are directed to features that are contained in both of the limitations on either side of the and/or. Therefore, it is unclear whether both limitations on either side of the and/or are required by the claim or whether only one of the limitations on either side of the and/or is required and the newly amended in limitations are merely required when the features selected are present. One example of this, although numerous exist throughout the claim, is that in the beginning of the claim it is stated that either a first signal line is present or and/or a second signal line is present while later in claim contains limitations directed to the first and second initial signal lines being connected to various other structural features in the claim. Thus, it is unclear whether, should one see the claim as being “or” and just the first initial signal line limitation is chosen, it is unclear whether the limitation “wherein a first electrode of the seventh transistor is connected with the second initial signal line, and a second electrode of the seventh transistor is connected with a first electrode of a light emitting device; the seventh transistor is configured to transmit a second initial voltage to the first electrode of the light emitting device to initialize a charge amount accumulated in the first electrode of the light emitting device or release the charge amount accumulated in the first electrode of the light emitting device” would be required. This issue would also be present if the “and/or” were to be replaced with “or”. Therefore, one way to clarify the language and resolve the issue is to change “and/or” to “and”. Appropriate correction should be made to clarify the language. Claims 2-18 are also rejected under 35 USC 112(b) as they depend from and include all of the limitations of claim 1. Regarding claim 19, claim 19 recites “…and multiple dummy units forming at least one dummy row and/or at least one dummy column…” and “…form a mesh for transmitting a first initial signal; and/or, forming a second initial signal line extending along the first direction…”. The “and/or” language indicates that either both of the limitations or in the alternative only one of the limitations before and after the “and/or” is required by the claim. However, the amended in limitations are directed to features that are contained in both of the limitations on either side of the and/or. Therefore, it is unclear whether both limitations on either side of the and/or are required by the claim or whether only one of the limitations on either side of the and/or is required and the newly amended in limitations are merely required when the features selected are present. One example of this, although numerous exist throughout the claim, is that in the beginning of the claim it is stated that either a first signal line is present or and/or a second signal line is present while later in claim contains limitations directed to the first and second initial signal lines being connected to various other structural features in the claim. Thus, it is unclear whether, should one see the claim as being “or” and just the first initial signal line limitation is chosen, it is unclear whether the limitation “wherein a first electrode of the seventh transistor is connected with the second initial signal line, and a second electrode of the seventh transistor is connected with a first electrode of a light emitting device; the seventh transistor is configured to transmit a second initial voltage to the first electrode of the light emitting device to initialize a charge amount accumulated in the first electrode of the light emitting device or release the charge amount accumulated in the first electrode of the light emitting device” would be required. This issue would also be present if the “and/or” were to be replaced with “or”. Therefore, one way to clarify the language and resolve the issue is to change “and/or” to “and”. Appropriate correction should be made to clarify the language. Claim 20 is also rejected under 35 USC 112(b) as it depends from and include all of the limitations of claim 19. Allowable Subject Matter Claims 1-20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 1, none of the prior art teaches, suggests or motivates one having ordinary skill in the art to have wherein at least one circuit unit of the multiple circuit units comprises a pixel drive circuit, the pixel drive circuit at least comprises multiple transistors; wherein the multiple transistors comprise a first transistor, a third transistor, and a seventh transistor; wherein a first electrode of the first transistor is connected with the first initial signal line, and a second electrode of the first transistor is connected with a second node; the first transistor is configured to transmit a first initial voltage to a control electrode of the third transistor to initialize a charge amount of the control electrode of the third transistor; wherein the control electrode of the third transistor is connected with the second node; a first electrode of the third transistor is connected with a first node, and a second electrode of the third transistor is connected with a third node; the third transistor is configured to determine an amount of a drive current flowing between a first power supply line and a second power supply line according to a potential difference between the control electrode of the third transistor and the first electrode of the third transistor; and wherein a first electrode of the seventh transistor is connected with the second initial signal line, and a second electrode of the seventh transistor is connected with a first electrode of a light emitting device; the seventh transistor is configured to transmit a second initial voltage to the first electrode of the light emitting device to initialize a charge amount accumulated in the first electrode of the light emitting device or release the charge amount accumulated in the first electrode of the light emitting device along with the other limitations of claim 1. Regarding claim 19, none of the prior art teaches, suggests or motivates one having ordinary skill in the art to have wherein at least one circuit unit of the multiple circuit units comprises a pixel drive circuit, the pixel drive circuit at least comprises multiple transistors; wherein the multiple transistors comprise a first transistor, a third transistor, and a seventh transistor; wherein a first electrode of the first transistor is connected with the first initial signal line, and a second electrode of the first transistor is connected with a second node; the first transistor is configured to transmit a first initial voltage to a control electrode of the third transistor to initialize a charge amount of the control electrode of the third transistor; wherein the control electrode of the third transistor is connected with the second node; a first electrode of the third transistor is connected with a first node, and a second electrode of the third transistor is connected with a third node; the third transistor is configured to determine an amount of a drive current flowing between a first power supply line and a second power supply line according to a potential difference between the control electrode of the third transistor and the first electrode of the third transistor; and wherein a first electrode of the seventh transistor is connected with the second initial signal line, and a second electrode of the seventh transistor is connected with a first electrode of a light emitting device; the seventh transistor is configured to transmit a second initial voltage to the first electrode of the light emitting device to initialize a charge amount accumulated in the first electrode of the light emitting device or release the charge amount accumulated in the first electrode of the light emitting device along with the other limitations of claim 19. Response to Arguments The Examiner acknowledges the Applicant’s arguments. However, the Examiner is not able to respond to the specific arguments in relation to prior art as the Applicant’s amendments introduced 112(b) issues which need to be resolved before the scope of the current claims and any relevant prior art can be determined. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC K ASHBAHIAN whose telephone number is (571)270-5187. The examiner can normally be reached 8-5:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERIC K ASHBAHIAN/Primary Examiner, Art Unit 2891
Read full office action

Prosecution Timeline

Mar 20, 2023
Application Filed
Jul 22, 2025
Non-Final Rejection — §112
Oct 23, 2025
Response Filed
Feb 25, 2026
Final Rejection — §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
67%
Grant Probability
74%
With Interview (+7.2%)
2y 11m
Median Time to Grant
Moderate
PTA Risk
Based on 465 resolved cases by this examiner. Grant probability derived from career allow rate.

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