DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/11/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “a circuit simulation apparatus”, “a sub-circuit obtaining module”, “a fitting processing module”, and “a simulation processing module” in claim 8.
Because these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 8 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The specification does not set forth adequate structure, materials, or acts, to perform the recited functionality of the means plus function claim limitations, as described in the claim interpretation section of this action. Because the claim limitation(s) have been found as indefinite based on failure of the specification to disclose sufficient structure (see rejection under 112(b) below), the claim limitation(s) necessarily lack adequate written description.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 and 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites “this one of the subcircuit modules”. “This” is a relative term that requires context to understand such reference. It is unclear what the term “this” is particularly referring to, rendering the claim indefinite.
Claim limitations “a circuit simulation apparatus”, “a sub-circuit obtaining module”, “a fitting processing module”, and “a simulation processing module” in claim 8 invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The specification does not disclose an operative algorithm for the claim elements noted herein. The apparatus is depicted in Fig. 6, showing that the apparatus is comprised of modules and the apparatus is not otherwise described in the specification so as to describe the appropriate corresponding structure. While the specification further describes the modules of the apparatus in ¶15-37 in general terms of their intended purpose/use/function, the structural mechanisms describing how the configured functionality is actually achieved is not made readily apparent. The specification fails to disclose algorithm(s) or description(s) as to how the functionality the modules are configured for is actually carried out in sufficient detail. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-9 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The following section follows the 2019 Patent Eligibility Guidance (PEG) for analyzing subject matter eligibility:
Step 1 - Statutory Category:
Step 1 of the PEG analysis entails considering whether the claimed subject matter falls within the four statutory categories of patentable subject matter identified by 35 U.S.C. 101 (process, machine, manufacture, or composition of matter).
Step 2A Prong One - Judicial exception:
In Step 2A Prong 1, examiners evaluate whether the claim recites a judicial exception (an abstract idea, law of nature, or a natural phenomenon).
Step 2A Prong Two - Integration into a practical application:
If claims recite a judicial exception, the claim requires further analysis in Step 2A Prong 2. In Step 2A Prong 2, examiners evaluate whether the claim as a whole integrates the exception into a practical application. This evaluation considers any additional elements in the claim beyond any recited judicial exceptions.
Step 2B - Significantly More:
If the additional elements identified in Step 2A Prong 2 do not integrate the exception into a practical application, then the claim is directed to the recited judicial exception and requires further analysis under Step 2B- Significantly More. This evaluation is to evaluate if the additional elements of the claim provide an inventive concept.
As noted in the MPEP 2106.05(II): The identification of the additional element(s) in the claim from Step 2A Prong 2, as well as the conclusions from Step 2A Prong 2 on the considerations discussed in MPEP 2106.05(a) -(c), (e), (f), and (h) are to be carried over. Claim limitations identified as Insignificant Extra-Solution Activities are re-evaluated to determine if the elements are beyond what is well -understood, routine, and conventional (WURC) activity, as dictated by MPEP 2106.05(II).
The additional elements are evaluated to determine if any additional element or combination of elements are other than what is well-understood, routine, conventional activity in the field, or simply append well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception, per MPEP § 2106.05(d).
Independent Claims:
Claim 1:
Step 1: Claim 1 and its dependent claims 2-8 are directed to a method which falls within one of the four statutory categories of a process.
Step 2A Prong 1: Claim 1 recites a judicial exception, noted in bold:
performing function fitting processing on the sub-circuit modules to obtain fitting functions corresponding to the sub-circuit modules; and The claim limitation can be reasonably read to entail performing a function fitting process, which is the derivation of a mathematical function that best describes a mathematical relationship. Therefore, this claim limitation includes the recitation of the judicial exception of abstract ideas as a mathematical concept. This process can also be performed in the human mind or using pen and paper as assistive physical aids. Therefore, this claim limitation includes the recitation of the judicial exception of abstract ideas of a mental process.
replacing, based on a logical relationship among the sub-circuit modules, the target circuit with the fitting functions respectively corresponding to the sub-circuit modules [[…]]The claim limitation can be reasonably read to entail evaluating a logical relationship so as to make a judgement as to a fitting function replacement for the target circuit. This task can be performed within the human mind or using a pen and paper as an assistive physical aid, for example by modifying the representation of the sub circuit to be a fitting function on a piece of paper as opposed to an alternative representation.
Therefore, the claim recites a judicial exception.
Step 2A Prong 2: Additional elements were identified and are noted in italics.
obtaining sub-circuit modules in a target circuit;- This limitation has been identified as Insignificant Extra Solution Activity (MPEP 2106.05(g)) of mere data gathering.
for simulation processing to obtain a simulation result of the target circuit. -This limitation has been identified as Mere Instructions to Apply an Exception (MPEP 2106.05(f)) for invoking the use of generic computing components as a tool to perform an existing process and for generically reciting “apply it” with regard for the judicial exception.
The courts have found that merely including instructions to implement an abstract idea on a computer or merely using a computer as a tool to perform an existing process (Mere Instructions to Apply an Exception (MPEP 2106.05(f))); and adding insignificant extra- solution activity to the judicial exception (Insignificant Extra Solution Activity (MPEP 2106.05(g))) does not integrate the judicial exception into a practical application.
When viewed independently and within the claim as a whole, the additional element does not appear to integrate the judicial exception into a practical application.
Step 2B: As discussed in Step 2A Prong 2, additional elements were identified as Insignificant Extra Solution Activity (MPEP 2106.05(g)) which must be further evaluated to determine if they are beyond WURC activities. Additional elements identified otherwise and conclusions from Step 2A Prong 2 are carried over for evaluating if the claim, as a whole, amounts to an inventive concept that is significantly more than the judicial exception:
obtaining sub-circuit modules in a target circuit – This limitation has been identified as the insignificant extra solution activity of mere data gathering, as stated above. Under broadest reasonable interpretation and when read in light of the specification, obtaining sub circuit modules may encompass receiving data over a network. Transmitting and receiving data over a network have been found by the courts to be well understood, routine, and conventional activities when claimed in a merely generic manner.
The courts have found that simply appending insignificant extra solution activities that are well-understood, routine, and conventional activities to the judicial exception does not qualify the limitations as “significantly more” than the recited judicial exception. The remaining additional elements were identified as Mere Instructions to Apply an Exception (MPEP 2106.05(f)), as stated previously. The courts have found that merely using a computer as a tool and reciting the words “apply it” with regard to the judicial exception does not qualify the limitations as “significantly more” than the recited judicial exception.
With the additional elements viewed independently and as part of the ordered combination, the claim as a whole does not appear to amount to significantly more than the recited judicial exception because the claim is using generic computing components recited at a high level of generality and functioning in their normal capacity in conjunction with well-understood, routine, and conventional activity to enable the performance of a task that can practically be performed within the human mind or using pen and paper as an assistive physical aid. Therefore, the claim does not include additional elements, alone or in combination that are sufficient to amount to significantly more than the recited judicial exception.
Conclusion: Based on this rationale, the claim has been deemed to be ineligible subject matter under 35 U.S.C. 101.
Claim 8:
Step 1: Claim 8 is directed to a circuit simulation apparatus which falls within one of the four statutory categories of a machine. Note this interpretation of an apparatus has been made in light of the claim interpretation set forth in this action.
Step 2A Prong 1: Claim 8 recites a judicial exception, noted in bold:
perform function fitting processing on the sub-circuit modules to obtain fitting functions corresponding to the sub-circuit modules; and The claim limitation can be reasonably read to entail performing a function fitting process, which is the derivation of a mathematical function that best describes a mathematical relationship. Therefore, this claim limitation includes the recitation of the judicial exception of abstract ideas as a mathematical concept. This process can also be performed in the human mind or using pen and paper as assistive physical aids. Therefore, this claim limitation includes the recitation of the judicial exception of abstract ideas of a mental process.
replace, based on a logical relationship among the sub-circuit modules, the target circuit with the fitting functions respectively corresponding to the sub-circuit modules [[…]] The claim limitation can be reasonably read to entail evaluating a logical relationship so as to make a judgement as to a fitting function replacement for the target circuit. This task can be performed within the human mind or using a pen and paper as an assistive physical aid, for example by modifying the representation of the sub circuit to be a fitting function on a piece of paper as opposed to an alternative representation.
Therefore, the claim recites a judicial exception.
Therefore, the claim recites a judicial exception.
Step 2A Prong 2: Additional elements were identified and are noted in italics.
a sub-circuit obtaining module, configured to- This limitation has been identified as Mere Instructions to Apply an Exception (MPEP 2106.05(f)) for including mere instructions to implement the abstract idea on a computer
obtain sub-circuit modules in a target circuit;- This limitation has been identified as Insignificant Extra Solution Activity (MPEP 2106.05(g)) of mere data gathering.
a fitting processing module, configured to- This limitation has been identified as Mere Instructions to Apply an Exception (MPEP 2106.05(f)) for including mere instructions to implement the abstract idea on a computer a simulation processing module, configured to- This limitation has been identified as Mere Instructions to Apply an Exception (MPEP 2106.05(f)) for including mere instructions to implement the abstract idea on a computer
for simulation processing to obtain a simulation result of the target circuit.- This limitation has been identified as Mere Instructions to Apply an Exception (MPEP 2106.05(f)) for invoking the use of generic computing components as a tool to perform an existing process and for generically reciting “apply it” with regard for the judicial exception.
The courts have found that merely including instructions to implement an abstract idea on a computer or merely using a computer as a tool to perform an existing process (Mere Instructions to Apply an Exception (MPEP 2106.05(f))); and adding insignificant extra- solution activity to the judicial exception (Insignificant Extra Solution Activity (MPEP 2106.05(g))) does not integrate the judicial exception into a practical application.
When viewed independently and within the claim as a whole, the additional element does not appear to integrate the judicial exception into a practical application.
Step 2B: As discussed in Step 2A Prong 2, additional elements were identified as Insignificant Extra Solution Activity (MPEP 2106.05(g)) which must be further evaluated to determine if they are beyond WURC activities. Additional elements identified otherwise and conclusions from Step 2A Prong 2 are carried over for evaluating if the claim, as a whole, amounts to an inventive concept that is significantly more than the judicial exception:
obtain sub-circuit modules in a target circuit;– This limitation has been identified as the insignificant extra solution activity of mere data gathering, as stated above. Under broadest reasonable interpretation and when read in light of the specification, obtaining sub circuit modules may encompass receiving data over a network. Transmitting and receiving data over a network have been found by the courts to be well understood, routine, and conventional activities when claimed in a merely generic manner.
The courts have found that simply appending insignificant extra solution activities that are well-understood, routine, and conventional activities to the judicial exception does not qualify the limitations as “significantly more” than the recited judicial exception. The remaining additional elements were identified as Mere Instructions to Apply an Exception (MPEP 2106.05(f)), as stated previously. The courts have found that merely using a computer as a tool and reciting the words “apply it” with regard to the judicial exception does not qualify the limitations as “significantly more” than the recited judicial exception.
With the additional elements viewed independently and as part of the ordered combination, the claim as a whole does not appear to amount to significantly more than the recited judicial exception because the claim is using generic computing components recited at a high level of generality and functioning in their normal capacity in conjunction with well-understood, routine, and conventional activity to enable the performance of a task that can practically be performed within the human mind or using pen and paper as an assistive physical aid. Therefore, the claim does not include additional elements, alone or in combination that are sufficient to amount to significantly more than the recited judicial exception.
Conclusion: Based on this rationale, the claim has been deemed to be ineligible subject matter under 35 U.S.C. 101.
Claim 9:
Step 1: Claim 9 is directed to an electronic device comprising a processor and memory which falls within one of the four statutory categories of a machine.
Step 2A Prong 1: Claim 9 recites a judicial exception, noted in bold:
implement the circuit simulation method according to claim 1. The claim limitation contains the judicial exception(s) and additional elements as stated above for the rejection of claim 1 and is not restated for brevity.
Therefore, the claim recites a judicial exception.
Step 2A Prong 2: Additional elements were identified and are noted in italics.
An electronic device, wherein the electronic device comprises a processor and a memory, the memory stores at least one instruction, and the at least one instruction is configured to be loaded and executed by the processor to- This limitation has been identified as Mere Instructions to Apply an Exception (MPEP 2106.05(f)) for invoking the use of generic computing components to execute the judicial exception.
The courts have found that merely including instructions to implement an abstract idea on a computer or merely using a computer as a tool to perform an abstract idea (Mere Instructions to Apply an Exception (MPEP 2106.05(f))) does not integrate the judicial exception into a practical application.
When viewed independently and within the claim as a whole, the additional element does not appear to integrate the judicial exception into a practical application.
Step 2B: As discussed in Step 2A Prong 2, no additional elements were identified as Insignificant Extra Solution Activity (MPEP 2106.05(g)) so no further evaluation is required to determine if beyond WURC activities. Additional elements identified otherwise and conclusions from Step 2A Prong 2 are carried over for evaluating if the claim, as a whole, amounts to an inventive concept that is significantly more than the judicial exception
The courts have found that merely using a generic computer as a tool to perform the judicial exception does not qualify the limitations as “significantly more” than the recited judicial exception.
With the additional elements viewed independently and as part of the ordered combination, the claim as a whole does not appear to amount to significantly more than the recited judicial exception because the claim is using generic computing components recited at a high level of generality and functioning in their normal capacity in conjunction with well-understood, routine, and conventional activity to enable the performance of a task that can practically be performed within the human mind or using pen and paper as an assistive physical aid. Therefore, the claim does not include additional elements, alone or in combination that are sufficient to amount to significantly more than the recited judicial exception.
Conclusion: Based on this rationale, the claim has been deemed to be ineligible subject matter under 35 U.S.C. 101.
Dependent Claims:
Examiner notes limitations identified as judicial exceptions are indicated in italicized bold and limitations identified as additional elements are indicated using italics.
Claim 2
Step 1: Regarding dependent claim 2, the judicial exception of independent claim 1 is further incorporated. The claim falls within the corresponding statutory category as stated previously.
Step 2A Prong 1: Claim 2 additionally recites the limitation performing the function fitting processing on this one of the sub-circuit modules to obtain the fitting function corresponding to this one of the sub-circuit modules., which can reasonably be read to entail performing a function fitting process. This task can be performed within the human mind or using a pen and paper as an assistive physical aid. Therefore, this claim limitation includes the recitation of the judicial exception of abstract ideas of a mental process. Furthermore, function fitting is the derivation of a mathematical function that best describes a mathematical relationship and accordingly the claim limitation includes the recitation of the judicial exception of abstract ideas as a mathematical concept.
Step 2A Prong 2: Claim 2 additionally recites the limitation obtaining a simulation result of each of the sub-circuit modules; and. This limitation has been identified as Insignificant Extra Solution Activity (MPEP 2106.05(g)). The claim further recites when a confirmation operation for the simulation result of any one of the sub-circuit modules is received, which has been identified as Insignificant Extra Solution Activity (MPEP 2106.05(g)).The courts have ruled appending insignificant extra solution activity to the judicial exception does not integrate the judicial exception into a practical application. With the additional element viewed in conjunction with the other limitations, the claim as a whole does not appear to integrate the judicial exception into a practical application.
Step 2B: Because the elements were identified as Insignificant Extra Solution Activity (MPEP 2106.05(g)), they require further consideration to evaluate if the elements are beyond well understood, routine, and conventional activities. Under broadest reasonable interpretation and when read in light of the specification, these limitations encompass receiving data over a network. The courts have found that the computer functionalities of transmitting and receiving data over a network are well understood, routine, and conventional when claimed in a merely generic manner such as in the claims. The courts have found that limitations that amount to appending well understood, routine, and conventional activities to the judicial exception are not enough to qualify the claim as significantly more than the abstract idea. Therefore, the claim does not include additional elements, alone or in the ordered combination that are sufficient to amount to significantly more than the recited judicial exception.
This claim is not eligible subject matter under 35 U.S.C. 101.
Claim 3
Step 1: Regarding dependent claim 3, the judicial exception of independent claim 1 is further incorporated. The claim falls within the corresponding statutory category as stated previously.
Step 2A Prong 1: Claim 3 additionally recites the limitation determining the candidate sub-circuit module as a sub-circuit module in the target circuit; and, which can reasonably be read to entail making a judgment as to a candidate sub circuit module. This task can be performed within the human mind or using a pen and paper as an assistive physical aid. Therefore, this claim limitation includes the recitation of the judicial exception of abstract ideas of a mental process. The claim further recites the step of performing function fitting processing on the sub-circuit modules to obtain fitting functions corresponding to the sub-circuit modules comprises: [[…]]performing the function fitting processing on the sub-circuit modules to obtain the fitting functions corresponding to the sub-circuit modules which has been previously described as reciting both a mental process and a mathematical concept in at least the independent claim upon which this claim depends (see above- rejection of claim 1). Therefore, this claim limitation includes the recitation of the judicial exception of abstract ideas of a mental process and mathematical concepts.
Step 2A Prong 2: Claim 3 additionally recites the limitations:
obtaining a simulation result of a candidate sub-circuit module. – This claim limitation has been identified as Insignificant Extra Solution Activity (MPEP 2106.05(g))
wherein the candidate sub-circuit module is an unverified sub-circuit module for the target circuit; and -This claim limitation has been identified as Field of Use and Technological Environment (MPEP 2106.05(h)) for generally linking the use of the judicial exception to a particular field of use or technological environment
when a confirmation operation for the simulation result of the candidate sub-circuit module is received, -This claim limitation has been identified as Insignificant Extra Solution Activity (MPEP 2106.05(g))
when a simulation operation for the target circuit is received,- This claim limitation has been identified as Insignificant Extra Solution Activity (MPEP 2106.05(g))
The courts have ruled appending insignificant extra solution activity to the judicial exception and generally linking the use of the judicial exception to a particular field of use and technological environment does not integrate the judicial exception into a practical application. With the additional element viewed in conjunction with the other limitations, the claim as a whole does not appear to integrate the judicial exception into a practical application.
Step 2B: Because elements were identified as Insignificant Extra Solution Activity (MPEP 2106.05(g)), they require additional evaluation to determine if the elements are beyond WURC activities. Under broadest reasonable interpretation and when read in light of the specification, these elements encompass receiving data over a network. The courts have found that the computer functions of transmitting and receiving data over a network are well understood, routine, and conventional activities when claimed in a merely generic manner. The courts have found that limitations that amount to appending well understood, routine, and conventional activities to the judicial exception and generally linking the use of the judicial exception to a particular technological environment are not enough to qualify the claim as significantly more than the abstract idea. Therefore, the claim does not include additional elements, alone or in the ordered combination that are sufficient to amount to significantly more than the recited judicial exception.
This claim is not eligible subject matter under 35 U.S.C. 101.
Claim 4
Step 1: Regarding dependent claim 4, the judicial exception of independent claim 1 is further incorporated. The claim falls within the corresponding statutory category as stated previously.
Step 2A Prong 1: Claim 4 additionally recites the limitation and constructing, based on the sub-circuit parameters, a sub-circuit matrix corresponding to each of the sub-circuit modules;, which can reasonably be read to entail creating a matrix corresponding to the parameters. This task can be performed within the human mind or using a pen and paper as an assistive physical aid, for example by evaluating the parameter values and writing down a corresponding matrix on a piece of paper. Furthermore, the creation of a matrix is the formation of a data representation indicative of mathematical relationships. Therefore, this claim limitation includes the recitation of the judicial exception of abstract ideas as a mathematical concept. The claim further recites processing sample input data based on the sub-circuit matrix to obtain predicted output data corresponding to the sample input data; and which can reasonably be read to entail evaluating the matrix in terms of sample input data to derive output predictions. This evaluation and judgment task can be performed within the human mind or using a pen and paper as an assistive physical aid. Therefore, this claim limitation includes the recitation of the judicial exception of abstract ideas of a mental process. And further the claim recites performing fitting by using a linear regression method based on the sample input data and the predicted output data corresponding to the sample input data to obtain the fitting function corresponding to each of the sub-circuit modules which is the recitation of performing a linear regression as mathematical calculations on data. Therefore, this claim limitation includes the recitation of the judicial exception of abstract ideas as a mathematical concept. Further this may be performed practically in the human mind or using assistive aids such as pen and paper and is likewise considered an abstract idea of mental process.
Step 2A Prong 2: Claim 4 additionally recites the limitation obtaining sub-circuit parameters of each of the sub-circuit modules,. This limitation has been identified as Insignificant Extra Solution Activity (MPEP 2106.05(g)). The courts have ruled appending insignificant extra solution activity to the judicial exception does not integrate the judicial exception into a practical application. With the additional element viewed in conjunction with the other limitations, the claim as a whole does not appear to integrate the judicial exception into a practical application.
Step 2B: Because an additional element was identified as Insignificant Extra Solution Activity (MPEP 2106.05(g)), it requires further evaluation to determine if it is beyond WURC activity. Under broadest reasonable interpretation and when read in light of the specification, obtaining parameters encompasses receiving data over a network. This computer function has been found by the courts to be well understood, routine, and conventional when claimed in a merely generic manner. The courts have found that limitations that amount to appending well understood routine and conventional activities with the recited exception(s) are not enough to qualify the claim as significantly more than the abstract idea. Therefore, the claim does not include additional elements, alone or in the ordered combination that are sufficient to amount to significantly more than the recited judicial exception.
This claim is not eligible subject matter under 35 U.S.C. 101.
Claim 5
Step 1: Regarding dependent claim 5, the judicial exception of independent claim 1 is further incorporated. The claim falls within the corresponding statutory category as stated previously.
Step 2A Prong 1: Claim 5 additionally recites the limitation performing sampling within the input data range corresponding to the sub-circuit matrix to obtain the sample input data which can reasonably be read to entail evaluating data in a range and making a judgment as to which data is to be used. This task can be performed within the human mind or using a pen and paper as an assistive physical aid. Therefore, this claim limitation includes the recitation of the judicial exception of abstract ideas of a mental process. The claim further recites the evaluation of data with regard for a range, wherein a range is understood as a mathematical relationship characterizing the bounds of applicable data. Therefore, this claim limitation includes the recitation of the judicial exception of abstract ideas as a mathematical concept.
Step 2A Prong 2: Claim 5 additionally recites the limitation obtaining an input data range corresponding to the sub-circuit matrix; and. This limitation has been identified as Insignificant Extra Solution Activity (MPEP 2106.05(g)) The courts have ruled appending insignificant extra solution activity to the judicial exception does not integrate the judicial exception into a practical application. With the additional element viewed in conjunction with the other limitations, the claim as a whole does not appear to integrate the judicial exception into a practical application.
Step 2B: Because an additional element was identified as Insignificant Extra Solution Activity (MPEP 2106.05(g)), it requires further evaluation to determine if it is beyond WURC activity. Under broadest reasonable interpretation and when read in light of the specification, obtaining a range encompasses receiving data over a network. This computer function has been found by the courts to be well understood, routine, and conventional when claimed in a merely generic manner. The courts have found that limitations that amount to appending well understood routine and conventional activities with the recited exception(s) are not enough to qualify the claim as significantly more than the abstract idea. Therefore, the claim does not include additional elements, alone or in the ordered combination that are sufficient to amount to significantly more than the recited judicial exception.
This claim is not eligible subject matter under 35 U.S.C. 101.
Claim 6
Step 1: Regarding dependent claim 6, the judicial exception of independent claim 1 is further incorporated. The claim falls within the corresponding statutory category as stated previously.
Step 2A Prong 1: Claim 6 additionally recites the limitation equally dividing the input data range based on the matrix order of the sub-circuit matrix, and determining data values obtained by the equal dividing as the sample input data., which can reasonably be read to entail evaluating a matrix order to divide the input data range and subsequently evaluating the divided data to make a judgment of data values. This task can be performed within the human mind or using a pen and paper as an assistive physical aid. Therefore, this claim limitation includes the recitation of the judicial exception of abstract ideas of a mental process. Furthermore, because the claim recites the equal division of a range, the claim further recites the judicial exception of abstract ideas as mathematical concepts.
Step 2A Prong 2: Claim 6 additionally recites the limitation obtaining a matrix order corresponding to the sub-circuit matrix; and. This limitation has been identified as Insignificant Extra Solution Activity (MPEP 2106.05(g)) .The courts have ruled appending insignificant extra solution activity to the judicial exception does not integrate the judicial exception into a practical application. With the additional element viewed in conjunction with the other limitations, the claim as a whole does not appear to integrate the judicial exception into a practical application.
Step 2B: Because an additional element was identified as Insignificant Extra Solution Activity (MPEP 2106.05(g)), it requires further evaluation to determine if it is beyond WURC activity. Under broadest reasonable interpretation and when read in light of the specification, obtaining a matrix order encompasses receiving data over a network. This computer function has been found by the courts to be well understood, routine, and conventional when claimed in a merely generic manner. The courts have found that limitations that amount to appending well understood routine and conventional activities with the recited exception(s) are not enough to qualify the claim as significantly more than the abstract idea. Therefore, the claim does not include additional elements, alone or in the ordered combination that are sufficient to amount to significantly more than the recited judicial exception.
This claim is not eligible subject matter under 35 U.S.C. 101.
Claim 7
Step 1: Regarding dependent claim 7, the judicial exception of independent claim 1 is further incorporated. The claim falls within the corresponding statutory category as stated previously.
Step 2A Prong 1: Claim 7 additionally recites the limitation processing input data corresponding to an ith sub-circuit module by using a fitting function corresponding to the ith sub-circuit module to obtain output data corresponding to the ith sub-circuit module, wherein the ith sub-circuit module and an (i+l)th sub-circuit module have a logical connection relationship; and processing, by using a fitting function corresponding to the (i+l)th subcircuit module, the output data corresponding to the ith sub-circuit module as input data corresponding to the (i+l)th sub-circuit module to obtain output data corresponding to the (i+l)th sub-circuit module., which can reasonably be read to entail evaluating data with regard to a fitting function to derive output data and further using the fitting function for another subcircuit to derive more output data. This task can be performed within the human mind or using a pen and paper as an assistive physical aid. Therefore, this claim limitation includes the recitation of the judicial exception of abstract ideas of a mental process. Further, because the claim recites the use of a fitting function to process the data, the claim further recites a mathematical relationship between the fitting function and the data. Therefore, this claim limitation includes the recitation of the judicial exception of abstract ideas as a mathematical concept.
Step 2A Prong 2 & Step 2B: Claim 7 does not recite any additional elements that would integrate the judicial exception(s) into a practical application nor amount to significantly more than the recited exception(s).
This claim is not eligible subject matter under 35 U.S.C. 101.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3 and 7-9 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Fischer et al (US 2021/0390243 A1), hereinafter referred to as Fischer.
Regarding claim 1, Fischer discloses A circuit simulation method, wherein the method comprises: ((Fischer, ¶16) " Another aspect of the present disclosure relates to a method comprising receiving a first set of sub-circuit physical parameters for electrical components of a subcircuit, and an indication of a first process technology, determining a first variation of sub-circuit physical parameters for the electrical components of the structural subcircuit, the first variation including at least one sub-circuit physical parameter that vary from sub-circuit physical parameters of the first set of sub-circuit physical parameters, simulating the first variation of sub-circuit physical parameters in the first process technology to generate a first set of sub-circuit performance parameter values associated with the first variation, training a machine learning (ML) model of the structural sub-circuit based on a set of variations, the set of variations including the first variation and set of sub-circuit physical parameters associated with the first variation, for the first process technology, and storing the trained ML model.")
obtaining sub-circuit modules in a target circuit; ((Fischer, ¶116) "At block 1202, a data object representing a circuit for a first process technology may be received, the circuit including a first sub-circuit, the first sub-circuit including a first electrical component and a second electrical component, the first electrical component and the second electrical component arranged in a first topology."); ((Fischer, ¶61) "In this example, a representation 514 of a circuit, such as a netlist describing the circuit, may be parsed to identify one or more circuit blocks at block 516. A circuit block may be parsed to identify sub-circuits of the circuit block at block 518.")
performing function fitting processing on the sub-circuit modules to obtain fitting functions corresponding to the sub-circuit modules; and ML models corresponding to each sub-circuit are trained and obtained via creation (wherein training is understood to be a function fitting process since the model is being described as potentially being over-fitted and further described as corresponding to having nodes representative of mathematical functions that are adjusted via weighting) ((Fischer, ¶126) " At block 1608, a machine learning (ML) model of the structural sub-circuit is trained based on a set of variations, the set of variations including the first variation and set of sub-circuit physical parameters associated with the first variation, for the first process technology. [[…]] At block 1610, the trained ML model is stored. In certain cases, the library of trained ML models includes a trained ML model for each sub-circuit of a set of predetermined sub-circuits. In certain cases, in the library of trained ML models, each trained ML model is associated with a specific sub-circuit and each trained ML model may differ from other trained ML models in the library of trained ML models."). ((Fischer, ¶58) "A ML model for each sub-circuit of the known sub-circuits ( or those sub-circuits supported by the particular embodiment) may be trained at block 504 to create a set of trained ML models for a process technology."); ((Fischer, ¶81) "The ML model 812 may use a variety of ML modeling techniques, including linear regression models, large margin classifiers (e.g., support vector machines), principal component analysis, tree-based techniques (e.g., random forest or gradient boosted trees), or neural networks. Linear regression models may be ML models which assumes a linear relationship between input parameters and output. [[…]] Neural network ML modeling techniques may include fully connected (where every neuron of a layer is connected to every other node of the layer), fully connected with regularization (where a regularization function is added to a fully connected neural network to help avoid over fitting), and fully connected with dropout (which removes nodes to simplify the network) and optimizers, such as adaptive moment estimation optimizer enhanced neural networks (which reduces data parameters of the network using gradient descent algorithms)."); ((Fischer, ¶102) "The example neural network ML model 1000 is a simplified example presented to help understand how such neural network ML model 1000 may be trained. It may be understood that each implementation of a ML model may be trained or tuned in a different way, depending on a variety of factors including, but not limited to, a type of ML model being used, parameters being used for the ML model, relationships as among the parameters, desired speed of training, etc. In this simplified example, sub-circuit physical parameters values ofW and Lare parameter inputs 1002 and 1004 to the ML model 1000. Each layer (e.g., first layer 1006, second layer 1008, and third layer 1010) includes a plurality of nodes ( e.g., neurons) and generally represents a set of operations performed on the parameters, such as a set of matrix multiplications. For example, each node represents a mathematical function that takes, as input (aside from the nodes of the first layer 1006), output from a previous layer and a weight. The weight is typically adjusted during ML model training and fixed after the ML model training. The specific mathematical function of the node can vary depending on ML model implementation.")
replacing, based on a logical relationship among the sub-circuit modules, the target circuit with the fitting functions respectively corresponding to the sub-circuit modules for simulation processing to obtain a simulation result of the target circuit. A new circuit may be converted from an original circuit, as a replacement, wherein the subcircuits of the converted circuit are converted by using a corresponding trained ML model for each subcircuit to identify alternative topologies. ((Fischer, ¶61) "At block 522, a representation of the sub-circuit, such as a netlist, is created for each identified sub-circuit based on the predicted certain sub-circuit physical parameters for components of each sub-circuit and the sub-circuits may be connected into circuit blocks, which in tum are connected to form an overall circuit, thus converting the original circuit to a new circuit in the second process technology. At block 524, this new circuit may be simulated to verify that the new circuit meets the design specification, and if the design specifications are met, the representation of the new circuit may be output at block 526."); The conversion (replacement) process is subject to a formatting tool that accounts for connections between subcircuit components, as logical relationships ((Fischer, ¶96) "Formatting tool 830 may correct formatting, connection drawing, and/or mapping issues that may arise during the conversion. In certain cases, the formatting tool 830 may extract certain formatting, connection, and or mapping information from the original circuit design 802 for use to correct the converted data object (e.g., netlist). In certain cases, this netlist may be connected to or appended on another netlist, such as a netlist for a converted version of the circuit block and other circuit blocks, if needed, to output a data object representing a new circuit 832 for the second process technology". The converted circuit is subject to simulation ((Fischer, ¶45) "After the electronic components are converted to the target process technology, the completed circuit may be simulated on circuit simulation software, such as simulation program with integrated circuit emphasis (SPICE), as against the design specifications.");
Regarding claim 2, Fischer discloses The method according to claim 1, as stated above. Fischer further discloses wherein the step of performing function fitting processing on the sub-circuit modules to obtain fitting functions corresponding to the sub-circuit modules comprises: as the training of machine learning models corresponding to each subcircuit. See Fischer Figure 16 depicting the training of ML models per each sub circuit including the simulation of variants of sub-circuits. The ML model is described as undergoing/comprising a linear regression, as a function fitting process. ((Fischer, ¶81) " The ML model 812 may use a variety of ML modeling techniques, including linear regression models, large margin classifiers (e.g., support vector machines), principal component analysis, tree-based techniques (e.g., random forest or gradient boosted trees), or neural networks. Linear regression models may be ML models which assumes a linear relationship between input parameters and output.");((Fischer, ¶111) " In certain cases, the interaction may be based on mathematical functions applied as between parameters in a node of a neural network. A linear regression may then be performed on the parameters of the second set 1104. The linear regression is a linear function which attempts to model a relationship between the parameters of the second set 1104 and results of the linear regression may be compared to expected results of the ML model (e.g., as determined by a circuit simulation of the sub-circuit topology being modeled by the ML model)."); ((Fischer, ¶126) " In certain cases, the ML model of the sub-circuit comprises one of a linear regression, large margin classifier, principle component analysis, tree based, or neural network machine learning model.")
obtaining a simulation result of each of the sub-circuit modules; and ((Fischer, ¶125) "At block 1606, the first variation of sub-circuit physical parameters in the first process technology is simulated to generate a first set of sub-circuit performance parameter values associated with the first variation. For example, for a particular sub-circuit, sets of physical parameters may be generated by simulating the particular sub-circuit with sets of physical parameter values")
when a confirmation operation for the simulation result of any one of the sub-circuit modules is received, performing the function fitting processing on this one of the sub-circuit modules to obtain the fitting function corresponding to this one of the sub-circuit modules. Parameters are compared to simulation results and evaluated for accuracy (as an operation to confirm validity) ((Fischer, ¶113) "The resulting parameters in the fourth set 1110 may be compared to the expected results (e.g., obtained via circuit simulations) to determine an accuracy of the resulting parameters in the fourth set 1110. If the accuracy meets a threshold accuracy value, then the fourth set 1110 of parameters may be used as input parameters for the ML model for the sub-circuit. The threshold accuracy value may be determined in any way, for example, by experimentation, experience, etc."). When the accuracy is determined to not have been met (as the receipt of a confirmation of not satisfying comparison to the simulation results), the ML model may be further tuned via training, wherein the training fits the model to the data ((Fischer, ¶115) "In certain cases, if the desired threshold accuracy value is not met by threshold stepwise selection, threshold stepwise selection may be applied in conjunction with stacked models to help improve accuracy. A stacked model uses information derived from an initial model, such as the final set 1108 of parameters output from threshold stepwise selection, as inputs to help guide subsequent modeling techniques. For example, if after applying a predetermined number of rounds of threshold stepwise selection, the desired threshold accuracy value is not met, the parameters selected during the last round of threshold stepwise selection may be used as used as input to a ML model, such as a neural network trained on the sub-circuit physical parameters and simulated sub-circuit performance parameters. This ML model may then be further tuned using any known ML tuning technique. For example, Bayesian hyperparameter optimization may also be applied to the ML model to tune the hyperparameters of the ML model. Bayesian hyperparameter optimization is a technique for determining hyperparameters of a ML model based on a probability model of how a hyperparameter influences the accuracy of the ML model as different hyperparameters are adjusted based on a validation score. The validation score may be determined by adjusting the hyperparameter of the ML model, training the ML model to generate predictions of the ML model with the adjusted hyperparameter, and evaluating these predictions against expected results to calculate the validation score."); ((Fischer, ¶131) "For example, where the sufficient level of accuracy has not been met and the repeating ended after each variable in the original set of variables has been interacted a predetermined number of times, a final set of candidate variables may be used to train another ML model.") See also Fischer Figure 17B showing the determination and transmission of yes/no confirmation from block 1716. The ML models each correspond to a simulated subcircuit topology ((Fischer, ¶83) "In certain cases, the set of sub-circuit physical parameters, sub-circuit operational parameters, and generated sub-circuit performance parameters resulting from the simulations may be used to train a ML model 504 corresponding to the simulated sub-circuit topology."); ((Fischer, ¶102) "The example neural network ML model 1000 is a simplified
example presented to help understand how such neural network ML model 1000 may be trained. It may be understood that each implementation of a ML model may be trained or tuned in a different way, depending on a variety of factors including, but not limited to, a type of ML model being used, parameters being used for the ML model, relationships as among the parameters, desired speed of training, etc. In this simplified example, sub-circuit physical parameters values ofW and Lare parameter inputs 1002 and 1004 to the ML model 1000. Each layer (e.g., first layer 1006, second layer 1008, and third layer 1010) includes a plurality of nodes ( e.g., neurons) and generally represents a set of operations performed on the parameters, such as a set of matrix multiplications. For example, each node represents a mathematical function that takes, as input (aside from the nodes of the first layer 1006), output from a previous layer and a weight. The weight is typically adjusted during ML model training and fixed after the ML model training. The specific mathematical function of the node can vary depending on ML model implementation.")
Regarding claim 3, Fischer discloses The method according to claim 1, wherein the step of obtaining sub-circuit modules in a target circuit comprises: as stated previously and further discloses
obtaining a simulation result of a candidate sub-circuit module, wherein the candidate sub-circuit module is an unverified sub-circuit module for the target circuit; and Subcircuit topologies may be simulated, wherein the topologies may vary according to candidate parameters ((Fischer, ¶80) "For example, a first sub-circuit topology of the known sub-circuit topologies may be simulated 502 using a variety of sub-circuit physical parameters and operational parameters for the first process technology. This simulation may be performed using a circuit simulator, such as a SPICE simulation. The simulation generates a set of sub-circuit performance parameters corresponding to variants of the sub-circuit physical parameters and operational parameters for the first topology in the first technology process. The ML model for the first subcircuit topology may then be trained 504 using the variants of the sub-circuit physical parameters and operational parameters to predict the corresponding sub-circuit performance parameter for that ML model for the first process technology. The simulated sub-circuits 502 and the results of the simulated sub-circuits 502 may be stored and represented in a data object."); ((Fischer, ¶82) "A particular sub-circuit topology may then be simulated 502 across a selection of the practical range of sub-circuit physical parameters ( e.g., physical parameters) and sub-circuit opera tional parameters to generate sub-circuit performance parameters (e.g., performance parameters) associated with the particular sub-circuit topology for the first process technology. For example, a particular circuit mirror topology, such as that shown in FIG. 4, may be simulated 502 with varying combinations of sub-circuit physical parameters and sub-circuit operational parameters, such as W/L of electrical components, input and output currents, impedance, operating region (e.g., conditions), N-type/P-type, etc. to generate sub-circuit performance parameters (e.g., performance parameters) associated with the respective physical parameters and respective sub-circuit operational parameters."). Expected results corresponding to a subcircuit with candidate parameters are obtained from circuit simulations ((Fischer, ¶113) "The resulting parameters in the fourth set 1110 may be compared to the expected results (e.g., obtained via circuit simulations) to determine an accuracy of the resulting parameters in the fourth set 1110."). The accuracy evaluation serves as the verification of the sub-circuit, wherein the candidate parameters for a subcircuit are not verified until the accuracy evaluation has been undergone ((Fischer, ¶129) "At block 1728, the accuracy of the candidate set of parameters may be determined based on the set of expected parameter values. At block 1730, the accuracy of the candidate set of parameters may be compared to a predetermined accuracy level. At block 1732, if the accuracy of the second candidate set of parameters has reached the predetermined accuracy, the candidate set of parameters are output at block 1718.")
when a confirmation operation for the simulation result of the candidate sub-circuit module is received, determining the candidate sub-circuit module as a sub-circuit module in the target circuit; and . Parameters are compared to simulation results and evaluated for accuracy (as an operation to confirm validity) ((Fischer, ¶113) "The resulting parameters in the fourth set 1110 may be compared to the expected results (e.g., obtained via circuit simulations) to determine an accuracy of the resulting parameters in the fourth set 1110. If the accuracy meets a threshold accuracy value, then the fourth set 1110 of parameters may be used as input parameters for the ML model for the sub-circuit. The threshold accuracy value may be determined in any way, for example, by experimentation, experience, etc."). When the accuracy is determined to have been reached (as the receipt of a confirmation of satisfying the comparison to the simulation results), the candidate set of parameters are output ((Fischer, ¶129) "At block 1732, if the accuracy of the second candidate set of parameters has reached the predetermined accuracy, the candidate set of parameters are output at block 1718"). The identified (determined) subcircuit is converted according to the candidate set of parameters so as to form the target overall circuit ((Fischer, ¶61) "At block 522, a representation of the sub-circuit, such as a netlist, is created for each identified sub-circuit based on the predicted certain sub-circuit physical parameters for components of each sub-circuit and the sub-circuits may be connected into circuit blocks, which in tum are connected to form an overall circuit, thus converting the original circuit to a new circuit in the second process technology.")
the step of performing function fitting processing on the sub-circuit modules to obtain fitting functions corresponding to the sub-circuit modules comprises: (as given above in claim 1)
when a simulation operation for the target circuit is received, performing the function fitting processing on the sub-circuit modules to obtain the fitting functions corresponding to the sub-circuit modules. A target circuit may be simulated in SPICE software and then the ML is trained whereby training entails a mathematical function fitting per nodes of the ML ((Fischer, ¶90) "For example, the first sub-circuit topology of the known subcircuit topologies may be simulated 508 using a variety of sub-circuit physical parameters and operational parameters for the second process technology. This simulation may be performed using a circuit simulator, such as a SPICE simulation. The simulation generates a set of sub-circuit performance parameters corresponding to each variant of the sub-circuit physical parameters and sub-circuit operational parameters for the first topology in the second process
technology. The ML model 822 for the first sub-circuit topology may then be trained 510 using the variants of the sub-circuit physical parameters and operational parameters to predict the corresponding sub-circuit performance parameter for that ML model for the second process technology"); ((Fischer, ¶102) "The example neural network ML model 1000 is a simplified
example presented to help understand how such neural network ML model 1000 may be trained. It may be understood that each implementation of a ML model may be trained or tuned in a different way, depending on a variety of factors including, but not limited to, a type of ML model being used, parameters being used for the ML model, relationships as among the parameters, desired speed of training, etc. In this simplified example, sub-circuit physical parameters values ofW and Lare parameter inputs 1002 and 1004 to the ML model 1000. Each layer (e.g., first layer 1006, second layer 1008, and third layer 1010) includes a plurality of nodes ( e.g., neurons) and generally represents a set of operations performed on the parameters, such as a set of matrix multiplications. For example, each node represents a mathematical function that takes, as input (aside from the nodes of the first layer 1006), output from a previous layer and a weight. The weight is typically adjusted during ML model training and fixed after the ML model training. The specific mathematical function of the node can vary depending on ML model implementation.")
Regarding claim 7, Fischer discloses The method according to claim 1,as stated above and further discloses wherein the step of replacing, based on a logical relationship among the sub-circuit modules, the target circuit with the fitting functions respectively corresponding to the sub-circuit modules for simulation processing to obtain a simulation result of the target circuit comprises: A new circuit may be converted from an original circuit, as a replacement, wherein the subcircuits of the converted circuit are converted by using a corresponding trained ML model for each subcircuit to identify alternative topologies. ((Fischer, ¶61) "At block 522, a representation of the sub-circuit, such as a netlist, is created for each identified sub-circuit based on the predicted certain sub-circuit physical parameters for components of each sub-circuit and the sub-circuits may be connected into circuit blocks, which in tum are connected to form an overall circuit, thus converting the original circuit to a new circuit in the second process technology. At block 524, this new circuit may be simulated to verify that the new circuit meets the design specification, and if the design specifications are met, the representation of the new circuit may be output at block 526."); The conversion (replacement) process is subject to a formatting tool that accounts for connections between subcircuit components, as logical relationships ((Fischer, ¶96) "Formatting tool 830 may correct formatting, connection drawing, and/or mapping issues that may arise during the conversion. In certain cases, the formatting tool 830 may extract certain formatting, connection, and or mapping information from the original circuit design 802 for use to correct the converted data object (e.g., netlist). In certain cases, this netlist may be connected to or appended on another netlist, such as a netlist for a converted version of the circuit block and other circuit blocks, if needed, to output a data object representing a new circuit 832 for the second process technology". The converted circuit is subject to simulation ((Fischer, ¶45) "After the electronic components are converted to the target process technology, the completed circuit may be simulated on circuit simulation software, such as simulation program with integrated circuit emphasis (SPICE), as against the design specifications.");
processing input data corresponding to an ith sub-circuit module by using a fitting function corresponding to the ith sub-circuit module to obtain output data corresponding to the ith sub-circuit module, wherein the ith sub-circuit module and an (i+l)th sub-circuit module have a logical connection relationship; and For each subcircuit, parameters are input into an ML model (as the fitting function as described in claim 1) wherein the ML corresponds to a first process technology as a first subcircuit and wherein the ML model outputs predictions. ((Fischer, ¶61) " In this example, a representation 514 of a circuit, such as a netlist describing the circuit, may be parsed to identify one or more circuit blocks at block 516. A circuit block may be parsed to identify sub-circuits of the circuit block at block 518. A sub-circuit type may also be identified. At block 520 for each identified sub-circuit, sub-circuit physical parameters for components of the sub-circuit are identified and input to a ML model corresponding to the identified sub-circuit for the first process technology ( e.g., stored in ML model library 506) to predict certain subcircuit performance parameters."). The subcircuits of the circuit block are described as being defined per a netlist that describes the circuit, thereby indicating a logical relationship. ((Fischer, ¶71) " A netlist is an electronic representation of electrical components in a circuit and the connection between the electrical components in the circuit. In certain embodiments, the netlist may also include nodes that represent the connection between a first electrical component and a second electrical component in the circuit. The netlist may include multiple circuit blocks and may organize the circuit by each circuit block. In certain cases, the netlist, and corresponding circuit blocks, may be organized into portions that perform a particular task or function.")
processing, by using a fitting function corresponding to the (i+l)th subcircuit module, the output data corresponding to the ith sub-circuit module as input data corresponding to the (i+l)th sub-circuit module to obtain output data corresponding to the (i+l)th sub-circuit module. The output of the first ML model is used as input to the second ML model, wherein the second ML model corresponds to a second process technology as a subcircuit and wherein the ML model makes further output predictions ((Fischer, ¶61) " These predicted certain sub-circuit performance parameters are then input to a second ML model corresponding to the identified sub-circuit for the second process technology ( e.g., stored in ML model library 512) to predict certain sub-circuit physical parameters for components of the sub-circuit in the second process technology. At block 522, a representation of the sub-circuit, such as a netlist, is created for each identified sub-circuit based on the predicted certain sub-circuit physical parameters for components of each sub-circuit and the sub-circuits may be connected into circuit blocks, which in tum are connected to form an overall circuit, thus converting the original circuit to a new circuit in the second process technology.")
Regarding claim 8, Fischer discloses A circuit simulation apparatus, wherein the apparatus comprises: ((Fischer, ¶135) "Processor 1805 may be configured to execute the stored instructions or process steps in order to perform instructions or process steps to transform the computing device into a non-generic, particular, specially programmed machine or apparatus.")
a sub-circuit obtaining module, configured to obtain sub-circuit modules in a target circuit; ((Fischer, ¶70) " FIG. 8 is a system diagram illustrating an overview of technique 800 for designing a new analog circuit from an original analog circuit, in accordance with aspects of the present disclosure. In certain cases, technique 800 may be implemented in software as one or more software programs which may include various modules."); See Figure 8, blocks 803 and 804. ((Fischer, ¶71) "A circuit block parser 803 may parse the first data object to identify individual circuit blocks. A circuit block may be further parsed by a sub-circuit parser 804 to identify sub-circuits of the circuit block based on a set of sub-circuit parsing rules 806. In other embodiments, technique 800 may identify sub-circuits using the original circuit represented by the first data object"). ((Fischer, ¶116) "At block 1202, a data object representing a circuit for a first process technology may be received, the circuit including a first sub-circuit, the first sub-circuit including a first electrical component and a second electrical component, the first electrical component and the second electrical component arranged in a first topology.");
a fitting processing module, configured to perform function fitting processing on the sub-circuit modules to obtain fitting functions corresponding to the sub-circuit modules; and ((Fischer, ¶70) " FIG. 8 is a system diagram illustrating an overview of technique 800 for designing a new analog circuit from an original analog circuit, in accordance with aspects of the present disclosure. In certain cases, technique 800 may be implemented in software as one or more software programs which may include various modules."); ML models corresponding to each sub-circuit are trained and obtained via creation (wherein training is understood to be a function fitting process since the model is being described as potentially being over-fitted and further described as corresponding to having nodes representative of mathematical functions that are adjusted via weighting) ((Fischer, ¶126) " At block 1608, a machine learning (ML) model of the structural sub-circuit is trained based on a set of variations, the set of variations including the first variation and set of sub-circuit physical parameters associated with the first variation, for the first process technology. [[…]] At block 1610, the trained ML model is stored. In certain cases, the library of trained ML models includes a trained ML model for each sub-circuit of a set of predetermined sub-circuits. In certain cases, in the library of trained ML models, each trained ML model is associated with a specific sub-circuit and each trained ML model may differ from other trained ML models in the library of trained ML models."). ((Fischer, ¶58) "A ML model for each sub-circuit of the known sub-circuits ( or those sub-circuits supported by the particular embodiment) may be trained at block 504 to create a set of trained ML models for a process technology."); ((Fischer, ¶81) "The ML model 812 may use a variety of ML modeling techniques, including linear regression models, large margin classifiers (e.g., support vector machines), principal component analysis, tree-based techniques (e.g., random forest or gradient boosted trees), or neural networks. Linear regression models may be ML models which assumes a linear relationship between input parameters and output. [[…]] Neural network ML modeling techniques may include fully connected (where every neuron of a layer is connected to every other node of the layer), fully connected with regularization (where a regularization function is added to a fully connected neural network to help avoid over fitting), and fully connected with dropout (which removes nodes to simplify the network) and optimizers, such as adaptive moment estimation optimizer enhanced neural networks (which reduces data parameters of the network using gradient descent algorithms)."); ((Fischer, ¶102) "The example neural network ML model 1000 is a simplified example presented to help understand how such neural network ML model 1000 may be trained. It may be understood that each implementation of a ML model may be trained or tuned in a different way, depending on a variety of factors including, but not limited to, a type of ML model being used, parameters being used for the ML model, relationships as among the parameters, desired speed of training, etc. In this simplified example, sub-circuit physical parameters values ofW and Lare parameter inputs 1002 and 1004 to the ML model 1000. Each layer (e.g., first layer 1006, second layer 1008, and third layer 1010) includes a plurality of nodes ( e.g., neurons) and generally represents a set of operations performed on the parameters, such as a set of matrix multiplications. For example, each node represents a mathematical function that takes, as input (aside from the nodes of the first layer 1006), output from a previous layer and a weight. The weight is typically adjusted during ML model training and fixed after the ML model training. The specific mathematical function of the node can vary depending on ML model implementation.")
a simulation processing module, configured to replace, based on a logical relationship among the sub-circuit modules, the target circuit with the fitting functions respectively corresponding to the sub-circuit modules for simulation processing to obtain a simulation result of the target circuit. ((Fischer, ¶70) " FIG. 8 is a system diagram illustrating an overview of technique 800 for designing a new analog circuit from an original analog circuit, in accordance with aspects of the present disclosure. In certain cases, technique 800 may be implemented in software as one or more software programs which may include various modules."); A new circuit may be converted from an original circuit, as a replacement, wherein the subcircuits of the converted circuit are converted by using a corresponding trained ML model for each subcircuit to identify alternative topologies. ((Fischer, ¶61) "At block 522, a representation of the sub-circuit, such as a netlist, is created for each identified sub-circuit based on the predicted certain sub-circuit physical parameters for components of each sub-circuit and the sub-circuits may be connected into circuit blocks, which in tum are connected to form an overall circuit, thus converting the original circuit to a new circuit in the second process technology. At block 524, this new circuit may be simulated to verify that the new circuit meets the design specification, and if the design specifications are met, the representation of the new circuit may be output at block 526."); The conversion (replacement) process is subject to a formatting tool that accounts for connections between subcircuit components, as logical relationships ((Fischer, ¶96) "Formatting tool 830 may correct formatting, connection drawing, and/or mapping issues that may arise during the conversion. In certain cases, the formatting tool 830 may extract certain formatting, connection, and or mapping information from the original circuit design 802 for use to correct the converted data object (e.g., netlist). In certain cases, this netlist may be connected to or appended on another netlist, such as a netlist for a converted version of the circuit block and other circuit blocks, if needed, to output a data object representing a new circuit 832 for the second process technology". The converted circuit is subject to simulation ((Fischer, ¶45) "After the electronic components are converted to the target process technology, the completed circuit may be simulated on circuit simulation software, such as simulation program with integrated circuit emphasis (SPICE), as against the design specifications.")
Regarding claim 9, Fischer discloses An electronic device, wherein the electronic device comprises a processor and a memory, the memory stores at least one instruction, and the at least one instruction is configured to be loaded and executed by the processor to implement the circuit simulation method according to claim 1 ((Fischer, ¶132-134) "As illustrated in FIG. 18, device 1800 includes a processing element such as processor 1805 that contains one or more hardware processors, where each hardware processor may have a single or multiple processor cores. Examples of processors include, but are not limited to, a central processing unit (CPU) or a microprocessor. Although not illustrated in FIG. 18, the processing elements that make up processor 1805 may also include one or more other types of hardware processing components, such as graphics processing units (GPUs), application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and/or digital signal processors (DSPs). In certain cases, processor 1805 may be configured to perform functions described in conjunction with FIGS. 5, 6, 8, 11, and 12-17. It may also be understood that while described in conjunction with a single device, the functions described may be performed by any number of processing elements and that these processing elements may associated with multiple devices that are communicatively coupled. For example, generation of ML models, ML libraries, netlists, etc. may be performed on a separate device as compared to the conversion or optimization of a circuit. In certain cases, these various devices may be networked by any known networking technology, examples of which include ethemet, wireless fidelity (WiFi), internet, etc. In certain cases, data objects may be provided and/or received via non-transitory computer readable storage medium."); ((Fischer, ¶133-134) "FIG. 18 illustrates that memory 1810 may be operatively and communicatively coupled to processor 1805. Memory 1810 may be a non-transitory computer readable storage medium configured to store various types of data. For example, memory 1810 may include one or more volatile devices such as random access memory (RAM). In certain cases, the SRAM and circuits as described in FIGS. 4-8 may be incorporated as part of the memory 1810. Non-volatile storage devices 1820 can include one or more disk drives, optical drives, solid-state drives (SSDs ), tap drives, flash memory, electrically programmable read only memory (EEPROM), and/or any other type memory designed to maintain data for a duration time after a power loss or shut down operation. The non-volatile storage devices 1820 may also be used to store programs that are loaded into the RAM when such programs executed. Persons of ordinary skill in the art are aware that software programs may be developed, encoded, and compiled in a variety of computing languages for a variety of software platforms and/or operating systems and subsequently loaded and executed by processor 1805. In one embodiment, the compiling process of the software program may transform program code written in a programming language to another computer language such that the processor 1805 is able to execute the programming code. For example, the compiling process of the software program may generate an executable program that provides encoded instructions (e.g., machine code instructions) for processor 1805 to accomplish specific, non-generic, particular computing functions."). See also rejection of claim 1 for limitations described therein by Fischer.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fischer et al (US 2021/0390243 A1), as given above and further in view of McGaughy et al (US 2015/0363527 A1), hereinafter referred to as McGaughy.
Regarding claim 4, Fischer discloses (except the limitations surrounded by brackets ([[..]])) The method according to claim 1, wherein the step of performing function fitting processing on the sub-circuit modules to obtain fitting functions corresponding to the subcircuit modules comprises: as stated previously and further discloses
obtaining sub-circuit parameters of each of the sub-circuit modules, [[and constructing, based on the sub-circuit parameters, a sub-circuit matrix corresponding to each of the sub-circuit modules;]] ((Fischer, ¶127) "At block 1702, an initial set of parameters are received, the initial set of parameters associated with a sub-circuit. For example, a set of subcircuit performance parameters or sub-circuit physical parameters for a ML model of a sub-circuit may be received. At block 1704, a first parameter of the initial set of parameters is interacted with other parameters of the initial set of parameters to generate a set of interacted parameters. For example, the first parameter may be interacted with another parameter of the set of parameters to generate an interacted parameter. At block 1706, the interacted parameter is added to the initial set parameters to generate a candidate set of parameters. For example, the interacted parameter may be added to the set of parameters."); ((Fischer, ¶102) "In certain embodiments, modeling analog circuits with ML models can be performed by using sub-circuit parameters as input parameters (e.g., features) of a ML model.")
processing sample input data based on the sub-circuit [[matrix]] to obtain predicted output data corresponding to the sample input data; and ((Fischer, ¶127) "At block 1708, a linear regression may be performed on parameters of the candidate set of parameters against a set of expected parameter values to determine a predictive value for parameters of the candidate set of parameters."); ((Fischer, ¶129) "At block 1724, the linear regression may be performed on parameters of the candidate set of parameters against a set of expected parameter values to determine a predictive value for parameters of the candidate set of parameters.")
performing fitting by using a linear regression method based on the sample input data and the predicted output data corresponding to the sample input data to obtain the fitting function corresponding to each of the sub-circuit modules. ((Fischer, ¶127) "At block 1708, a linear regression may be performed on parameters of the candidate set of parameters against a set of expected parameter values to determine a predictive value for parameters of the candidate set of parameters. For example, the linear regression attempts to model a relationship between the parameters as compared to expected results of the ML model and a statistical significance test may be applied to the results of the linear regression to determine a statistical significance value of parameters of the set of parameters. In certain cases, this linear regression equation may be based on a Taylor series regression."); ((Fischer, ¶131) "In certain cases where the accuracy has not reached the predetermined accuracy level, a second ML model may be trained based on the set of selected variables and parameter values of the second set of parameter values. For example, where the sufficient level of accuracy has not been met and the repeating ended after each variable in the original set of variables has been interacted a predetermined number of times, a final set of candidate variables may be used to train another ML model."). See further sections of Fischer ¶127-131 discussing leveraging using the linear regression analysis as part of training the ML model that is used to convert the subcircuits, wherein the ML model is understood as the fitted function corresponding to each subcircuit. The ML models correspond to each subcircuit ((Fischer, ¶58) "A ML model for each sub-circuit of the known sub-circuits ( or those sub-circuits supported by the particular embodiment) may be trained at block 504 to create a set of trained ML models for a process technology.")
While Fischer does not explicitly disclose the construction of a sub-circuit matrix corresponding to the parameters corresponding to the subcircuit modules, McGaughy is relied upon to disclose and constructing, based on the sub-circuit parameters, a sub-circuit matrix corresponding to each of the sub-circuit modules; Nodal analysis is performed in SPICE to convert nodal equations in matrix form, to include the utilization of model parameters ((McGaughy, ¶10-11) "SPICE models a circuit in a node/element fashion, i.e., the circuit is regarded as a collection of various circuit elements connected at nodes. At the heart of SPICE is the so-called Nodal Analysis, which is accomplished by formulating nodal equations ( or circuit equations) in matrix format to represent the circuit and by solving these nodal equations. The circuit elements are modeled by device models, which produce model results that are represented in the circuit equations as matrices. A device model for modeling a circuit element, such as the SPICE model for modeling MOSFET devices, developed by UC Berkeley, typically includes model equations and a set of model parameters that mathematically represent characteristics of the circuit element under various bias conditions."). SPICE simulations are described as being applied to sub-circuits ((McGaughy, ¶6) "SPICE-like simulations may provide fairly accurate predictions of how corresponding circuits will behave when actually built. The predictions are preferably made not only for individual sub-circuit but also for whole systems ( e.g., whole integrated circuits) so that system-wide problems relating to noise and the like may be uncovered and dealt with. ")
McGaughy covers further the subcircuit matrix as the data representation in SPICE to characterize the subcircuit, as given above.
Fischer is analogous to the claimed invention because it is related to the same field of endeavor of circuit design and simulation software. McGaughy is likewise analogous to the claimed invention for being in the same field of endeavor. It would have been obvious to one of ordinary skill to which said subject matter pertains at the time the invention was filed to have modified the teachings of Fischer with the teachings of McGaughy because some teaching, suggestion, or motivation in the prior art would have led one having skill in the art to do so in order to arrive at the claimed invention. Fischer discloses the utilization of SPICE simulation software as part of a design approach, wherein Fischer particularly states that a subcircuit comprises parameters and can be simulated using SPICE software ((Fischer, ¶62) " At block 502, models of these models may be simulated using circuit simulation software, such as SPICE. Each set of sub-circuit physical parameters may be simulated to identify certain sub-circuit performance parameters associated with a given set of sub-circuit physical parameters for the first process technology. "). Fischer fails to discloses the innerworkings of how the subcircuit is processed within the SPICE simulations; however McGaughy explicitly describes how SPICE simulations fundamentally treat circuits under consideration. That is, McGaughy discloses that SPICE leverages Nodal Analysis as a fundamental process which is accomplished by formulating nodal equations in the form of matrices. ((McGaughy, ¶10) "SPICE models a circuit in a node/element fashion, i.e., the circuit is regarded as a collection of various circuit elements connected at nodes. At the heart of SPICE is the so-called Nodal Analysis, which is accomplished by formulating nodal equations ( or circuit equations) in matrix format to represent the circuit and by solving these nodal equations. The circuit elements are modeled by device models, which produce model results that are represented in the circuit equations as matrices."). Accordingly, because Fischer suggests the utilization of SPICE simulation but does not describe the fundamental process that characterize it and because McGaughy explicitly demonstrates the nodal analysis process to generate matrices representative of circuits under evaluation, the combination would have accordingly been obvious.
Regarding claim 5, the proposed combination discloses The method according to claim 4, as stated above and further discloses in view of Fischer wherein, before the step of processing sample input data based on the sub-circuit [[matrix]] to obtain predicted output data corresponding to the sample input data, the method further comprises: Prior to performing the processing as given above, a circuit topology is simulated, wherein the simulation is based on the identification of a range of physical parameters ((Fischer, ¶83) "In certain cases, the set of sub-circuit physical parameters, sub-circuit operational parameters, and generated sub-circuit performance parameters resulting from the simulations may be used to train a ML model 504 corresponding to the simulated sub-circuit topology."); ((Fischer, ¶58) "Each component of a sub-circuit may be associated with certain range of physical parameters. Sets of sub-circuit physical parameters may be identified, each set having a different combination of physical parameters for the electrical com ponents. These known sub-circuits may be modeled, for example as a netlist for use with a circuit simulator, for each set of sub-circuit physical parameters. This modeling may be based on a netlist, which generally is a list of the electrical components of a circuit and a list of nodes each electronic component is connected with. At block 502, models of these known sub-circuits may be simulated using circuit simulation software, such as SPICE. Each set of sub-circuit physical parameters may be simulated to identify certain sub circuit performance parameters associated with a given set of sub-circuit physical parameters for the first process technology."). See Fischer Figs. 17A and 17B depicting the sequence of events demonstrating that simulation is performed prior to linear regression as the processing, as given particularly by block 1716 wherein the accuracy is compared to the simulation results prior to block 1724 regression step.
obtaining an input data range corresponding to the sub-circuit [[matrix;]] and ((Fischer, ¶82) "A particular type of sub-circuit implemented in a given process technology may be associated with a practical range of sub-circuit physical parameters (e.g., physical parameters) and operational parameters for the first process technology. The practical range of sub-circuit physical parameters may be provided, for example, by a user and the practical range may be based on limitations of a process technology. ")
performing sampling within the input data range corresponding to the sub-circuit [[matrix]] to obtain the sample input data. ((Fischer, ¶82) "Moreover, in certain cases, the combinations of sub-circuit physical parameters, sub-circuit performance parameters, and sub-circuit operational parameters are not exhaustive, but rather combinations of the sub-circuit physical parameters, sub-circuit performance parameters, and sub-circuit operational parameters are selected and simulated to cover the Gaussian and Uniform distribution encompassing the cases typically identified in analog semiconductor technology manufacturing variations. For example, operating points may be selected substantially uniformly across the practical range of sub-circuit physical parameters with additional operating points selected in ranges of sub-circuit physical parameters most commonly used ( or expected to be used) for a given sub-circuit or circuit."). The parameters correspond to the input data for the processing, as stated above ((Fischer, ¶127) "At block 1708, a linear regression may be performed on parameters of the candidate set of parameters against a set of expected parameter values to determine a predictive value for parameters of the candidate set of parameters.").
Fischer does not disclose the utilization of a matrix representation for the subcircuit; however, as stated above in the rejection of claim 4 from which this claim depends, McGaughy explicitly describes the sub-circuit representation as being in matrix form. By considering the generated matrix of McGaughy as the representation by which to perform data analysis and sampling per Fischer, one would arrive at the claimed invention. The motivation to further describe the invention in this way is given by the rationale in claim 5.
Regarding claim 6, the proposed combination discloses The method according to claim 5, as stated previously and further discloses in view of Fischer (except the limitations surrounded by brackets ([[..]])) wherein the step of performing sampling within the input data range corresponding to the subcircuit [[matrix]] to obtain the sample input data comprises: Selection is performed over a range of parameters wherein the parameters are used to create an ML model ((Fischer, ¶82-83) " Moreover, in certain cases, the combinations of sub-circuit physical parameters, sub-circuit performance parameters, and sub-circuit operational parameters are not exhaustive, but rather combinations of the sub-circuit physical parameters, sub-circuit performance parameters, and sub-circuit operational parameters are selected and simulated to cover the Gaussian and Uniform distribution encompassing the cases typically identified in analog semiconductor technology manufacturing variations. For example, operating points may be selected substantially uniformly across the practical range of sub-circuit physical parameters with additional operating points selected in ranges of sub-circuit physical parameters most commonly used ( or expected to be used) for a given sub-circuit or circuit. certain cases, the set of sub-circuit physical parameters, sub-circuit operational parameters, and generated sub-circuit performance parameters resulting from the simulations may be used to train a ML model 504 corresponding to the simulated sub-circuit topology").
obtaining a [[matrix]] order corresponding to the sub-circuit [[matrix]]; and When read in light of the specification in ¶108, the matrix order is representative of the complexity of the sub-circuit matrix. The circuit theory equations are described as being correlated to an equation order and are used to characterize the circuit ((Fischer, ¶108) " In certain embodiments, attempting to characterize the non-linearities based on circuit theory, such as by including known circuit theory equations ( e.g., the first order equation for transconductance), can introduce higher-order interaction terms and may increase the dimensionality (e.g., number of parameters input into the ML model).").
equally dividing the input data range based on the [[matrix]] order of the sub-circuit matrix, and Threshold step wise selection is performed based on the equations having an order ((Fischer, ¶107) " As an example, an input parameter to a ML model may be based on the equation for determining transconductance of a CMOS transistor. In this example, a ML model, MLgm, may have input parameters such that MLgm=f(W,L,T,NCH,T0 x , In, Ins), where the input parameters respectively represent the electrical component width, electrical component length, temperature, N-channel doping concentration, oxide thickness, electrical component drain current bias, and the voltage across the drain-source terminals of the electrical component. One known nonlinear parameter interaction is the first order equation for transconductance, gm =y'2μncoJW/L)"). The threshold stepwise selection may be performed so as to provide an optimal set of parameters, wherein the selection accounts for the order of the equations characterizing the circuit behavior ((Fischer, ¶108) " In certain embodiments, attempting to characterize the non-linearities based on circuit theory, such as by including known circuit theory equations ( e.g., the first order equation for transconductance), can introduce higher-order interaction terms and may increase the dimensionality (e.g., number of parameters input into the ML model). To help reduce the number of parameters for input into the ML model, dimensionality reduction may be performed. Dimensionality reduction removes parameters as inputs to the ML model if it is determined that those parameters do not impact the model behavior. Dimensionality reduction may help reduce the number of variables, identify an optimal set of parameters to be input into the ML model, and/or help reduce the processing time of the ML model. In certain cases, dimensionality reduction may be performed using threshold stepwise selection."). The combinations of the subcircuit parameters (such as the optimal set provided by the threshold stepwise selection above, which accounts for the order) are selected to cover a uniform distribution over the practical range, whereby a uniform distribution is understood to impart an equal probability on each data point of being selected (as the equal division of the likelihood of sampling the input data) ((Fischer, ¶82) " Moreover, in certain cases, the combinations of sub-circuit physical parameters, sub-circuit performance parameters, and sub-circuit operational parameters are not exhaustive, but rather combinations of the sub-circuit physical parameters, sub-circuit performance parameters, and sub-circuit operational parameters are selected and simulated to cover the Gaussian and Uniform distribution encompassing the cases typically identified in analog semiconductor technology manufacturing variations. For example, operating points may be selected substantially uniformly across the practical range of sub-circuit physical parameters with additional operating points selected in ranges of sub-circuit physical parameters most commonly used ( or expected to be used) for a given sub-circuit or circuit.")
determining data values obtained by the equal dividing as the sample input data. Operating points (as data values) are selected according to the distribution ((Fischer, ¶82) " For example, operating points may be selected substantially uniformly across the practical range of sub-circuit physical parameters with additional operating points selected in ranges of sub-circuit physical parameters most commonly used ( or expected to be used) for a given sub-circuit or circuit. ")
Fischer does not disclose the representation of the circuit as a matrix, as described previously; however McGaughy is relied upon to disclose the matrix representation of the circuit behavior with a corresponding matrix dimension/order. ((McGaughy, ¶8) " A circuit may be represented as a large numerically discrete nonlinear matrix for analyzing instant current. The matrix dimension is of the same order as the number of the nodes in the circuit.").
By treating the described behavior of the circuit technology as parameters and equations, as given in Fischer (See at least ¶106-108) instead as in the explicit form of a matrix to describe such characterization as given by McGaughy, one would arrive at the claimed invention. Doing so would have been driven by the motivation set forth in the rejection of claim 4 from which this claim depends.
Conclusion
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/E.G.L./Examiner, Art Unit 2187
/EMERSON C PUENTE/Supervisory Patent Examiner, Art Unit 2187
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