DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/21/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5, 11, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Iwaya (US Pub. No. 2009/0280646) in view of Kerber (US Pub. No. 2011/0176339).
Regarding claim 1, in FIGs. 6 and 9, Iwaya discloses a semiconductor device comprising: a semiconductor chip (1, paragraph [0038]) that has a principal surface (top); an insulating portion (10, paragraph [0037]) formed on the principal surface of the semiconductor chip; a first conductive layer (7, paragraph [0037]) that is formed in the insulating portion and connected to a first potential (capable of being connected to a primary potential); a second conductive layer (14, paragraph [0037]) that opposes the first conductive layer of the principal surface in a normal direction and is connected to a second potential (capable of being connected to a secondary potential) different from the first potential; an insulating layer (12, paragraph [0037]) that is formed between the first conductive layer and the second conductive layer, and a first pad (9, paragraph [0038]) that is electrically connected to the first conductive layer; a second pad (16, paragraph [0044]) that is aligned with respect to the second conductive layer in a plan view when the semiconductor chip is viewed from the normal direction and is electrically connected to the second conductive layer, wherein the second conductive layer and the second pad are placed on the insulating layer, the semiconductor chip has, in the plan view, one side and another side that intersect each other (adjacent edges), and the first pad is formed in the insulating portion such that the first pad is exposed from the insulating layer.
Iwaya appears not to explicitly disclose that the first pad is formed in the insulating portion such that the first pad is exposed from the insulating layer, in a region separated from the second pad in a third direction extending in the plan view so as to intersect both a first direction parallel to the one side of the semiconductor chip and a second direction parallel to the other side of the semiconductor chip in the plan view.
The art however well recognized (see, for example, Kerber FIGs. 4-5) a first pad (16) formed in an insulating portion (14) such that the first pad is exposed from an insulating layer, in a region separated from a second pad (28) in a third direction (direction oblique to the sides of the extension direction of the sides of the chip) extending in a plan view so as to intersect both a first direction parallel to the one side of a semiconductor chip and a second direction parallel to the other side of the semiconductor chip in the plan view to be suitable as a pad layout for a semiconductor device with integrated transformer.
According to well-established patent law precedents (see, for example, M.P.E.P. § 2144.07), therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have formed the first pad in the insulating portion such that the first pad is exposed from the insulating layer, in a region separated from the second pad in a third direction extending in the plan view so as to intersect both a first direction parallel to the one side of the semiconductor chip and a second direction parallel to the other side of the semiconductor chip in the plan view for its recognized suitability as a pad layout for a semiconductor device with integrated transformer.
Regarding claim 2, in FIGs. 6 and 9, Iwaya discloses that the insulating layer (12) is placed on the insulating portion (10), and a distance between the second conductive layer and the first pad in a normal direction is greater than a thickness of the insulating layer in the normal direction.
Regarding claim 5, in FIGs. 6 and 9, Iwaya discloses that the first conductive layer includes a first coil, and the second conductive layer includes a second coil.
Regarding claim 11, in FIGs. 6 and 9, Iwaya discloses a first conductive member (2, paragraph [0038]) that is connected to an inner end portion of the first coil, extends by crossing the first coil below the first coil and is electrically connected to the first pad.
Regarding claim 19, in FIGs. 6 and 9, Iwaya discloses the one side and the other side of the semiconductor chip are orthogonal to each other (adjacent edges), and the first direction intersects each of the second direction and the third direction, the second direction and the third direction being orthogonal to each other.
Claims 3, 6-7, and 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over Iwaya (US Pub. No. 2009/0280646) and Kerber (US Pub. No. 2011/0176339) as applied to claims 1, 2, 5, 11, and 19 above, and further in view of Tanaka (US Pub. No. 2018/0130587).
Regarding claim 3, in FIGs. 6 and 9, Iwaya discloses that the semiconductor chip is formed in a quadrilateral shape that has a first corner portion and a second corner portion which are diagonal to each other as well as a third corner portion and a fourth corner portion which are diagonal to each other in a plan view.
The combination of Iwaya and Kerber appears not to explicitly disclose that the second conductive layer is provided such that the second conductive layer is close to the first corner portion, and the first pad is provided such that the first pad is close to the second corner portion.
The art however well recognized a second conductive layer provided such that a second conductive layer is close to a first corner portion, and a first pad is provided such that the first pad is close to a second corner portion to be suitable as a layout for a semiconductor device with integrated transformer. See, for example, Tanaka FIGs. 1-10, which disclose a semiconductor chip formed in a quadrilateral shape (rectangle) that has a first corner portion (e.g. top right corner in FIG. 6) and a second corner portion (e.g. bottom left corner in FIG. 6) which are diagonal to each other as well as a third corner portion and a fourth corner portion (remaining corners in FIG. 6) which are diagonal to each other in a plan view, a second conductive layer (25) is provided such that the second conductive layer is close to the first corner portion, and a first pad (14) is provided such that the first pad is close to the second corner portion.
According to well-established patent law precedents (see, for example, M.P.E.P. § 2144.07), therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have formed the second conductive layer such that the second conductive layer is close to the first corner portion, and the first pad is provided such that the first pad is close to the second corner portion for its recognized suitability as a layout for a semiconductor device with integrated transformer.
Regarding claim 6, the combination of Iwaya and Kerber appears not to explicitly disclose that the second coil is larger in thickness than the first coil.
The art however well recognized a second coil larger in thickness than a first coil to be suitable as a coil layout for a semiconductor device with integrated transformer. See, for example, Tanaka FIG. 7, which discloses a second coil (at least 65 portion, paragraph [0124]) is larger in thickness than a first coil (as measured in a horizontal direction in FIG. 7).
According to well-established patent law precedents (see, for example, M.P.E.P. § 2144.07), therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have formed the second coil larger in thickness than the first coil for its recognized suitability as a coil layout for a semiconductor device with integrated transformer.
Regarding claim 7, the combination of Iwaya and Kerber appears not to explicitly disclose that the second coil has a thickness larger than a pitch of the first coil.
The art however well recognized a second coil having a thickness larger than a pitch of the first coil to be suitable as a coil layout for a semiconductor device with integrated transformer. See, for example, Tanaka FIGs. 1-10, which discloses a second coil having a thickness (at least 65 portion, paragraph [0124]) larger than a pitch of a first coil (space between portions of 26 as measured in a horizontal direction in FIG. 7).
According to well-established patent law precedents (see, for example, M.P.E.P. § 2144.07), therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have formed the second coil to have a thickness larger than a pitch of the first coil for its recognized suitability as a coil layout for a semiconductor device with integrated transformer.
Regarding claims 14-15, the combination of Iwaya and Kerber appears not to explicitly disclose that the insulating layer includes a laminated structure of a first inorganic insulating layer and a second inorganic insulating layer that is laminated on the first inorganic insulating layer.
The art however well recognized an insulating layer including a laminated structure of a first inorganic insulating layer and a second inorganic insulating layer that is laminated on the first inorganic insulating layer to be suitable as an insulating layer for a semiconductor device with integrated transformer. See, for example, Tanaka FIGs. 1-10, which discloses an insulating layer including a laminated structure of a first inorganic insulating layer (45, e.g. SiN, paragraph [0083]) and a second inorganic insulating layer (46, e.g. SiO2) that is laminated on the first inorganic insulating layer (paragraph [0081], paragraph [0083]).
According to well-established patent law precedents (see, for example, M.P.E.P. § 2144.07), therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have formed the insulating layer to include a laminated structure of a first inorganic insulating layer and a second inorganic insulating layer that is laminated on the first inorganic insulating layer, as disclosed by Iwaya, for its recognized suitability as an insulating layer for a semiconductor device with integrated transformer.
Regarding claims 16-18, the combination of Iwaya and Kerber appears not to explicitly disclose a semiconductor module comprising: a die pad; the semiconductor device according to Claim 5 that is installed on the die pad; a package main body that seals the die pad and the semiconductor device; and a lead terminal that is electrically connected to the semiconductor device and exposed from the package main body; wherein the semiconductor device includes a signal-transmitting insulating element for transmitting a signal in an insulation state between the first coil and the second coil, and the semiconductor module further including a second semiconductor device that is electrically connected to the insulating element; the second semiconductor device includes a control element that is electrically connected to one of the first coil and the second coil, and a driving element that is electrically connected to the other of the first coil and the second coil.
The art however well recognized such a configuration to be suitable for use as a semiconductor device with integrated transformer configuration. See, for example, Tanaka FIGs. 1-10, which discloses a semiconductor module comprising: a die pad (8, paragraph [0053]); the semiconductor device according to claim 5 (5) that is installed on the die pad; a package main body (2, paragraph [0049]) that seals the die pad and the semiconductor device; and a lead terminal (3) that is electrically connected to the semiconductor device and exposed from the package main body; wherein the semiconductor device includes a signal-transmitting (5) insulating element for transmitting a signal in an insulation state (interpreted as not being directly connected) between the first coil and the second coil, and the semiconductor module further including a second semiconductor device (4/6) that is electrically connected to the insulating element; the second semiconductor device includes a control element (4) that is electrically connected to one of the first coil and the second coil, and a driving element (6) that is electrically connected to the other of the first coil and the second coil.
According to well-established patent law precedents (see, for example, M.P.E.P. § 2144.07), therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have formed the structure disclosed by Iwaya to include the features of claims 16-18, as disclosed by Tanaka, for its recognized suitability as a semiconductor device with integrated transformer configuration.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Iwaya (US Pub. No. 2009/0280646) and Kerber (US Pub. No. 2011/0176339) as applied to claims 1 and 5 above, and further in view of Chu (US Pub. No. 2017/0221819).
Regarding claim 8, the combination of Iwaya and Kerber appears not to explicitly disclose that the second coil includes a first portion that forms an outermost periphery of the second coil and has a first width and a second portion that forms a coil portion further inside than the first portion and has a second width smaller than the first width.
However, Chu discloses that the efficiency of a coil may be enhanced by making the outer rings of a coil wider than that of the inner rings (paragraph [0041]).
To improve the efficiency of the second coil it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to form the second coil such that it includes a first portion that forms an outermost periphery of the second coil and has a first width and a second portion that forms a coil portion further inside than the first portion and has a second width smaller than the first width.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Iwaya (US Pub. No. 2009/0280646) and Kerber (US Pub. No. 2011/0176339) as applied to claims 1 and 5 above, and further in view of Fouquet (US Pub. No. 2008/0180206).
Regarding claim 10, the combination of Iwaya and Kerber appears not to explicitly disclose that the first coil is AlCu, and the second coil is Cu.
The art however well recognized combinations of Al and AlCu to be suitable for use as first and second coil materials. See, for example, Fouquet, paragraph [0055].
According to well-established patent law precedents (see, for example, M.P.E.P. § 2144.07), therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have formed the Iwaya disclosed first coil from AlCu and the second coil from Cu for its recognized suitability as a first and second coil materials.
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Iwaya (US Pub. No. 2009/0280646) and Kerber (US Pub. No. 2011/0176339) as applied to claim 1 above, and further in view of Funya (US Pub. No. 2015/0206934).
Regarding claims 12-13, the combination of Iwaya and Kerber appears not to explicitly disclose that the insulating layer includes an organic insulating layer, wherein the organic insulating layer includes at least one among a polyimide film, a phenol resin film, and an epoxy resin film.
However, Funaya discloses a similar device having a polyimide film disposed between the two coils at least because of its increased heat resistance (paragraph [0161]).
To increase the heat resistance of the insulating layer it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to include a polyimide film.
Allowable Subject Matter
Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUCKER J WRIGHT whose telephone number is (571)270-3234. The examiner can normally be reached 8:30am-5:00pm.
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/TUCKER J WRIGHT/Primary Examiner, Art Unit 2891
