Prosecution Insights
Last updated: October 04, 2026
Application No. 18/029,855

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR, AND LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREFOR

Final Rejection §103
Filed
Mar 31, 2023
Priority
Nov 18, 2020 — nonprovisional of PCTCN2020129794
Examiner
HSIEH, HSIN YI
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Enkris Semiconductor Inc.
OA Round
2 (Final)
51%
Grant Probability
Moderate
3-4
OA Rounds
4m
Est. Remaining
57%
With Interview

Examiner Intelligence

Grants 51% of resolved cases
51%
Career Allowance Rate
326 granted / 641 resolved
-17.1% vs TC avg
Moderate +6% lift
Without
With
+5.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 11m
Avg Prosecution
31 currently pending
Career history
698
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
37.2%
-2.8% vs TC avg
§102
20.2%
-19.8% vs TC avg
§112
40.6%
+0.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 641 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-6, 8 and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okurama et al. (US 2005/0145865 A1) in view of Zhang et al. (CN 110098295 A, please see the machine translation attached in the office action mailed on 02/23/2026). Regarding claim 1, Okurama et al. teach in Fig. 12, a semiconductor structure (semiconductor light emitting element; Fig. 12, [0001]), comprising: a substrate (11; [0127]), a first semiconductor layer (12/15; [0127, 0129]), an isolation layer (14; [0128]), an active layer (16; [0130]), a second semiconductor layer (17; [0130]), a first electrode (18; [0135]) and a second electrode (19; [0136]), wherein the first semiconductor layer (12/15) has a conductivity type (n-type; [0127, 0129]) opposite to a conductivity type (p-type; [0130]) of the second semiconductor layer (17); the first semiconductor layer (12/15) comprises a flat portion (12; [0127]), first protrusions (a lower portion of 15 in the through hole of 14) and second protrusions (an upper portion of 15 above the through hole of 14) which are stacked sequentially in a vertical direction (vertical direction of Fig. 12), the flat portion (12) is formed on the substrate (11), the isolation layer (14) is formed on the flat portion (12) and comprises first through-holes (the middle through hole of 14) in the vertical direction (vertical direction of Fig. 12), the first protrusions (a lower portion of 15 in the through hole of 14) are formed in the first through-holes (the middle through hole of 14) respectively, the second protrusions (an upper portion of 15 above the through hole of 14) are formed on the first protrusions (a lower portion of 15 in the through hole of 14) respectively, the second protrusions (an upper portion of 15 above the through hole of 14) correspond to the first through-holes (the middle through hole of 14) respectively, the second protrusions (an upper portion of 15 above the through hole of 14) are spaced apart from each other (see Fig. 10), and a side surface of each of the second protrusions (an upper portion of 15 above the through hole of 14) is a bevel (see Fig. 12); the active layer (16), the second semiconductor layer (17), and the first electrode (18) are sequentially stacked on the second protrusions (an upper portion of 15 above the through hole of 14) of the first semiconductor layer (12/15); and the isolation layer (14) is further provided with a second through-hole (the right through hole of 14 in Fig. 12) in the vertical direction (vertical direction of Fig. 12), and the second electrode (19; [0136]) is formed in the second through-hole (the right through hole of 140 in Fig. 12) and is connected to the first semiconductor layer (12/15; see Fig. 12). Okurama et al. do not teach the second semiconductor layer is a conductive Distributed Bragg Reflector (DBR) structure; wherein the conductive DBR structure is a porous conductive DBR structure, the porous conductive DBR structure comprises one or more first porous conductive layers and one or more second porous conductive layers, each of the one or more first porous conductive layers has first holes, each of the one or more second porous conductive layers has second holes, and one of the first holes has a first diameter different from a second diameter of one of the second holes. In the same field of endeavor of light emitting devices, Zhang et al. teach the second semiconductor layer (porous conductive DBR layer; 14 in Fig. 1, [0011, 0050]) is a conductive Distributed Bragg Reflector (DBR) structure ([0011]); wherein the conductive DBR structure (14) is a porous conductive DBR structure ([0011, 0050]), the porous conductive DBR structure (14) comprises one or more first porous conductive layers (high-porosity porous GaN layers; [0011]) and one or more second porous conductive layers (low-porosity porous GaN layers; [0011]), each of the one or more first porous conductive layers (high-porosity porous GaN layers) has first holes (holes of the high-porosity porous GaN layers), each of the one or more second porous conductive layers (low-porosity porous GaN layers) has second holes (holes of the low-porosity porous GaN layers), and one of the first holes (holes of the high-porosity porous GaN layers) has a first diameter (pore size, which can be 300 nm; [0015]) different from a second diameter (pore size, which can be 1 nm; [0015]) of one of the second holes (holes of the low-porosity porous GaN layers). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Okurama et al. and Zhang et al., and to form a conductive DBR structure of Zhang et al. on the outer surface of the layer 17 of Okurama et al. under the layer 18 of Okurama et al., and also switching the polarity of layers of Okurama et al. to avoid forming the p-n junction on the layer 17 of Okurama et al., because Okurama et al. teach that the light emitted from the active layer has to be reflected at the outer surface of the layer 17 to have efficient extract of the light ([0145]), while Zhang et al. teach that the conductive DBR structure of Zhang et al. can provide high-reflectivity ([0035]), and the combination of Okurama et al. and Zhang et al. would put the conductive DBR structure in contact with the outer surface of the layer 17 of Okurama et al. to efficiently reflect the light arriving at the outer surface of the layer 17, and further provide the advantages of good conductivity, wide cutoff bandwidth, and easy adjustment of center wavelength ([0035] of Zhang et al.). Regarding claim 2, Okurama et al. teach the semiconductor structure according to claim 1. Okurama et al. do not teach wherein, the porous conductive DBR structure comprises the one or more first porous conductive layers and the one or more second porous conductive layers which are alternately stacked and formed after electrochemical corrosion. In the same field of endeavor of light emitting devices, Zhang et al. teach wherein, the porous conductive DBR structure (14) comprises the one or more first porous conductive layers (high-porosity porous GaN layers) and the one or more second porous conductive layers (low-porosity porous GaN layers) which are alternately stacked and formed after electrochemical corrosion ([0011]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Okurama et al. and Zhang et al., and to form a conductive DBR structure of Zhang et al. on the outer surface of the layer 17 of Okurama et al. under the layer 18 of Okurama et al., and also switching the polarity of layers of Okurama et al. to avoid forming the p-n junction on the layer 17 of Okurama et al., because Okurama et al. teach that the light emitted from the active layer has to be reflected at the outer surface of the layer 17 to have efficient extract of the light ([0145]), while Zhang et al. teach that the conductive DBR structure of Zhang et al. can provide high-reflectivity ([0035]), and the combination of Okurama et al. and Zhang et al. would put the conductive DBR structure in contact with the outer surface of the layer 17 of Okurama et al. to efficiently reflect the light arriving at the outer surface of the layer 17, and further provide the advantages of good conductivity, wide cutoff bandwidth, and easy adjustment of center wavelength ([0035] of Zhang et al.). Regarding claim 3, Okurama et al. teach the semiconductor structure according to claim 2. Okurama et al. do not teach wherein materials of the one or more first porous conductive layers and the one or more second porous conductive layers are gallium nitride-based materials. In the same field of endeavor of light emitting devices, Zhang et al. teach wherein materials of the one or more first porous conductive layers (high-porosity porous GaN layers) and the one or more second porous conductive layers (low-porosity porous GaN layers) are gallium nitride-based materials (GaN; [0011]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Okurama et al. and Zhang et al., and to form a conductive DBR structure of Zhang et al. on the outer surface of the layer 17 of Okurama et al. under the layer 18 of Okurama et al., and also switching the polarity of layers of Okurama et al. to avoid forming the p-n junction on the layer 17 of Okurama et al., because Okurama et al. teach that the light emitted from the active layer has to be reflected at the outer surface of the layer 17 to have efficient extract of the light ([0145]), while Zhang et al. teach that the conductive DBR structure of Zhang et al. can provide high-reflectivity ([0035]), and the combination of Okurama et al. and Zhang et al. would put the conductive DBR structure in contact with the outer surface of the layer 17 of Okurama et al. to efficiently reflect the light arriving at the outer surface of the layer 17, and further provide the advantages of good conductivity, wide cutoff bandwidth, and easy adjustment of center wavelength ([0035] of Zhang et al.). Regarding claim 4, Okurama et al. teach the semiconductor structure according to claim 1, wherein an angle between the side surface (the left side surface) of each of the second protrusions (an upper portion of 15 above the through hole of 14; see Fig. 3B) and a horizontal plane (the horizontal plane in Fig. 3B) is a first angle (the angle between F1-F4 and the top surface of 14; Fig. 3B), and the first angle (the angle between F1-F4 and the top surface of 14) has a degree range (the degree range of F4 to the top surface of 14) of 20 degrees to 70 degrees (62° to 63°; [0129]). Regarding claim 5, Okurama et al. teach the semiconductor structure according to claim 4, wherein a sidewall (the left sidewall) of each of the first through-holes (the middle through hole of 14) is a bevel (see Fig. 12 tilted clockwise 30 degrees), and, for each of the first through-holes (the middle through hole of 14), the sidewall of the first through-hole (the left sidewall of the middle through hole of 14) and the side surface of a corresponding one of the second protrusions (the left side surface of an upper portion of 15 above the through hole of 14) on a same side (the top side of 12) are inclined in a same direction (inclined in a right horizontal direction seeing Fig. 12 tilted clockwise 30 degrees). Regarding claim 6, Okurama et al. teach the semiconductor structure according to claim 1, wherein each of the second protrusions (an upper portion of 15 above the through hole of 14) is shaped as a cone, a truncated circular cone, a pyramid or a truncated pyramid (a pyramid; Fig. 7, [0141]). Regarding claim 8, Okurama et al. teach the semiconductor structure according to claim 1, wherein a material of the first semiconductor layer (12/15) is a gallium nitride-based material (12 of GaN and 15 of GaN [0127, 0129]). Regarding claim 17, Okurama et al. teach the semiconductor structure according to claim 1, wherein an angle between the side surface (the left side surface) of each of the second protrusions (an upper portion of 15 above the through hole of 14; see Fig. 3B) and a horizontal plane (the horizontal plane in Fig. 3B) is a first angle (the angle between F1-F4 and the top surface of 14; Fig. 3B), and the first angle (the angle between F1-F4 and the top surface of 14) has a degree range (the degree range of F4 to the top surface of 14) of 40 degrees to 70 degrees (62° to 63°; [0129]). Regarding claim 18, Okurama et al. teach the semiconductor structure according to claim 1, wherein a width w of the second semiconductor layer (17) is less than or equal to 200 µm (the horizontal width of 17 at the top of 17 is 0 µm). Regarding claim 19, Okurama et al. teach the semiconductor structure according to claim 1, wherein a width w of the second semiconductor layer (17) is less than or equal to 100 µm (the horizontal width of 17 at the top of 17 is 0 µm). Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okurama et al. and Zhang et al. as applied to claim 1 above, and further in view of Kim et al. (US 20190371967 A1). Regarding claim 7, Okurama et al. teach the semiconductor structure according to claim 1, the second semiconductor layer (17) and the first electrode (18). Okurama et al. do not teach wherein a transparent electrode is further provided between the second semiconductor layer and the first electrode. In the same field of endeavor of light emitting device, Kim et al. teach wherein a transparent electrode (31; Fig. 4A, [0090]) is further provided between the second semiconductor layer (29; Fig. 4A, [0090]) and the first electrode (35; Fig. 4A, [0090]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Okurama et al., Zhang et al. and Kim et al., and to further include a transparent electrode between the second semiconductor layer and the first electrode as taught by Kim et al. ([0090]), because the transparent electrode can help to spread the electric current as taught by Kim et al. ([0090]). Response to Arguments Applicant's arguments with respect to claim 5 have been considered but are moot in view of the new ground(s) of rejection. On pages 9-10 of Applicant’s Response, Applicant argues that Zhang fails to disclose “the second semiconductor layer is a conductive Distributed Bragg Reflector (DBR) structure” recited in claim 1, based on that that Zhang (CN 110098295 A) does not teach the conductive DBR structure is direct contact with the active layer. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “the conductive DBR structure is direct contact with the active layer”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). On page 10 of Applicant’s Response, Applicant argues that the combination of Zhang and Okurama (US 2005/0145865 A1) would not make Okurama’s second semiconductor layer itself the conductive DBR structure recited in claim 1, and the Office Action fails to provide a reasoned explanation for replacing Okurama’s semiconductor layer with Zhang’s porous conductive DBR layer while preserving the claimed stack. The Examiner respectfully disagrees with Applicant’s argument, because the Office Action clearly shows how and why Zhang and Okurama are combined. Zhang and Okurama are combined by placing the conductive DBR structure 14 of Zhang et al. (i.e. “the second conductor layer is a conductive Distributed Bragg Reflector (DBR) structure” as claimed in claim 1) on the outer surface of the layer 17 of Okurama et al. under the layer 18 of Okurama et al., and also switching the polarity of layers of Okurama et al. to avoid forming the p-n junction on the layer 17 of Okurama et al. The reason and the motivation are that Okurama et al. teach that the light emitted from the active layer has to be reflected at the outer surface of the layer 17 to have efficient extract of the light ([0145]), while Zhang et al. teach that the conductive DBR structure 14 of Zhang et al. can provide high-reflectivity ([0035]), and the combination of Okurama et al. and Zhang et al. would put the conductive DBR structure in contact with the outer surface of the layer 17 of Okurama et al. to efficiently reflect the light arriving at the outer surface of the layer 17, and further provide the advantages of good conductivity, wide cutoff bandwidth, and easy adjustment of center wavelength ([0035] of Zhang et al.). The rejection still stands. On page 11 of Applicant’s Response, Applicant argues that Zhang fails to teach the one of the first holes has a first diameter different from a second diameter of one of the second holes recited in claim 1. The Examiner respectfully disagrees with Applicant’s argument, because Zhang teaches “one of the first holes (holes of the high-porosity porous GaN layers) has a first diameter (pore size, which can be 300 nm; [0015]) different from a second diameter (pore size, which can be 1 nm; [0015]) of one of the second holes (holes of the low-porosity porous GaN layers)” of claim 1 disclosed in the Office Action. Zhang mentioned in the paragraph [0015] that “the pore size of the porous conductive DBR layer is 1 to 300nm”. It would have been obvious to one of ordinary skill in the art to know that this range of pore sizes applied to both high-porosity porous GaN layers and low-porosity porous GaN layers for they both are parts of the porous conductive DBR layer. As the pore sizes have a range, one of the pores in the high-porosity porous GaN layers can have diameters different from the diameters of one of the pores in the high-porosity porous GaN layers. The rejection still stands. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Zhu et al. (US 2023/0361252 A1) teach a LED having a porous DBR layer. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HSIN YI HSIEH whose telephone number is (571)270-3043. The examiner can normally be reached 8:30 - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra V Smith can be reached on 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HSIN YI HSIEH/Primary Examiner, Art Unit 2899 8/21/2026
Read full office action

Prosecution Timeline

Mar 31, 2023
Application Filed
Feb 23, 2026
Non-Final Rejection mailed — §103
May 26, 2026
Response Filed
Aug 25, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
51%
Grant Probability
57%
With Interview (+5.7%)
3y 11m (~4m remaining)
Median Time to Grant
Moderate
PTA Risk
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