DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. If Applicant fails to provide a sufficiently descriptive title, Examiner will do so upon allowance of the claims.
Election/Restrictions
Applicant's election with traverse of Group I (claims 1-11) in the reply filed on 5/28/26 is acknowledged. The traversal is on the ground(s) that Feng does not disclose “the output control sub-circuit, … is configured to provide the signal of the first power supply terminal or a signal of the second power supply terminal to the signal output terminal under control of the second node” in claim 1 because “there is only one power supply terminal, i.e., VGL” (Remarks filed 5/28/26, p. 16). Examiner disagrees, as Applicant’s claim uses the term “or”. In other words, Applicant’s claim does not require providing both the first and second power supply signal to the output terminal. Applicant further states that Feng does not disclose “the node control sub-circuit, … provide the signal of the first node to the second node under control of the second clock signal terminal” (ibid, p. 16). Examiner disagrees, as Examiner may consider any node within Feng’s circuit as the “second node” as is claimed.
Additionally, Applicant’s arguments are moot in view of the rejection of the claims below (i.e., Applicant’s technical feature is not a special technical feature as it does not make a contribution over the prior art).
The requirement is still deemed proper and is therefore made FINAL.
Claims 12-19 and 24 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-6, 8, and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al. (US 2021/0118375).
Regarding claim 1, Yang discloses a shift register, comprising a storage sub-circuit, a node control sub-circuit and an output control sub-circuit (figs. 5-7, ¶ 89-99),
wherein: the storage sub-circuit, electrically connected to a first node and a first power supply terminal respectively, is configured to store a voltage difference between a signal of the first node and a signal of the first power supply terminal (figs. 6-10, ¶ 116-118, C1 connected between node N1 and low voltage line);
the node control sub-circuit, electrically connected to a signal input terminal, a first clock signal terminal, a second clock signal terminal, the first node and a second node respectively, is configured to provide a signal of the signal input terminal to the first node under control of the first clock signal terminal and provide the signal of the first node to the second node under control of the second clock signal terminal (figs. 6-10, ¶ 106-108, ¶ 121-123, T1 and T3 receive clock signals CLK1 and CLK2 to provide signal from input to N1 and N3);
and the output control sub-circuit, electrically connected to the second node, the first power supply terminal, a second power supply terminal and a signal output terminal respectively, is configured to provide the signal of the first power supply terminal or a signal of the second power supply terminal to the signal output terminal under control of the second node (figs. 6-10, ¶ 124-131, e.g., INV2 connected to N3, VGH, and VGL; see also ¶ 132-140).
Regarding claim 2, Yang discloses wherein the output control sub-circuit comprises a first output control sub-circuit and a second output control sub-circuit (figs. 6-10, ¶ 124-131, e.g., INV2 and INV3; see also ¶ 132-140),
wherein the first output control sub-circuit, electrically connected to the second node, a third node, the first power supply terminal and the second power supply terminal respectively, is configured to provide the signal of the first power supply terminal or the signal of the second power supply terminal to the third node under control of the second node (figs. 6-10, ¶ 124-131, e.g., INV2);
and the second output control sub-circuit, electrically connected to the third node, the first power supply terminal, the second power supply terminal and the signal output terminal respectively, is configured to provide the signal of the first power supply terminal or the signal of the second power supply terminal to the signal output terminal under control of the third node (figs. 6-10, ¶ 132-140, e.g., INV3 connected to node N4).
Regarding claim 4, Yang discloses wherein the storage sub-circuit comprises a capacitor comprising a first plate and a second plate, wherein the first plate of the capacitor is electrically connected to the first node, and the second plate of the capacitor is electrically connected to the first power supply terminal (figs. 6-10, ¶ 116-118, C1 connected between node N1 and low voltage line).
Regarding claim 5, Yang discloses wherein the node control sub-circuit comprises a first transistor and a second transistor (figs. 6-10, ¶ 106-108, ¶ 121-123, T1 and T3),
wherein a control electrode of the first transistor is electrically connected to the first clock signal terminal, a first electrode of the first transistor is electrically connected to the signal input terminal, and a second electrode of the first transistor is electrically connected to the first node (figs. 6-10, ¶ 106-108, e.g., T1 receives clock signal CLK1);
and a control electrode of the second transistor is electrically connected to the second clock signal terminal, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the second node (figs. 6-10, ¶ 121-123, e.g., T3 receives clock signal CLK2).
Regarding claim 6, Yang discloses wherein the first output control sub-circuit comprises a third transistor and a fourth transistor (figs. 6-10, ¶ 124-131, INV2 with T7 and T8),
and the second output control sub-circuit comprises a fifth transistor and a sixth transistor (figs. 6-10, ¶ 132-140, INV3 with T9 and T10),
wherein a control electrode of the third transistor is electrically connected to the second node, a first electrode of the third transistor is electrically connected to the first power supply terminal, and a second electrode of the third transistor is electrically connected to the third node (figs. 6-10, ¶ 124-131, e.g., T7);
a control electrode of the fourth transistor is electrically connected to the second node, a first electrode of the fourth transistor is electrically connected to the second power supply terminal, and a second electrode of the fourth transistor is electrically connected to the third node (figs. 6-10, ¶ 124-131, e.g., T8);
a control electrode of the fifth transistor is electrically connected to the third node, a first electrode of the fifth transistor is electrically connected to the first power supply terminal, and a second electrode of the fifth transistor is electrically connected to the signal output terminal (figs. 6-10, ¶ 132-140, e.g., T9);
a control electrode of the sixth transistor is electrically connected to the third node, a first electrode of the sixth transistor is electrically connected to the second power supply terminal, and a second electrode of the sixth transistor is electrically connected to the signal output terminal (figs. 6-10, ¶ 132-140, e.g., T10);
and the third transistor and the fourth transistor are of opposite types, and the fifth transistor and the sixth transistor are of opposite types (figs. 6-10, ¶ 124-131; see also ¶ 132-140).
Regarding claim 8, Yang discloses the first transistor, the second transistor, the third transistor and the fifth transistor are P-type transistors, and the fourth transistor and the sixth transistor are N-type transistors and are oxide transistors (figs. 6-10, ¶ 124-131; see also ¶ 132-140; see also ¶ 87, ¶ 113).
The remaining limitations of claim 8 are rejected under the same rationale as claims 4-6.
Regarding claim 10, Yang discloses wherein a clock signal of the first clock signal terminal and a clock signal of the second clock signal terminal are inverted signals with respect to each other (fig. 10, ¶ 149);
the signal of the signal input terminal is a first pulse signal, a duration of the first pulse signal is equal to a period of the clock signal of the first clock signal terminal (figs. 5-10, ¶ 149-160, e.g., SC(k-1) during t1 and t2);
and a signal of the signal output terminal is a second pulse signal, a duration of the second pulse signal is equal to the duration of the first pulse signal (figs. 5-10, ¶ 161-174, e.g., SC(k) during t3 and t4),
and start time of the second pulse signal is end time of the first pulse signal (fig. 10, e.g., SC(k-1) during t1 and t2, SC(k) during t3 and t4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 7, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Taya (US 2022/0028342).
Regarding claim 3, Yang fails to explicitly disclose a noise reduction sub-circuit, wherein the noise reduction sub-circuit, electrically connected to the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the second power supply terminal, the second node and the third node respectively, is configured to provide the signal of the first power supply terminal or the signal of the second power supply terminal to the second node under control of the first clock signal terminal, the second clock signal terminal and the third node.
Taya teaches a noise reduction sub-circuit, wherein the noise reduction sub-circuit, electrically connected to the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the second power supply terminal, the second node and the third node respectively, is configured to provide the signal of the first power supply terminal or the signal of the second power supply terminal to the second node under control of the first clock signal terminal, the second clock signal terminal and the third node (fig. 3, ¶ 40-50, e.g., clocked inverter 14 connected to VGH, GND, CK, and CKB).
Yang and Taya are both directed to shift register circuits for display driving. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Yang with the clocked inverter of Taya since such a modification provides a shift register that can easily initialize internal nodes (Taya, ¶ 8) and provides that even when the input signal is changed while the clock is at a high or low level, the output signal does not change (Taya, ¶ 49-50).
Regarding claim 7, Taya further teaches wherein the noise reduction sub- circuit comprises a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor (fig. 3, ¶ 40-50, e.g., transistors Q41, Q42, Q43, and Q44),
wherein a control electrode of the seventh transistor is electrically connected to the first clock signal terminal, a first electrode of the seventh transistor is electrically connected to the first power supply terminal, and a second electrode of the seventh transistor is electrically connected to a first electrode of the eighth transistor (fig. 3, ¶ 40-50, e.g., Q41);
a control electrode of the eighth transistor is electrically connected to the third node, and a second electrode of the eighth transistor is electrically connected to the second node (fig. 3, ¶ 40-50, e.g., Q42);
a control electrode of the ninth transistor is electrically connected to the third node, a first electrode of the ninth transistor is electrically connected to the second node, and a second electrode of the ninth transistor is electrically connected to a second electrode of the tenth transistor (fig. 3, ¶ 40-50, e.g., Q43);
a control electrode of the tenth transistor is electrically connected to the second clock signal terminal, and a first electrode of the tenth transistor is electrically connected to the second power supply terminal (fig. 3, ¶ 40-50, e.g., Q44);
and the seventh transistor and the eighth transistor are of a same type, the ninth transistor and the tenth transistor are of a same type, and the seventh transistor and the ninth transistor are of opposite types (fig. 3, ¶ 40-50, e.g., transistors Q41, Q42, Q43, and Q44).
Regarding claim 9, Yang discloses the first transistor, the second transistor, the third transistor, the fifth transistor, the seventh transistor and the eighth transistor are P-type transistors, and the fourth transistor, the sixth transistor, the ninth transistor and the tenth transistor are N-type transistors and are oxide transistors (figs. 6-10, ¶ 124-131; see also ¶ 132-140; see also ¶ 87, ¶ 113).
The remaining limitations of claim 9 are rejected under the same rationale as claims 3-7.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Xuan (US 2019/0073933).
Regarding claim 11, Yang discloses wherein a clock signal of the first clock signal terminal and a clock signal of the second clock signal terminal are inverted signals with respect to each other (fig. 10, ¶ 149);
the signal of the signal input terminal is a third pulse signal (figs. 5-10, ¶ 149-160, e.g., SC(k-1) during t1 and t2);
and a signal of the signal output terminal is a fourth pulse signal (figs. 5-10, ¶ 161-174, e.g., SC(k) during t3 and t4),
a duration of the fourth pulse signal is equal to the duration of the third pulse signal (fig. 10, e.g., SC(k-1) during t1 and t2, SC(k) during t3 and t4),
and a difference between start time of the fourth pulse signal and start time of the third pulse signal is equal to the period of the clock signal of the first clock signal terminal (fig. 10, e.g., SC(k-1) during t1 and t2, SC(k) during t3 and t4).
Yang fails to disclose a duration of the third pulse signal is equal to N times a period of the clock signal of the first clock signal terminal, N being a positive integer greater than or equal to 2.
Xuan teaches a duration of the third pulse signal is equal to N times a period of the clock signal of the first clock signal terminal, N being a positive integer greater than or equal to 2 (fig. 3, ¶ 57, ¶ 70, duration of signal is N times a pulse duration of the clock signal).
Yang and Xuan are both directed to shift register circuits for display driving. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Yang with the device of Xuan since such a modification provides a shift register having an adjustable duty cycle (Xuan, ¶ 70) that may be used in shift registers having different functions based on the duty cycle of the input signal (Xuan, ¶ 70).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: See attached Notice of References Cited.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEITH L CRAWLEY whose telephone number is (571)270-7616. The examiner can normally be reached Monday - Friday 10-6 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Temesghen Ghebretinsae can be reached at 571-272-3017. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KEITH L CRAWLEY/ Primary Examiner, Art Unit 2626
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