Non-Final Rejection
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This application was filed with claims 1-20, which are pending.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In the fifth to last line of claim 1 applicant uses the term “the lower wirings” which lacks antecedent basis. While plural upper wirings were introduced previously, plural lower wirings were never introduced so there is no antecedent basis.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 9-12, 16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0408768 (“Wang”) in view of US 2013/0163626 (“Seurin”).
Regarding claim 1, Wang discloses in Figs. 6-7 a semiconductor device comprising: a first substrate 603; a lower1 wiring 605/705 provided on the first substrate; a plurality of upper wirings 604/704 provided on the lower wiring via an insulation film 606; and a second substrate provided on the upper wirings via a plurality of elements. The VCSELs are the plurality of elements and have substrate where the “VCSEL 1” etc. labels are, like 106 of Fig. 1. The upper wirings 604/704 include a first wiring and a second wiring adjacent to each other in a first direction, and there is an opening in the upper wirings.2
Wang does not disclose that “the elements on the first wiring and the elements on the second wiring are connected in series to each other.” Seurin describes a similar system where numerous light emitting elements are formed on a substrate, and are then mounted on another substrate. Seurin shows in Fig. 8(b), starting at [0089], that separate array groups, which correspond to the elements on the first and second wirings, may be formed in series with each other. Compare to groups D1, D2, D3 of Fig. 1 of this application. It would have been obvious to a person of ordinary skill in the art to group the elements like this as it offers a multitude of design choices and expansion options for constructing a VCSEL array illuminator in a modular fashion, allowing various patterns of light in any desired shape, as taught by Seurin. [0096].
Regarding claim 2, any particular group of the elements of Wang are parallel. That is, one can see that the tops of VCSELs 1 and 2 in Fig. 7 share a connection at the top and bottom electrodes 704, they are in parallel. VCSEL 3 and others like it would be similar. See Fig. 10, showing groups of VCSELs sharing connections.
Regarding claim 3, the elements are VCSELs, light emitters.
Regarding claim 4, Wang shows a different embodiment in Fig. 9 where the light is emitted from the backside of the VCSEL, where the second substrate was. Wang states that the substrate was etched off, [0038], but a person of ordinary skill would understand that this does not need to be the case, as flip chip VCSELs are well known that merely use transparent substrates instead of removing them. It would have been obvious to a person of ordinary skill in the art to do so as this simplifies fabrication by not requiring this additional step of removing the substrate.
Regarding claim 5, the VCSELs may be arranged so that for one wiring the current flows in a first direction and for the other it flows in the opposite direction. For example, See Wang Fig. 5, [0031], where bond pads 501 and 502 are used to charge the different VCSELs and correspond to the upper and lower wiring, and one will go up in the figure while the other will go down.
Regarding claim 6, the second opening (in the upper wiring) is in the first direction, i.e. the direction in which wirings 604/704 are spaced.
Regarding claims 9-11 and 16, the width of the wirings in the second direction, i.e. into the page in Fig. 4 of Gerlach, is not shown. A person of ordinary skill would understand that the widths of wirings for powering devices such as these affect things like heat dissipation and resistance. It would have been obvious to a person of ordinary skill in the art to adjust the widths as needed to account for such things. This is essentially an optimization within routine conditions of a result effective variable, which does not support patentability. See MPEP 2144.05 II.
Regarding claim 12, as seen in Figs. 6-7 there can be openings in each of the upper and lower wirings. Note this is like the similar limitation of claim 1, except now it is claiming A or B and C or D, and A and C is met.
Regarding claim 18, as seen in Figs. 5, 10, the VCSELs are in a two-dimensional array, so the openings are likewise.
Regarding claim 19, it is apparent that the purpose of Wang is to create an irregular pattern of VCSELs by connecting different VCSELs to the upper and lower wirings. [0029]. It would have been obvious to a person of ordinary skill in the art that one of the wirings may be for wiring just one VCSEL, if that is the desired pattern of the user. In that case only one opening is provided in the upper wirings or in the lower wiring, like VCSEL 3 in Fig. 7.
Regarding claim 20, the materials of the substrates are not given. A person of ordinary skill would recognize that Si and GaAs are typical substrate materials in semiconductor devices and semiconductor lasers. It would have been obvious to a person of ordinary skill in the art to choose such known materials that are suitable substrates in these devices. See MPEP 2144.07.
Claims 1-4, 6, 9-13, 16, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0104873 (“Gerlach”) in view of US 2013/0163626 (“Seurin”).
Regarding claim 1, Gerlach discloses in Fig. 4 a semiconductor device comprising: a first substrate 144; a lower wiring 148 provided on the first substrate; a plurality of upper wirings 127 provided on the lower wiring via an insulation film 144 (it must be insulating, or else everything will be shorted together and nothing will work correctly); and a second substrate 110 provided on the upper wirings via a plurality of elements, the four VCSELs. [0042]. The upper wirings include a first wiring and a second wiring adjacent to each other in a first direction, and there is an opening in the upper wirings.
Gerlach does not disclose that “the elements on the first wiring and the elements on the second wiring are connected in series to each other.” Seurin describes a similar system where numerous light emitting elements are formed on a substrate, and are then mounted on another substrate. Seurin shows in Fig. 8(b), starting at [0089], that separate array groups, which correspond to the elements on the first and second wirings, may be formed in series with each other. Compare to groups D1, D2, D3 of Fig. 1 of this application. It would have been obvious to a person of ordinary skill in the art to group the elements like this as it offers a multitude of design choices and expansion options for constructing a VCSEL array illuminator in a modular fashion, allowing various patterns of light in any desired shape, as taught by Seurin. [0096]. These modular groups would likewise be considered to be on first and second wirings separated by openings.
Regarding claim 2, any particular group of the elements of Gerlach are parallel. That is, one can see that the tops and bottoms VCSEL the VCSELs share connections at the top and bottom electrodes 127,105, they are in parallel.
Regarding claims 3-4, the elements are VCSELs, light emitters and the light emitted is shown in Fig. 4 as passing through the second substrate 110 as claimed.
Regarding claim 6, the second opening (in the upper wiring) is in the first direction, i.e. the direction in which wirings are spaced. This would also be the case after modification by Suerin, when the first modular group is on the first wiring, second group is on the second wiring, etc.
Regarding claims 9-11 and 16, the width of the wirings in the second direction, i.e. into the page in Fig. 4 of Gerlach, is not shown. A person of ordinary skill would understand that the widths of wirings for powering devices such as these affect things like heat dissipation and resistance. It would have been obvious to a person of ordinary skill in the art to adjust the widths as needed to account for such things. This is essentially an optimization within routine conditions of a result effective variable, which does not support patentability. See MPEP 2144.05 II.
Regarding claim 12, as seen in Fig. 4 there can be openings in each of the upper and lower wirings. Note this is like the similar limitation of claim 1, except now it is claiming A or B and C or D, and A and C is met.
Regarding claim 13, as seen in Fig. 4 the openings in the lower and upper wirings face the other wiring vertically (flip the Fig. 90 degrees clockwise).
Regarding claim 18, as seen in Fig. 3, the VCSELs are in a two-dimensional array, so the openings are likewise.
Regarding claim 20, second substrate 110 is GaAs as claimed, [0042]. The material of the other substrate is not given. Gerlach does say the detectors in this substrate are silicon based, [0018], so we can consider that the substrate is Si as claimed. Alternatively, a person of ordinary skill would recognize that Si is a typical substrate material in semiconductor devices. It would have been obvious to a person of ordinary skill in the art to choose such known material that is suitable substrates in these devices. See MPEP 2144.07.
Allowable Subject Matter
Claims 7-8, 14-15, and 17 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 7, there is not taught or disclosed the device as in claim 1, wherein a plurality of openings extending in the first direction and adjacent to each other in the second direction is provided as the first or second openings.
Claims 8 and 17 are dependent on claim 7 and allowable for the same reasons.
Regarding claim 14, there is not taught or disclosed the device as in claim 12, wherein a plurality of openings extending in the first direction is provided as the first opening, the lower wiring includes a plurality of first parts extending in the first direction and a plurality of second parts extending in the second direction, and each of the plurality of openings is provided between the first parts adjacent to each other in the second direction.
Regarding claim 15, there is not taught or disclosed the device as in claim 12, wherein a plurality of openings extending in the first direction is provided as the second openings, and each of the plurality of openings is provided between the upper wirings adjacent to each other in the second direction.
All of these are getting at the wirings being like those in for example Fig. 11A, which is a side view compared to figures like Fig. 3. There is not shown in the art a device like that having the wirings with openings in that direction like claimed.
Conclusion
US 2015/0071320 also shows VCSEL subarrays in series, see Figs. 8-9, somewhat like Seurin.
Various other references are cited showing light emitters formed on a substrate and mounted to a different substrate having wirings.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to James Menefee whose telephone number is (571)272-1944. The examiner can normally be reached M-F 7-4.
Examiner interviews are available via telephone and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MinSun Harvey can be reached at (571) 272-1835. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of applications may be obtained from Patent Center. See: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JAMES A MENEFEE/ Primary Examiner, Art Unit 2828
1 Imagine Figs. 6-7 flipped upside down, then the directions “lower” and “upper” are more like the present application.
2 The last limitation of the claim reads “and a first opening is provided in the lower wiring or provided so as to be sandwiched between the lower wirings in a second direction different from the first direction, or a second opening is provided in the upper wirings or provided so as to be sandwiched between the upper wirings in the second direction.” This is essentially claiming “A or B or C or D” and the claim is met because C is met (a second opening is provided in the upper wirings).