DETAILED ACTION
This action is in response to the submission filed on 4/6/2023. Claims 1-20 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to because Figures 1-30 contain images and text which are extremely blurry and difficult to discern. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Applicant is directed towards 37 CFR § 1.84 - Standards for drawings:
(3) Numbers, letters, and reference characters must measure at least .32 cm. ( 1/8 inch) in height. They should not be placed in the drawing so as to interfere with its comprehension. Therefore, they should not cross or mingle with the lines. They should not be placed upon hatched or shaded surfaces. When necessary, such as indicating a surface or cross section, a reference character may be underlined and a blank space may be left in the hatching or shading where the character occurs so that it appears distinct.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 8 and 15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 9 and 17 of U.S. Patent No. US 11074388 B2 in view of US 20170344683 A1.
Current Application
U.S. Patent No. US 11074388 B2
US 20170344683 A1
Claim 1
A non-transitory medium holding computer-executable instructions for performing deformation and stress analysis modeling in a virtual fabrication environment, the instructions when executed causing at least one computing device to:
receive a selection of a process sequence in a process editor for a semiconductor device structure to be virtually fabricated;
receive a user-specified deformation and stress analysis modeling step inserted into the process sequence, the deformation and stress analysis modeling step indicating a designated point during the process sequence for deformation and stress analysis modeling to be performed;
perform with the computing device a virtual fabrication run that models an integrated process flow used to physically fabricate the semiconductor device structure by using the process sequence and 2D design data to simulate patterning, material addition and/or material removal steps performed to physically fabricate the semiconductor device structure, the virtual fabrication run:
executing the process sequence up until the deformation and stress analysis modeling step, the executing building a 3D structural model of the semiconductor device structure, the 3D structural model predictive of a result of a physical fabrication of the semiconductor device structure, and
performing the deformation and stress analysis modeling step, the deformation and stress analysis modeling step generating result data; and
output the result data generated from the deformation and stress analysis modeling step.
Claim 1:
A non-transitory computer-readable medium holding computing device-executable instructions for fabricating a semiconductor device structure in a virtual fabrication environment, the instructions when executed causing at least one computing device to:
receive a selection of a process sequence in a process editor for a semiconductor device structure to be virtually fabricated;
insert a user-specified virtual metrology measurement step into the process sequence, the virtual metrology measurement step indicating a point during the process sequence for a measurement to be performed;
perform with the computing device a virtual fabrication run that models an integrated process flow used to physically fabricate the semiconductor device structure by using the process sequence and 2D design data to simulate patterning, material addition and material removal steps performed to physically fabricate the semiconductor device structure, the virtual fabrication run:
executing the process sequence up until the virtual metrology measurement step, the executing building a 3D structural model of the semiconductor device structure, the 3D structural model including geometrically accurate 3D shapes predictive of a result of a physical fabrication of the semiconductor device structure, and
performing the measurement indicated by the virtual metrology measurement step within a region of the 3D structural model, the virtual metrology measurement step characterizing a three-dimensional aspect of the semiconductor device structure;
and export virtual metrology measurement data generated from the virtual metrology measurement step of the virtual fabrication run to an automated data analysis tool or a display.
paragraph [0051]:
"Electrical behavior engine 279 may include modeling engines for performing specific types of electrical modeling such … other modeling 274 related to semiconductor fabrication such as stress/strain analysis or thermal analysis. 3D modeling engine 275 may accept input data 220 in order to perform virtual fabrication “runs” that produce semiconductor device structural model data 290"
Claim 8
A computing device-implemented method for performing deformation and stress analysis modeling in a virtual fabrication environment, comprising:
receiving a selection of a process sequence in a process editor for a semiconductor device structure to be virtually fabricated, the process sequence including a user-specified deformation and stress analysis modeling step, the deformation and stress analysis modeling step indicating a point during the process sequence for deformation and stress analysis modeling to be performed;
performing with the computing device a virtual fabrication run that models an integrated process flow used to physically fabricate the semiconductor device structure by using the process sequence and 2D design data to simulate patterning, material addition and/or material removal steps performed to physically fabricate the semiconductor device structure, the virtual fabrication run:
executing the process sequence up until the deformation and stress analysis modeling step, the executing building a 3D structural model of the semiconductor device structure, the 3D structural model predictive of a result of a physical fabrication of the semiconductor device structure, and performing the deformation and stress analysis modeling step, the deformation and stress analysis modeling step generating result data; and
outputting the result data generated from the deformation and stress analysis modeling step.
Claim 9
A computing device-implemented method for fabricating a semiconductor device structure in a virtual fabrication environment provided by at least one computing device equipped with one or more processors, the method comprising:
receiving a selection of a process sequence in a process editor for a semiconductor device structure to be virtually fabricated;
inserting a user-specified virtual metrology measurement step into the process sequence, the virtual metrology measurement step indicating a point during the process sequence for a measurement to be performed;
performing with the computing device a virtual fabrication run that models an integrated process flow used to physically fabricate the semiconductor device structure by using the process sequence and 2D design data to simulate patterning, material addition and material removal steps performed to physically fabricate the semiconductor device structure, the virtual fabrication run:
executing the process sequence up until the virtual metrology measurement step, the executing building a 3D structural model of the semiconductor device structure, the 3D structural model including geometrically accurate 3D shapes predictive of a result of a physical fabrication of the semiconductor device structure, and performing the measurement indicated by the virtual metrology measurement step within a region of the 3D structural model, the virtual metrology measurement step characterizing a three-dimensional aspect of the semiconductor device structure;
and exporting virtual metrology measurement data generated from the virtual metrology measurement step of the virtual fabrication run to an automated data analysis tool or a display.
paragraph [0051]:
"Electrical behavior engine 279 may include modeling engines for performing specific types of electrical modeling such … other modeling 274 related to semiconductor fabrication such as stress/strain analysis or thermal analysis. 3D modeling engine 275 may accept input data 220 in order to perform virtual fabrication “runs” that produce semiconductor device structural model data 290"
Claim 15
A system for performing deformation and stress analysis modeling in a virtual fabrication environment, comprising:
at least one computing device equipped with one or more processors and configured to generate a virtual fabrication environment that includes a deformation and stress analysis modeling module, the deformation and stress analysis modeling module when executing:
receiving a selection of a process sequence in a process editor for a semiconductor device structure to be virtually fabricated, the process sequence including a user-specified deformation and stress analysis modeling step, the deformation and stress analysis modeling step indicating a point during the process sequence for deformation and stress analysis modeling to be performed;
performing with the computing device a virtual fabrication run that models an integrated process flow used to physically fabricate the semiconductor device structure by using the process sequence and 2D design data to simulate patterning, material addition and/or material removal steps performed to physically fabricate the semiconductor device structure, the virtual fabrication run:
executing the process sequence up until the deformation and stress analysis modeling step, the executing building a 3D structural model of the semiconductor device structure, the 3D structural model predictive of a result of a physical fabrication of the semiconductor device structure, and
performing the deformation and stress analysis modeling step, the deformation and stress analysis modeling step generating result data; and
a display in communication with the at least one computing device, the display configured to display the result data from the deformation and stress analysis modeling step.
17. A virtual fabrication system, comprising:
a computing device equipped with one or more processors and configured to receive input data with a 3D modeling engine, the input data including 2D design data and a process sequence for a semiconductor device structure to be virtually fabricated,
the process sequence including a user-specified virtual metrology measurement step indicating a point during the process sequence at which a measurement should be taken, the computing device configured to
perform a virtual fabrication run that models an integrated process flow used to physically fabricate the semiconductor device structure by using the process sequence and 2D design data to simulate patterning, material addition and material removal steps needed to physically fabricate the semiconductor device structure, the performing of the virtual fabrication run:
executing the process sequence up until the virtual metrology measurement step, the executing building a 3D structural model of the semiconductor device structure, the 3D structural model including geometrically accurate 3D shapes predictive of a result of a physical fabrication of the semiconductor device structure, and
performing the measurement indicated by the virtual metrology measurement step within a region of the 3D structural model, the virtual metrology measurement step characterizing a three-dimensional aspect of the semiconductor device structure; and a display surface in communication with the computing device,
the display surface configured to display the 3D structural model in a 3D view and to display virtual metrology measurement data generated by the performance of the virtual metrology measurement step.
paragraph [0051]:
"Electrical behavior engine 279 may include modeling engines for performing specific types of electrical modeling such … other modeling 274 related to semiconductor fabrication such as stress/strain analysis or thermal analysis. 3D modeling engine 275 may accept input data 220 in order to perform virtual fabrication “runs” that produce semiconductor device structural model data 290"
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Greiner (directed to predictive 3D virtual fabrication) and Kamon (directed to stress and deformation analysis) and arrived at predictive 3D virtual fabrication including stress and deformation analysis. One of ordinary skill in the art would have been motivated to make such a combination because “Fabricating experimental semiconductor wafers to measure electrical performance costs significant time and money, and so predicting behavior with software has been vital in technology development since the early days of integrated circuits. Electrical simulation tools that are often part of technology computer-aided design software suites have been used to simulate this electrical behavior to provide guidance in technology development” (Kamon: para [0003]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 20190286780 A1 (“Greiner”) in view of US 20170344683 A1 (“Kamon”).
Regarding claims 1, 8 and 15, Greiner teaches:
A non-transitory medium holding computer-executable instructions for performing deformation and stress analysis modeling in a virtual fabrication environment (Greiner: Abstract, claim 21), the instructions when executed causing at least one computing device to:
receive a selection of a process sequence in a process editor for a semiconductor device structure to be virtually fabricated (Greiner: claim 21, “receive a selection of a process sequence in a process editor for a semiconductor device structure to be virtually fabricated;”);
perform with the computing device a virtual fabrication run that models an integrated process flow used to physically fabricate the semiconductor device structure by using the process sequence and 2D design data to simulate patterning, material addition and/or material removal steps performed to physically fabricate the semiconductor device structure (Greiner: claim 21, “perform with the computing device a virtual fabrication run that models an integrated process flow used to physically fabricate the semiconductor device structure by using the process sequence and 2D design data to simulate patterning, material addition and material removal steps performed to physically fabricate the semiconductor device structure”), the virtual fabrication run:
executing the process sequence, the executing building a 3D structural model of the semiconductor device structure, the 3D structural model predictive of a result of a physical fabrication of the semiconductor device structure (Greiner: claim 21, “executing the process sequence up until the virtual metrology measurement step, the executing building a 3D structural model of the semiconductor device structure, the 3D structural model predictive of a result of a physical fabrication of the semiconductor device structure, ”), and
Greiner does not teach but Kamon does teach:
receive a user-specified deformation and stress analysis modeling step inserted into the process sequence, the deformation and stress analysis modeling step indicating a designated point during the process sequence for deformation and stress analysis modeling to be performed (Kamon: paragraph [0051]: "Computing device 210 may store and execute virtual fabrication application 270 including 3D modeling engine 275 and electrical behavior modeling engine 279. 3D modeling engine 275 may include one or more algorithms such as algorithm 1 (276), algorithm 2 (277), and algorithm 3 (278) used in virtually fabricating semiconductor device structures. Electrical behavior engine 279 may include modeling engines for performing specific types of electrical modeling such … other modeling 274 related to semiconductor fabrication such as stress/strain analysis or thermal analysis. 3D modeling engine 275 may accept input data 220 in order to perform virtual fabrication “runs” that produce semiconductor device structural model data 290."; paragraph [0099]; Figure 12: "the 3D viewer 225 may display saved states 1204 in the process sequence and allow a particular state to be selected 1206 and appear in the 3D view canvas 120");
performing the deformation and stress analysis modeling step, the deformation and stress analysis modeling step generating result data (Kamon: paragraph [0051]: "3D modeling engine 275 may include one or more algorithms such as algorithm 1 (276), algorithm 2 (277), and algorithm 3 (278) used in virtually fabricating semiconductor device structures. Electrical behavior engine 279 may include modeling engines for performing specific types of electrical modeling such … other modeling 274 related to semiconductor fabrication such as stress/strain analysis or thermal analysis”); and
output the result data generated from the deformation and stress analysis modeling step (Kamon: para [0101], “The 3D modeling engine may export or display the electrical behavior data generated by the electrical behavior modeling step (step 1112). The electrical data may be displayed to a user in the 3D viewer 125 along with the a depiction of the current state of the 3D structural model at one or more points in the process sequence. The 3D modeling engine may also export the electrical behavior data. For example, the electrical behavior data 80 may be exported to an automatic data analysis tool for further processing or may be displayed to a user through a user interface such as the tabular and electrical behavior modeling results view 224 or other view”).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Greiner (directed to predictive 3D virtual fabrication) and Kamon (directed to stress and deformation analysis) and arrived at predictive 3D virtual fabrication including stress and deformation analysis. One of ordinary skill in the art would have been motivated to make such a combination because “Fabricating experimental semiconductor wafers to measure electrical performance costs significant time and money, and so predicting behavior with software has been vital in technology development since the early days of integrated circuits. Electrical simulation tools that are often part of technology computer-aided design software suites have been used to simulate this electrical behavior to provide guidance in technology development” (Kamon: para [0003]).
Regarding claims 2, 9 and 16, Greiner and Kamon teach:
The medium of claim 1 wherein the result data is displayed in a 3D graphical view of the 3D structural model (Greiner: para [0014], “FIG. 6 depicts an exemplary 3D viewer utilized in an embodiment of the present invention”).
Regarding claims 3, 10 and 19, Greiner teaches:
The medium of claim 1 wherein the instructions when executed cause the at least one computing device to:
receive a plurality of steps at designated locations in the process sequence; and generate a plurality of result data for the plurality of steps (Greiner: claim 25, “receive a specification of a set of parameter variations for the process sequence or the 2D design data; and perform a plurality of virtual fabrication runs in a virtual experiment that build a plurality of 3D structural models using the parameter variations, wherein the virtual metrology measurement data is generated for each parameter variation”).
Greiner does not teach but Kamon does teach:
deformation and stress analysis (Kamon: paragraph [0051]: "3D modeling engine 275 may include one or more algorithms such as algorithm 1 (276), algorithm 2 (277), and algorithm 3 (278) used in virtually fabricating semiconductor device structures. Electrical behavior engine 279 may include modeling engines for performing specific types of electrical modeling such … other modeling 274 related to semiconductor fabrication such as stress/strain analysis or thermal analysis")
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Greiner (directed to predictive 3D virtual fabrication) and Kamon (directed to stress and deformation analysis) and arrived at predictive 3D virtual fabrication including stress and deformation analysis. One of ordinary skill in the art would have been motivated to make such a combination because “Fabricating experimental semiconductor wafers to measure electrical performance costs significant time and money, and so predicting behavior with software has been vital in technology development since the early days of integrated circuits. Electrical simulation tools that are often part of technology computer-aided design software suites have been used to simulate this electrical behavior to provide guidance in technology development” (Kamon: para [0003]).
Regarding claims 4, 11, and 18, Greiner and Kamon teach:
The medium of claim 3 wherein the plurality of result data is displayed in a 3D graphical view of the 3D structural model (Greiner: para [0042], “3D structural model data 90 may be used to generate a 3D view of the structural model of the semiconductor device structure which may be displayed in the 3D viewer”).
Regarding claims 5, 12 and 19, Greiner does not teach but Kamon does teach:
The medium of claim 1, wherein the 3D structural model is a voxel-based model that uses an implicit geometry representation that includes a plurality of voxels arranged in a voxel grid and the deformation and stress analysis modeling step performs: identification of interfaces between different materials in the plurality of voxels based on volume fraction data for each voxel (Kamon: para [0087], “Geometric data represented with voxels implicitly represents the interface between materials. FIG. 10B illustrates this concept in two dimensions for a circle. A B-rep representation 1012 may represent the circle as the equation of a circle with radius R with material 1 inside the circle with material 2 outside. A voxel representation of the circle 1011 is an array of cubes where each cube stores the material identification numbers within it, and the relative amounts of each material. The grayscale darkness of the squares in 1011 indicate the relative percentage of material 1 versus material 2. Black indicates 100% material 1 and 0% material 2, and white indicates 0% material 1 and 100% material 2. Since the circle cuts through the voxels along its path, grayscale voxels on the boundary of the circle are partially filled with each material and the darkness of gray indicates the fill fraction. Partially filled voxels indicate that the boundary crosses through that voxel, but does not indicate where and with what orientation. The fill fractions of a boundary voxel and others in its neighborhood may be used to determine the boundary explicitly. While the determined boundary could then be used to generate a conformal volume mesh of the geometry, it would take considerable computation time which is non-desirable in the virtual fabrication environment”).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Greiner (directed to predictive 3D virtual fabrication) and Kamon (directed to voxel based modeling) and arrived at predictive 3D virtual fabrication including voxel based modeling. One of ordinary skill in the art would have been motivated to make such a combination because “Fabricating experimental semiconductor wafers to measure electrical performance costs significant time and money, and so predicting behavior with software has been vital in technology development since the early days of integrated circuits. Electrical simulation tools that are often part of technology computer-aided design software suites have been used to simulate this electrical behavior to provide guidance in technology development” (Kamon: para [0003]).
Regarding claims 6, 13 and 20, Greiner does not teach but Kamon does teach:
The medium of claim 5, wherein the deformation and stress analysis modeling step performs a coarsening operation on the voxel grid (Kamon: [0091], “As an illustrative example of the effectiveness of the use of voxel-based implicit representations in a virtual fabrication environment, FIG. 10D depicts a cross-sectional slice of two concentric spherical shells, 1032 and 1033 with a first dielectric 1031 and second dielectric 1036 between the shells. Concentric spherical shells 1032 and 1033 are composed of conducting material and form two electrical nets between which the capacitance is calculated in this example. A plot 1035 depicts the determined error in the capacitance as the voxel size is increased when using an effective permittivity method between 1031 and 1036 and a numerical solution technique as described herein. Model resolution is the size of the voxels in each dimension. Less than 1% capacitance error is achieved for a model resolution of 3, which gives an inner net 1033 that is 6 times coarser than the circle 1011 shown in FIG. 10B. This technique therefore provides high accuracy in results for such a coarse representation of the geometry, thereby leading to faster electrical behavior computation time in the virtual fabrication environment”).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Greiner (directed to predictive 3D virtual fabrication) and Kamon (directed to coarsening of the grid) and arrived at predictive 3D virtual fabrication including coarsening of the grid. One of ordinary skill in the art would have been motivated to make such a combination because “Fabricating experimental semiconductor wafers to measure electrical performance costs significant time and money, and so predicting behavior with software has been vital in technology development since the early days of integrated circuits. Electrical simulation tools that are often part of technology computer-aided design software suites have been used to simulate this electrical behavior to provide guidance in technology development” (Kamon: para [0003]).
Regarding claims 7 and 14, Greiner does not teach but Kamon does teach:
The medium of claim 6, wherein the coarsening operation is an adaptive coarsening operation where the voxel grid is coarsened away from material interfaces (Kamon: [0091], “As an illustrative example of the effectiveness of the use of voxel-based implicit representations in a virtual fabrication environment, FIG. 10D depicts a cross-sectional slice of two concentric spherical shells, 1032 and 1033 with a first dielectric 1031 and second dielectric 1036 between the shells. Concentric spherical shells 1032 and 1033 are composed of conducting material and form two electrical nets between which the capacitance is calculated in this example. A plot 1035 depicts the determined error in the capacitance as the voxel size is increased when using an effective permittivity method between 1031 and 1036 and a numerical solution technique as described herein. Model resolution is the size of the voxels in each dimension. Less than 1% capacitance error is achieved for a model resolution of 3, which gives an inner net 1033 that is 6 times coarser than the circle 1011 shown in FIG. 10B. This technique therefore provides high accuracy in results for such a coarse representation of the geometry, thereby leading to faster electrical behavior computation time in the virtual fabrication environment”).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Greiner (directed to predictive 3D virtual fabrication) and Kamon (directed to coarsening of the grid) and arrived at predictive 3D virtual fabrication including coarsening of the grid. One of ordinary skill in the art would have been motivated to make such a combination because “Fabricating experimental semiconductor wafers to measure electrical performance costs significant time and money, and so predicting behavior with software has been vital in technology development since the early days of integrated circuits. Electrical simulation tools that are often part of technology computer-aided design software suites have been used to simulate this electrical behavior to provide guidance in technology development” (Kamon: para [0003]).
Additional References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure and are cited in the attached PTOL-892.
US-20140278266-A1: System and method for modeling epitaxial growth in a 3-D virtual fabrication environment
US-20140282302-A1: Multi-etch Process Using Material-specific Behavioral Parameters In 3-D Virtual Fabrication Environment
US-20140282324-A1: Predictive 3-D virtual fabrication system and method
US-20160217233-A1: System and method for performing directed self-assembly in a 3-D virtual fabrication environment
US-8832620-B1: Rule Checks In 3-D Virtual Fabrication Environment
US-9659126-B2: Modeling Pattern Dependent Effects For A 3-D Virtual Semiconductor Fabrication Environment
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NITHYA J. MOLL whose telephone number is (571)270-1003. The examiner can normally be reached Monday-Friday 10am-6pm EST.
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/NITHYA J. MOLL/Primary Examiner, Art Unit 2189
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