DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 04/08/2026 have been fully considered but they are not persuasive.
It is argued by the applicant that claims 1 and 16 are currently amended to explicitly express that the plurality of first pixel circuits are arranged in the second display region. However, note that claim 1 is not amended to explicitly express that the plurality of first pixel circuits are arranged in the second display region.
Claim 1 recites “a plurality of first pixel circuits between the base substrate and the first insulating layer, and arranged in the second display region”,
As such Yoon discloses a plurality of first pixel circuits (all TFTS 210s) between the base substrate and the first insulating layer (all TFTs 210s are between the base substrate and the first insulating layer), and arranged in the second display region (since all TFTs 210s are between the base substrate and the first insulating layer, and therefore some of the TFTs 210s are arranged in the second display region as claimed).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3-15 and 22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, line 16 recites “a plurality of first pixel circuits between the base substrate and the first insulating layer, and arranged in the second display region” is unclear and indefinite as to what is “arranged in the second display region”.
For example, another element (some-non-A-to-Z-element) different from “a plurality of first pixel circuits” such as (A-Z pixel circuits), (being some-non-A-to-Z-element) can be arranged in the second display region; or
another example, a plurality of first pixel circuits (A-Z pixel circuits) between the base substrate and the first insulating layer (A-Z pixel circuits are between the base substrate and the first insulating layer), and arranged in the second display region (since A-Z pixel circuits are between the base substrate and the first insulating layer, and therefore some of the A-Z pixel circuits) between the base substrate and the first insulating layer are arranged in the second display region as claimed – example will considered this to be such interpretation.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 6, 12-13 and 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoon et al. 20180047802.
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Regarding claim 1 (insofar to incompliance with 112 2nd), figs. 1-5 of Yoon discloses a display panel, comprising:
a base substrate 100;
a first insulating layer (composite layer of 125 and 160) on a side of the base substrate;
wherein the first insulating layer comprises a plurality of grooves (fig. 5) and a plurality of protrusions on a side of the first insulating layer away from the base substrate and alternately arranged in sequence;
each groove comprises a side wall and a bottom surface, and each protrusion comprises a top surface; and
traces (215c1/215c2 – fig. 5) on the side of the first insulating layer away from the base substrate,
wherein the traces comprise first traces 215c1 and second traces 215c2, each first trace is on a side of the top surface of the corresponding protrusion away from the base substrate, each second trace is on the bottom surface of the corresponding groove, and the first traces are disconnected from the second traces;
wherein the display panel comprises a first display region (P – pixel region) and a second display region (another P – pixel region) at an outer edge (each Pixel region has a defining boundary which is a type of outer edge – this interpretation is consistent with applicant b1 of applicant’s fig. 2) of the first display region, wherein the display panel comprises:
a plurality of first pixel circuits (all TFTS 210s) between the base substrate and the first insulating layer (all TFTs 210s are between the base substrate and the first insulating layer), and arranged in the second display region (since all TFTs 210s are between the base substrate and the first insulating layer, and therefore some of the TFTs 210s are arranged in the second display region); and
light emitting devices 300 on a side (top side) of the traces away from the base substrate and in the first display region (each pixel including the first display region has a 300),
wherein each trace is used for electrically connecting the corresponding first pixel circuit and the corresponding light emitting device (par [0095] - the wire 215c may be electrically connected to the TFT, etc., in the display area DA via the first conductive layer 213a),
so that the corresponding first pixel circuit drives the corresponding light emitting device to emit light (see fig. 3).
Regarding claim 6, fig. 3 of Yoon discloses wherein the display panel further comprises an under-screen functional region 510 (this under 520 which is a type of screen), and an orthographic projection of the first display region on the base substrate overlaps with an orthographic projection of the under-screen functional region on the base substrate.
Regarding claim 12, fig. 3 of Yoon discloses further comprising: a third insulating layer 150 on a surface of the first insulating layer close to the base substrate, wherein an orthographic projection of the first insulating layer on the base substrate covers an orthographic projection of the third insulating layer on the base substrate, and the orthographic projection of the third insulating layer on the base substrate does not overlap with an orthographic projection of each groove on the base substrate to have a non-overlapping region therebetween.
Regarding claim 13, fig. 3 of Yoon discloses further comprising: a fourth insulating layer 600 on a surface of the first insulating layer close to the base substrate, wherein an orthographic projection of the fourth insulating layer on the base substrate covers an orthographic projection of each groove on the base substrate.
Regarding claim 22, fig. 3 of Yoon discloses a display apparatus, comprising: the display panel according to claim 1, which comprises a first display region P and a second display region (another P); wherein the display panel comprises an under-screen functional region 510 (which is under 520), and an orthographic projection of the under-screen functional region on the display panel overlaps with an orthographic projection of the first display region on the display panel.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Yoon.
Regarding claim 3, Yoon discloses claim 1. Fig. 5 of Yoon discloses wherein an angle between the side wall of each groove and a plane where the bottom surface of the groove is located is in a range from 65° to 90°. Yoon does not disclose a depth of each groove is h1-h2.
Yoon does not disclose a depth of each groove is in a range from 100 nm to 480 nm.
However, although Yoon is silent about the claimed range, it should be noted that a range inherently exist.
Therefore, the prior art of Yoon provides foundation for experimental optimization and suggests a progress of changes in size/proportion in order to have thick enough interlayer insulating layer.
Therefore, while the structure of Yoon does not quantitatively state a range, the courts have held that when the only difference between the claimed invention and the prior art is a size/proportion, then a prima facie case of obviousness exists [See MPEP 2144.04(IV)(A)].
Therefore, it would have been obvious to one of ordinary skill in the art to form a device of Yoon wherein a depth of each groove is in a range from 100 nm to 480 nm order to have thick enough interlayer insulating layer.
Regarding claim 4, Yoon discloses claim 1. Yoon does not disclose of wherein a horizontal distance between the first trace and the second trace adjacent to each other is in a range from 1.8 μm to 2.5 μm.
However, although Yoon is silent about the claimed range, it should be noted that a range inherently exist.
Therefore, the prior art of Yoon provides foundation for experimental optimization and suggests a progress of changes in size/proportion in order to have thick enough interlayer insulating layer.
Therefore, while the structure of Yoon does not quantitatively state a range, the courts have held that when the only difference between the claimed invention and the prior art is a size/proportion, then a prima facie case of obviousness exists [See MPEP 2144.04(IV)(A)].
Therefore, it would have been obvious to one of ordinary skill in the art to form a device of Yoon wherein a horizontal distance between the first trace and the second trace adjacent to each other is in a range from 1.8 μm to 2.5 μm in order to prevent short circuit.
Regarding claim 5, Yoon discloses claim 1. Fig. 5 of Yoon disclose wherein the plurality of grooves do not penetrate through the first insulating layer. Yoon does not disclose a thickness of the first insulating layer at the bottom surface is in a range from 20 nm to 50 nm.
However, although Yoon is silent about the claimed range, it should be noted that a range inherently exist.
Therefore, the prior art of Yoon provides foundation for experimental optimization and suggests a progress of changes in size/proportion in order to have thick enough interlayer insulating layer.
Therefore, while the structure of Yoon does not quantitatively state a range, the courts have held that when the only difference between the claimed invention and the prior art is a size/proportion, then a prima facie case of obviousness exists [See MPEP 2144.04(IV)(A)].
Therefore, it would have been obvious to one of ordinary skill in the art to form a device of Yoon wherein a thickness of the first insulating layer at the bottom surface is in a range from 20 nm to 50 nm in order to meet applicant thickness specification.
Allowable Subject Matter
Claims 7-8, 11 and 14-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/VONGSAVANH SENGDARA/Primary Examiner, Art Unit 2893