DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/14/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5-6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Saito et al. US Pub 2018/0309308 (hereinafter Saito).
Regarding claim 1, Saito teaches a battery management system (BMS) printed circuit board assembly (PCBA) for managing a battery (fig. 1, element 2) comprising:
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a plurality of solid-state power transistors in back-to-back serial configuration (see fig. 1, elements 3 and 4; the charge control FET and the discharge control FET in back-to-back serial configuration) configured to connect and disconnect the battery (¶¶ 0009, 0025-0026, 0028-0032; turning on/off elements 3 and 4), and to function as resettable fuse (repeatedly turning on/off by a control circuit),
gate drive circuitries configured to turn on and off the solid-state power transistors (¶¶ 0025, 0028; turns off the charge control FET3 and instruct turning on of the charge control FET3 to the control circuit…the control circuit turns on the charge control FET3),
one or more shunt resistors configured for current sensing (¶ 0026; detecting the overcurrent situation),
a battery monitoring application-specific integrated circuit (ASIC) (fig. 1, element 1a), and a microprocessor (fig. 1; overcurrent detection circuit and control circuit 1b are able to receive inputs, process inputs, and generate output signal and ¶ 0026),
wherein the battery monitoring ASIC (claim 1; a charge/discharging monitoring circuit configured to output a signal to instruct turning off of the charge control FET or the discharging control FET to the control circuit in response to detection of overcharge or overdischarge of the secondary battery) and the microprocessor (claim 1; an overcurrent detection circuit configured to output a signal to instruct turning off of the discharge control FET to the control circuit according to the detection of a discharge overcurrent) are configured to provide redundant overcurrent detection (¶ 0026; in such an overcharge detection state, the load 30 is connected between the charge/discharge terminal P+ and the discharge terminal DIS-, and the load 30 goes into an abnormal state to make a large current flow, then a potential difference developed across the resistor becomes large, exceeding a voltage determined to be a discharge overcurrent. The overcurrent detection circuit 1c detects the discharge overcurrent and outputs signal to instruct turning off of the discharge control FET4 to the control circuit 1b; further claim 1; a charge/discharging monitoring circuit configured to output a signal to instruct turning off of the charge control FET or the discharging control FET to the control circuit in response to detection of overcharge or overdischarge of the secondary battery.
1) The charge/discharge monitoring circuit continuously monitors the battery’s voltage level and provide control signals when the battery reaches overcharge voltage, because the charge/discharge monitoring circuit monitors battery voltage directly, it can determine abnormal conditions that can be caused by excessive current (e.g., a sudden voltage drop or rise outside normal range, and excessive charging current can cause overcharge by driving the battery voltage rise above its safe limit), then the charge/discharging monitoring circuit configured to output a signal to instruct turning off of the charge control FET or the discharging control FET to the control circuit in response to detection of overcharge or overdischarge of the secondary battery.
2) The overcurrent detection circuit 1c directly detects the discharge overcurrent and outputs signal to instruct turning off of the discharge control FET4 to the control circuit 1b in ¶ 0026 and claim 1. Therefore, the charge/discharge monitoring circuit and the overcurrent detection circuit provide redundant overcurrent detection).
Regarding claim 5, Saito teaches wherein the gate drive circuitries comprise of a fast gate turn-off circuit configured to turn off the transistors when responding to an over-current fault (¶ 0026 and claim 1; able to turn on/off the FET/MOSFET).
Regarding claim 6, Saito teaches wherein the gate drive circuitries comprise of a charge pump circuit configured to turn on and off the solid-state power transistors (¶ 0026 and claim 1; capable of turning on/off the switches).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saito et al. US Pub 2018/0309308 (hereinafter Saito).
Regarding claim 2, Saito teaches wherein the plurality of solid-state power transistors are arranged in a common drain configuration. Rearranging the order of the first FET and the second FET in the circuit, does not show any criticality, is only considered to be an obvious modification of the Saito device that a person having ordinary skill in the art before the effective filing date of the claimed invention would be able to provide using routine experimentation since the courts have held that there is no invention in shifting the position if the operation of the device would not be thereby modified. See In re Japikse, 86 USPQ 70 (CCPA 1950) and MPEP 2144.04 VI.
Claim(s) 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saito in view of Klowak et al. US 2016/0240471 (hereinafter Klowak).
Regarding claim 3, Saito fails to teach wherein the plurality of solid-state power transistors comprise drain pins connected to large copper pads with vias to cool the solid-state power transistors through surrounding air convection.
Klowak further discloses wherein the plurality of solid-state power transistors (¶ 0067; GaN chip includes a silicon substrate and overlying GaN semiconductor layers, defining a large area lateral GaN power transistor) comprise drain pins connected to large copper pads with vias (¶ 0068; vias or contact openings are provided through the polyimide layer to expose the underlying on-chip metal layer. The Cu RDL fills the contact openings to provide larger area source and drain interconnects…the thick back-side copper foil layer is patterned to define the external contact pads) to cool the solid-state power transistors through surrounding air convection (¶ 0037; copper layer is attached for thermal dissipation).
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify Saito to incorporate with the teaching of Klowak by including a back-side copper layer providing a back-side heat-plate, because it would be advantageous to increase lifetime of switching devices and avoid package cracking.
Regarding claim 4, Saito fails to teach the BMS PCBA further comprising a metal clad or metal core printed circuit board (PCB).
Klowak further discloses the BMS PCBA further comprising a metal clad or metal core printed circuit board (PCB) (¶¶ 0083-0086; underlying copper foil layers, to respective contact areas and then plating copper therein, to form conducive copper pillars and/or posts…Thus the package can be mounted on an underlying thermal subtract, e.g. on a printed circuit board providing thermal vias for heat dissipation from the external thermal pad of the package, and corresponding source, drain, gate and source sense contact areas for electrical connections).
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify Saito to incorporate with the teaching of Klowak by including a back-side copper layer providing a back-side heat-plate, because it would be advantageous to reduce silicon aging rate and prolong the service of the device.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saito in view of Kang (US Pub 2017/0025872)
Regarding claim 7, Saito fails to teach the BMS PCBA further comprising a pre-charge circuit using MOSFET and resistors connected in parallel to one or more of the solid-state power transistors.
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However, Kang further discloses a pre-charge circuit (including a resistor R, a relay 114) using MOSFET and resistors connected in parallel (see fig. 2, elements R and 114 connected in parallel with element 112) to one or more of the solid-state power transistors (fig. 2 and ¶¶ 0066, 0068, 0071, 0074).
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify Saito to incorporate with the teaching of Kang by including a pre-charge circuit in the system, because it would be advantageous to prevent damage of the main switching device due to input of an inrush current generated.
Conclusion
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/ZIXUAN ZHOU/Primary Examiner, Art Unit 2859 01/23/2026