Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 14 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Applicant points to the embodiment shown in fig. 10 for support. However, the embodiment in fig. 10 does not teach “the first metal layer and the second metal layer are disposed to face each other in a second direction”.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-4,6,7,16-18,20-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Aoyagi et al (PG Pub 2017/0358711 A1) and Ohno (PG Pub 2014/0014998 A1).
Regarding claim 1, Aoyagi teaches a semiconductor light emitting device comprising: an active layer (23, fig. 6, paragraph [0056]) disposed on a first conductive semiconductor layer (21, paragraph [00567]); a first metal electrode layer (31, Table) disposed on the first conductive semiconductor layer; a second conductive semiconductor layer (22A/22B) disposed on the active layer; a metal-semiconductor (MS) contact layer (32, Table 1) disposed on an upper surface of the second conductive semiconductor layer: wherein a contact surface between the upper surface of the second conductive semiconductor layer and the MS layer is smaller than an upper surface area of the active layer (fig. 6).
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Aoyagi does not teach a second metal electrode layer covering the MS contact layer.
In the same field of endeavor, Ohno teaches a second metal electrode layer (23, fig. 7, paragraph [0060]) covering the MS contact layer (22), for the benefit of providing a wire bonding layer (paragraph [0060]) to allow external bias input to the device.
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention include a second metal electrode layer covering the MS contact layer, for the benefit of providing a wire bonding layer to allow external bias input to the device.
Regarding claim 2, Aoyagi teaches the semiconductor light emitting device of claim 1, wherein an area of one surface of the second conductive semiconductor layer (upper surface of 22B, fig. 6) is different from an area of another surface (lower surface of 22A) in contact with the active layer.
Regarding claim 3, Aoyagi teaches the semiconductor light emitting device of claim 1, wherein the second conductive semiconductor layer is formed in a mesa structure (fig. 6).
Regarding claim 4, Aoyagi teaches the semiconductor light emitting device of claim 1, wherein an area of one surface of the second conductive semiconductor layer corresponds to an effective light emitting area (black arrows, paragraph [0066], fig. 6).
Regarding claim 6, Aoyagi does not teach cross-sectional areas of the first metal layer and the second metal layer are identical. Aoyagi teaches to adjust the parameters in A to F (paragraph [0037]) to achieve the expression of 0≤J1/J2≤0.5.
It would have been obvious to the skilled in the art before the effective filing date of the invention to adjust the cross-sectional areas of the first metal layer and the second metal layer, to be identical, for example, to achieve the relative value of J1 to J2 according to the expression in paragraph [0037]: The electrical resistivity (condition A, paragraph [0037]), for example, is related to the cross-sectional areas of the first metal layer and the second metal layer. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Regarding claim 7, Aoyagi does not teach the MS contact layer is formed in ohmic contact.
Ohno teaches the MS contact layer is formed in ohmic contact (22, paragraph [0059]), for the known benefit of reducing contact resistance.
It would have been obvious to the skilled in the art before the effective filing date of the invention to form the MS contact layer in ohmic contact, for the known benefit of reducing contact resistance.
Regarding claim 16, Aoyagi teaches a semiconductor light emitting device comprising: an active layer (23, paragraph [0056], fig. 6) disposed on a first conductive semiconductor layer (21, paragraph [00567]); a first metal electrode layer (31, Table) disposed on the first conductive semiconductor layer; a second conductive semiconductor layer (22A/22B) disposed on the active layer; a metal-semiconductor (MS) contact layer (32, Table 1) disposed on an upper surface of the second conductive semiconductor layer; wherein the second conductive semiconductor layer includes an upper part and a lower part having a larger cross-sectional area than the upper part (fig. 6), and wherein a contact surface between the upper surface of the second conductive semiconductor layer and the MS layer is smaller than an upper surface area of the active layer (see fig. 6 attached above).
Aoyagi does not teach a second metal electrode layer covering the MS contact layer.
In the same field of endeavor, Ohno teaches a second metal electrode layer (23, fig. 7, paragraph [0060]) covering the MS contact layer (22), for the benefit of providing a wire bonding layer (paragraph [0060]) to allow external bias input to the device.
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention include a second metal electrode layer covering the MS contact layer, for the benefit of providing a wire bonding layer to allow external bias input to the device.
Regarding claim 17, Aoyagi teaches the semiconductor light emitting device of claim 16, wherein the second conductive semiconductor layer is formed in a mesa structure (fig. 6).
Regarding claim 18, Aoyagi teaches the semiconductor light emitting device of claim 16, wherein an area of one surface of the second conductive semiconductor layer corresponds to an effective light emitting area (paragraph [0066], fig. 6, black arrows).
Regarding claim 20, Aoyagi teaches the semiconductor light emitting device of claim 16, wherein: the first conductive semiconductor layer has a second region (left portion of 21, fig. 6) with a step difference in a first direction (vertical direction) for a first region (right portion of 21); the active layer (23) is formed in the second region.
Aoyagi does not explicitly teach the first region and the second region have an identical area.
Aoyagi teaches to adjust the parameters in A to F (paragraph [0037]) to achieve the expression of 0≤J1/J2≤0.5.
It would have been obvious to the skilled in the art before the effective filing date of the invention to adjust the area of the first region and the second region, to be identical, for example, to achieve the relative value of J1 to J2 according to the expression in paragraph [0037]: The electrical resistivity (condition A, paragraph [0037]), for example, is related to the area the first region and the second region. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Regarding claim 21, Aoyagi teaches the semiconductor light emitting device of claim 1, wherein the first conductive semiconductor layer includes a first region and a second region adjacent to the first region, and the second region is offset from the first region by a step height, wherein the active layer is disposed on the second region of the first conductive semiconductor layer (fig. 6).
Aoyagi does not explicitly teach the first region and the second region have a same area in a plan view.
Aoyagi teaches to adjust the parameters in A to F (paragraph [0037]) to achieve the expression of 0≤J1/J2≤0.5.
It would have been obvious to the skilled in the art before the effective filing date of the invention to adjust the area of the first region and the second region, to have a same area in a plan view, for example, to achieve the relative value of J1 to J2 according to the expression in paragraph [0037]: The electrical resistivity (condition A, paragraph [0037]), for example, is related to the area the first region and the second region. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Regarding claim 22, Aoyagi teaches the semiconductor light emitting device of claim 21, wherein the first metal electrode layer is disposed in the first region of the first conductive semiconductor layer, and the second metal electrode layer is disposed in the second region of the first conductive semiconductor layer (fig. 6)
Aoyagi does not explicitly teach the first metal electrode layer has a same area and a same shape as the second metal electrode layer in a plan view.
Aoyagi teaches to adjust the parameters in A to F (paragraph [0037]) to achieve the expression of 0≤J1/J2≤0.5.
It would have been obvious to the skilled in the art before the effective filing date of the invention to adjust the areas and shapes of the first metal electrode layer and of the second metal electrode layer, so that they are the same in a plan view, for example, to achieve the relative value of J1 to J2 according to the expression in paragraph [0037]: The electrical resistivity (condition A, paragraph [0037]), for example, is related to the areas/shapes of the first and second electrode layers. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Regarding claim 23, Aoyagi teaches the semiconductor light emitting device of claim 21, wherein the first metal electrode layer is disposed in the first region of the first conductive semiconductor layer, and the second metal electrode layer is disposed in the second region of the first conductive semiconductor layer, and wherein the first region including the first metal electrode layer and the second region including the second metal electrode layer (fig. 6).
Aoyagi does not explicitly teach the first region and the second region are symmetrical relative to a central axis bisecting the semiconductor light emitting device in a plan view.
Aoyagi teaches to adjust the parameters in A to F (paragraph [0037]) to achieve the expression of 0≤J1/J2≤0.5.
It would have been obvious to the skilled in the art before the effective filing date of the invention to adjust the areas/shapes and locations of the first and second regions, to have a same areas/shapes in a plan view so that they were symmetrical relative to a central axis bisecting the semiconductor light emitting device in a plan view, for example, to achieve the relative value of J1 to J2 according to the expression in paragraph [0037]: The electrical resistivity (condition A, paragraph [0037]), for example, is related to the area the first region and the second region. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Claim(s) 5 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ohno Aoyagi et al (PG Pub 2017/0358711 A1) and Ohno (PG Pub 2014/0014998 A1) as applied to claims 1 and 16 above, and further in view of Goto et al (PG Pub 2006/0097278 A1).
Regarding claim 5, the previous combination remains as applied in claim 1.
The previous combination does not teach horizontal projection areas of the first metal layer and the second metal layer are identical.
In the same field of endeavor, Goto teaches horizontal projection areas of the first electrode layer (64, fig. 4A) and the second metal layer (37) are identical (paragraph [0110]), for the benefit of improving current-to-light conversion efficiency (paragraph [0101]).
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to make horizontal projection areas of the first metal layer and the second metal layer identical for the benefit of improving current-to-light conversion efficiency.
Regarding claim 19, the previous combination remains as applied in claim 16.
The previous combination does not teach horizontal projection areas of the first metal layer and the second metal layer are identical.
In the same field of endeavor, Goto teaches horizontal projection areas of the first electrode layer (64, fig. 4A) and the second metal layer (37) are identical (paragraph [0110]), for the benefit of improving current-to-light conversion efficiency (paragraph [0101]).
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to make horizontal projection areas of the first metal layer and the second metal layer identical for the benefit of improving current-to-light conversion efficiency.
Claim(s) 8,10,11,13,15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al (PG Pub 2017/0069612 A1), Aoyagi et al (PG Pub 2017/0358711 A1), and Ohno (PG Pub 2014/0014998 A1).
Regarding claim 8, Zhang teaches a display device including a plurality of pixels (fig. 34) connected to a data line and a scan line, respectively, each of the plurality of pixels comprising: a light emitter including at least one semiconductor light emitting device (LED); and a driver supplying driving current (paragraph [0197]) to the semiconductor light emitting device.
Zhang does not explicitly teach an inverse relationship is not established between a size of the semiconductor light emitting device and current density of the drive current.
Feature “an inverse relationship is not established between a size of the semiconductor light emitting device and current density of the drive current” is an intended use of the device and Zhang device can be used as claimed by applying current proportional to size of the semiconductor light emitting device, for example. It was decided that “when the claim recites using an old composition or structure and the ‘use’ is directed to a result or property of that composition or structure, then the claim is anticipated.” In re May, 574 F.2d 1082, 1090, 197 USPQ 601, 607 (CCPA 1978). Also see MPEP 2112.02.
Zhang does not teach a semiconductor light emitting device as claimed.
In the same field of endeavor, Aoyagi teaches a semiconductor light emitting device comprising: an active layer (23, fig. 6, paragraph [0056]) disposed on a first conductive semiconductor layer (21, paragraph [0056]); a first metal electrode layer (31, Table) disposed on the first conductive semiconductor layer; a second conductive semiconductor layer (22A/22B) disposed on the active layer; a metal-semiconductor (MS) contact layer (32, Table 1) disposed on an upper surface of the second conductive semiconductor layer: wherein a contact surface between the upper surface of the second conductive semiconductor layer and the MS layer is smaller than an upper surface area of the active layer (fig. 6), for the benefit of reducing the size of the device without diminishing light emitting efficiency (paragraphs [0006][0007]).
It would have been obvious to the skilled in the art before the effective filing date of the invention to provide the semiconductor light emitting device as claimed for the benefit of reducing the size of the device without diminishing light emitting efficiency.
Aoyagi does not teach the MS contact layer is formed in ohmic contact.
Ohno teaches the MS contact layer is formed in ohmic contact (22, paragraph [0059]), for the known benefit of reducing contact resistance.
It would have been obvious to the skilled in the art before the effective filing date of the invention to form the MS contact layer in ohmic contact, for the known benefit of reducing contact resistance.
Regarding claim 10, Aoyagi teaches the display device of claim 8, wherein the second conductive semiconductor layer is formed in a mesa structure (fig. 6).
Regarding claim 11, Aoyagi does not explicitly teach the display device of claim 8, wherein current density of the driving current is in inverse proportion to a contact area between the second conductive semiconductor layer and the ohmic contact layer. It is inherent in Aoyagi device.
Regarding claim 13, Aoyagi teaches the display device of claim 9, wherein: the first conductive semiconductor layer (21, fig. 6) has a second region (right portion of 21) with a step difference in a first direction for a first region (left portion of 21); the active layer is formed in the second region.
Aoyagi does not explicitly teach the first region and the second region have an identical area.
Aoyagi teaches to adjust the parameters in A to F (paragraph [0037]) to achieve the expression of 0≤J1/J2≤0.5.
It would have been obvious to the skilled in the art before the effective filing date of the invention to adjust the area of the first region and the second region, to be identical, for example, to achieve the relative value of J1 to J2 according to the expression in paragraph [0037]: The electrical resistivity (condition A, paragraph [0037]), for example, is related to the area the first region and the second region. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Regarding claim 15, Zhang teaches (see fig. 35B) the display device of claim 8, wherein each of the plurality of pixels further includes a switching part connected to the data line and the scan line and differentiating (since Zhang device can perform differentiating activation because it is identical to Applicant’s device in fig. 16) activation of the driver.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al (PG Pub 2017/0069612 A1), Aoyagi et al (PG Pub 2017/0358711 A1), and Ohno (PG Pub 2014/0014998 A1) as applied to claim 8 above, and further in view of Goto et al (PG Pub 2006/0097278 A1).
Regarding claim 12, the previous combination remains as applied in claim 9.
The previous combination does not teach horizontal projection areas or cross-sectional areas of the first metal layer and the second metal layer are identical.
In the same field of endeavor, Goto teaches horizontal projection areas of the first electrode layer (64, fig. 4A) and the second metal layer (37) are identical (paragraph [0110]), for the benefit of improving current-to-light conversion efficiency (paragraph [0101]).
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to make horizontal projection areas of the first metal layer and the second metal layer identical for the benefit of improving current-to-light conversion efficiency.
Claim(s) 8 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al (PG Pub 2017/0069612 A1) and Ohno (PG Pub 2014/0014998 A1).
Regarding claim 8, Zhang teaches a display device including a plurality of pixels (fig. 34) connected to a data line and a scan line, respectively, each of the plurality of pixels comprising: a light emitter including at least one semiconductor light emitting device (LED); and a driver supplying driving current (paragraph [0197]) to the semiconductor light emitting device.
Zhang does not explicitly teach an inverse relationship is not established between a size of the semiconductor light emitting device and current density of the drive current.
Feature “an inverse relationship is not established between a size of the semiconductor light emitting device and current density of the drive current” is an intended use of the device and Zhang device can be used as claimed by applying current proportional to size of the semiconductor light emitting device, for example. It was decided that “when the claim recites using an old composition or structure and the ‘use’ is directed to a result or property of that composition or structure, then the claim is anticipated.” In re May, 574 F.2d 1082, 1090, 197 USPQ 601, 607 (CCPA 1978). Also see MPEP 2112.02.
Zhang does not teach a semiconductor light emitting device as claimed.
In the same field of endeavor, Ohno teaches a semiconductor light emitting device comprising: an active layer (13, fig. 7, paragraph [0053]) disposed on a first conductive semiconductor layer (10, paragraph [0067]); a first metal electrode layer (24, paragraph [0085]) disposed on (on the bottom of) the first conductive semiconductor layer; a second conductive semiconductor layer (20X) disposed on the active layer; an ohmic contact layer (22, paragraph [0059]) disposed on an upper surface of the second conductive semiconductor layer: wherein a contact surface between the upper surface of the second conductive semiconductor layer and the ohmic contact layer is smaller than an upper surface area of the active layer (fig. 6), for the benefit of providing a high-efficient light emitting device (paragraph [0163]).
It would have been obvious to the skilled in the art before the effective filing date of the invention to provide the semiconductor light emitting device as claimed for the benefit of providing a high-efficient light emitting device.
Regarding claim 14, Ohno teaches the display device of claim 9, wherein the first metal layer and the second metal layer are disposed to face each other in a second direction (fig. 7).
Response to Arguments
Applicant's arguments filed December 19, 2025 have been fully considered but they are not persuasive. Applicant argues that prior art does not teach the amended features (pages 8-11, remarks). Examiner disagrees. See rejection above.
Applicant also argues that the ITO layer in prior art does not read on the claimed “metal-semiconductor (MS) contact layer” because ITO is not metal. Page 11, third paragraph. Examiner disagrees because Applicant discloses that the “metal-semiconductor (MS) contact layer” can be ITO (paragraph [0143]) of Applicant’s PG Pub 2023/0395768 A1).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FEIFEI YEUNG LOPEZ whose telephone number is (571)270-1882. The examiner can normally be reached M-F: 8am to 4pm EST.
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/FEIFEI YEUNG LOPEZ/Primary Examiner, Art Unit 2899