DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This action is responsive to the following communication: Original claims filed 04/21/23. This action is made non-final.
3. Claims 1-11 and 18-26 are pending in the case. Claims 1, 23 and 24 are independent claims.
Claim Objections
4. Claims 6-7, 18-22 and 25-26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 112b
5. Claim 1 states “wherein the quantum processor is controlled by a first method of error correction on each of the patches connected by the bus to reduce a relatively high error rate in the digital qubits to a relatively low error rate of each patch, and by a second method of error correction on the multiple patches to correct the relatively low error rate”.
Here, “a relatively high error rate” and a “relatively low error rate” recites relative terms of degree and therefore it is unclear as to the metes and bounds of what is a “relatively high error rate” and what is a “relatively low error rate”.
Accordingly, a 112b rejection is been made for claim 1. Claims 2-11 and 18-22 further comprise this deficiency from claim 1 and do not remedy the 112b issue. While claim 26 further defines "the relatively low error rate" it does not further clarify "the relatively high error rate".
Regarding claims 23 and 24, claims 23 and 24 also recite “a relatively high error rate" and “a relatively low error rate" and is therefore rejected under a similar rationale. Claim 25 is dependent on claim 24 and further comprises the deficiency of claim 24 and do not remedy the 112b issue.
Claim Rejections - 35 USC § 102
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
7. Claims 1-5, 8-11, 23 and 24 are rejected under 35 U.S.C. 102(a)(1) as being rejected by anticipated by Zeng (US Patent No. US 10,352,992).
Regarding Claim 1, Zeng discloses wherein a quantum processor (quantum processor cell 204 [Col 7 Lines 55-65][Fig 2A]) comprising:
multiple patches of digital qubits (Qubit devices 214A, 214B, 214C, 214 D which act as data qubits [Col 7 Lines 60-65][Fig2A]); and
a quantum bus of digital qubits, configured to connect the multiple patches of digital qubits and to transmit quantum information constituting long-range interactions between the patches of digital qubits (Coupler devices 212A, 212B, 212C, 214 D which act as ancilla qubits [Col 7 Lines 60-65][Fig2A] The Qubit devices can interact with each other through the coupler devices [Col 5 Line 66- Col 6 Line 6]),
wherein the quantum processor is controlled by a first method of error correction on each of the patches connected by the bus to reduce a relatively high error rate in the digital qubits to a relatively low error rate of each patch (“In some aspects of operation, the control system 202 generates control signals 206 and sends the control signals to the quantum processor cell 204; the control signals are then delivered to the quantum processor cell 204 and cause the quantum processor cell 204 to execute the quantum error-correction scheme” [Col 8 Lines 5-9] The quantum error-correction scheme applied by the control system 202 can be a surface code or a color code (i.e. a first method of error correction to reduce a relatively high error rate to a relatively low error rate) [Col 8 Lines 10-15][Col 8 Lines 32-35]),
and by a second method of error correction on the multiple patches to correct the relatively low error rate (“In some examples, aspects of the quantum error-correction scheme are executed by the control system 202 applying a first set of two-qubit gates (e.g., a first set of CNOT gates) to qubits in a lattice cell in the device lattice, and then applying a second, different set of two-qubit gates (e.g., a second set of CNOT gates) to the same qubits in the lattice cell. After applying the first and second sets of two-qubit gates, the control system 202 can obtain measurement outcomes of the ancilla qubits in the lattice cell, and determine a parity of the measurement outcomes…For instance, the parity of the measurement outcomes can be used to detect and correct errors in the data qubits in a color code or surface code applied to the lattice.” [Col 9 Lines 9-28]) ) (i.e. performing a second method of error correction to correct errors in a color code or surface code (the first method of error correction).
Regarding claim 3, Zeng discloses wherein the multiple patches form multiple arrays of more than one patch each connected by the quantum bus (see FIG. 2A wherein the devices are arranged to form another type of ordered array).
Regarding claim 4, Zeng discloses wherein the multiple arrays are linear arrays (see FIG. 3 wherein an array of lattice cells, wherein each lattice cell includes a group of devices that includes cells extending in two spatial dimensions).
Regarding claim 5, Zeng discloses wherein each linear array has an identical width (see FIG. 3 wherein an array of lattice cells, wherein each lattice cell includes a group of devices that includes cells extending in two spatial dimensions).
Regarding claim 8, Zeng discloses further comprising an area between the multiple patches comprising connections to the digital qubits of the multiple patches (see FIG. 1 wherein coupler devices and control signals can utilize multiple qubits).
Regarding claim 9, Zeng discloses wherein the digital qubits of the bus are controlled by the first method of error correction (In some aspects of operation, the quantum error-correction scheme applied by the control system 202 is a surface code. For instance, the control system 202 may apply a two-dimensional or three-dimensional surface code to qubits in the device lattice. The two-dimensional surface code can be considered a stabilizer code on a three-valent, three-colorable lattice, where data qubits operate at the edges of a surface code lattice. The three-dimensional surface code can be considered a stabilizer code on a four-valent, four-colorable lattice, where data qubits operate at the edges of a surface code lattice. The stabilizers of the code can be implemented as parity measurements on faces and vertices of the surface code lattice. For instance, the face operators can measure the X-parity of the qubits around a face in the lattice cell, and the vertex operators can measure the Z-parity of the qubits incident on a single vertex of the lattice cell. The syndrome measurements of the code can be performed by measuring the stabilizers (e.g., X-stabilizers and Z-stabilizers) across the surface code lattice, and the stabilizer measurements can be decoded using classical decoding algorithms, see column 7).
Regarding claim 10, Zeng discloses wherein the first method of error correction comprises a surface code (In some aspects of operation, the quantum error-correction scheme applied by the control system 202 is a surface code. For instance, the control system 202 may apply a two-dimensional or three-dimensional surface code to qubits in the device lattice. The two-dimensional surface code can be considered a stabilizer code on a three-valent, three-colorable lattice, where data qubits operate at the edges of a surface code lattice. The three-dimensional surface code can be considered a stabilizer code on a four-valent, four-colorable lattice, where data qubits operate at the edges of a surface code lattice. The stabilizers of the code can be implemented as parity measurements on faces and vertices of the surface code lattice. For instance, the face operators can measure the X-parity of the qubits around a face in the lattice cell, and the vertex operators can measure the Z-parity of the qubits incident on a single vertex of the lattice cell. The syndrome measurements of the code can be performed by measuring the stabilizers (e.g., X-stabilizers and Z-stabilizers) across the surface code lattice, and the stabilizer measurements can be decoded using classical decoding algorithms, see column 7).
Regarding claim 11, Zeng discloses wherein the second method of error correction comprises a block code (In some aspects of operation, the quantum error-correction scheme applied by the control system 202 is a color code. For instance, the control system 202 may apply a two-dimensional or three-dimensional color code to qubits in the device lattice. The two-dimensional color code can be considered a stabilizer code on a three-valent, three-colorable lattice, where data qubits operate at the vertices of a color code lattice. The three-dimensional color code can be considered a stabilizer code on a four-valent, four-colorable lattice, where data qubits operate at the vertices of a color code lattice. The stabilizers of the code can be implemented as parity measurements on faces of the color code lattice. The syndrome measurements of the code can be performed by measuring the stabilizers (e.g., X-stabilizers and Z-stabilizers) across the color code lattice, and the stabilizer measurements can be decoded using classical decoding algorithms, see column 7).
Regarding claim 23, Zeng discloses a method for operating a quantum processor (quantum processor cell 204 [Col 7 Lines 55-65][Fig 2A]), the quantum processor comprising
multiple patches of digital qubits (Qubit devices 214A, 214B, 214C, 214 D which act as data qubits [Col 7 Lines 60-65][Fig2A]) and
a quantum bus of digital qubits, configured to connect the multiple patches of digital qubits and to transmit quantum information constituting long-range interactions between the patches of digital qubits (Coupler devices 212A, 212B, 212C, 214 D which act as ancilla qubits [Col 7 Lines 60-65][Fig2A] The Qubit devices can interact with each other through the coupler devices [Col 5 Line 66- Col 6 Line 6]), the method comprising:
applying a first method of error correction to each of the patches connected by the bus to reduce a relatively high error rate in the digital qubits to a relatively low error rate of each patch (“In some aspects of operation, the control system 202 generates control signals 206 and sends the control signals to the quantum processor cell 204; the control signals are then delivered to the quantum processor cell 204 and cause the quantum processor cell 204 to execute the quantum error-correction scheme” [Col 8 Lines 5-9] The quantum error-correction scheme applied by the control system 202 can be a surface code or a color code (i.e. a first method of error correction to reduce a relatively high error rate to a relatively low error rate) [Col 8 Lines 10-15][Col 8 Lines 32-35]),; and
applying a second method of error correction to the multiple patches to correct the relatively low error rate (“In some examples, aspects of the quantum error-correction scheme are executed by the control system 202 applying a first set of two-qubit gates (e.g., a first set of CNOT gates) to qubits in a lattice cell in the device lattice, and then applying a second, different set of two-qubit gates (e.g., a second set of CNOT gates) to the same qubits in the lattice cell. After applying the first and second sets of two-qubit gates, the control system 202 can obtain measurement outcomes of the ancilla qubits in the lattice cell, and determine a parity of the measurement outcomes…For instance, the parity of the measurement outcomes can be used to detect and correct errors in the data qubits in a color code or surface code applied to the lattice.” [Col 9 Lines 9-28]) ) (i.e. performing a second method of error correction to correct errors in a color code or surface code (the first method of error correction).
Regarding claim 24, Zeng discloses a method for manufacturing a quantum processor quantum processor cell 204 [Col 7 Lines 55-65][Fig 2A]), the method comprising:
creating multiple patches of digital qubits to form a first array of a number of patches (Qubit devices 214A, 214B, 214C, 214 D which act as data qubits [Col 7 Lines 60-65][Fig2A]);
connecting the multiple patches of the first array by a quantum bus of digital qubits, configured to connect the multiple patches of digital qubits and to transmit quantum information constituting long-range interactions between the patches of digital qubits (Coupler devices 212A, 212B, 212C, 214 D which act as ancilla qubits [Col 7 Lines 60-65][Fig2A] The Qubit devices can interact with each other through the coupler devices [Col 5 Line 66- Col 6 Line 6]);
creating multiple further arrays having an identical number of patches as the first array; connecting the multiple further arrays to the first array by the quantum bus (see FIG. 3 wherein an array of lattice cells, wherein each lattice cell includes a group of devices that includes cells extending in two spatial dimensions);
creating control circuitry to control the quantum processor by a first method of error correction on each of the patches connected by the bus to reduce a relatively high error rate in the digital qubits to a relatively low error rate of each patch (“In some aspects of operation, the control system 202 generates control signals 206 and sends the control signals to the quantum processor cell 204; the control signals are then delivered to the quantum processor cell 204 and cause the quantum processor cell 204 to execute the quantum error-correction scheme” [Col 8 Lines 5-9] The quantum error-correction scheme applied by the control system 202 can be a surface code or a color code (i.e. a first method of error correction to reduce a relatively high error rate to a relatively low error rate) [Col 8 Lines 10-15][Col 8 Lines 32-35]), and
by a second method of error correction on the multiple patches to correct the relatively low error rate (“In some examples, aspects of the quantum error-correction scheme are executed by the control system 202 applying a first set of two-qubit gates (e.g., a first set of CNOT gates) to qubits in a lattice cell in the device lattice, and then applying a second, different set of two-qubit gates (e.g., a second set of CNOT gates) to the same qubits in the lattice cell. After applying the first and second sets of two-qubit gates, the control system 202 can obtain measurement outcomes of the ancilla qubits in the lattice cell, and determine a parity of the measurement outcomes…For instance, the parity of the measurement outcomes can be used to detect and correct errors in the data qubits in a color code or surface code applied to the lattice.” [Col 9 Lines 9-28]) ) (i.e. performing a second method of error correction to correct errors in a color code or surface code (the first method of error correction).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID E CHOI whose telephone number is (571)270-3780. The examiner can normally be reached on M-F: 7-2, 7-10 (PST). If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bechtold, Michelle T. can be reached on (571) 431-0762. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DAVID E CHOI/Primary Examiner, Art Unit 2148