DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 and 6-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fortusini et al. (US 10564354 B2).
Re claim 1, Fortusini et al. discloses an optical circuit board (fig. 2B) comprising: a wiring board (124; col. 8, lines 62-64); and an optical waveguide (70), wherein the wiring board has comprises a first region (front end 36) on which a silicon photonics device (OE-IC 210 includes both photonic and electronic components) is to be mounted (via 90B, 99, 90T, 262 and 132), a second region (back end 38), a cavity (32) interposed between the first region (36) and the second region (38), and a first conductor layer (90) in the second region, the first region and the second region are located on a surface of the wiring board (124), the optical waveguide (70) is located on the first conductor layer (90) in the second region and comprises a cladding and a core surrounded by the cladding (col. 12, lines 53-67), and the first conductor layer (90) comprises a portion (60) protruding toward the first region (36) above the cavity (32).
Re claim 2, Fortusini et al. discloses the optical circuit board according to claim 1, wherein the wiring board comprises an insulating layer containing a plurality of particles of inorganic filler (air) and the plurality of particles of the inorganic filler are exposed from an inner surface of the cavity (fig. 2B; col. 12, lines 38-39).
Re claim 6, Fortusini et al. discloses a method of manufacturing the optical circuit board according to claim 1, the method comprising: forming the cavity (32) in the wiring board (124) using an excimer laser (col. 5, lines 53-58).
Re claim 7, Fortusini et al. discloses an electronic component mounting structure comprising: the optical circuit board described in claim 1; the silicon photonics device (210); and an electronic component (2nd 210; fig. 3A), wherein the silicon photonics device comprises a silicon waveguide (250) and is electrically connected (via 90B, 99, 90T, 262 and 132) to the optical circuit board in the first region (36), and the silicon waveguide faces the core of the optical waveguide (fig. 2B; col. 9, lines 46-50).
Re claim 8, Fortusini et al. discloses the optical circuit board according to claim 1, wherein the cavity (32) is recessed toward the second region (fig. 2B).
Re claim 9, Fortusini et al. discloses the optical circuit board according to claim 1, wherein the first conductor layer (90) is inclined toward a bottom portion of the cavity above the cavity (32; fig. 2B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fortusini et al.
Re claim 3, Fortusini et al. discloses the optical circuit board according to claim 2, but fails to teach wherein 20 or more of the plurality of particles of the inorganic filler having a particle size of from 0.1 µm to 1 µm per 5 µm2 are exposed at the inner surface of the cavity.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the cavity of Fortusini et al. filled as the claimed range since such modification would have been an obvious design variation, well within the ordinary skill in the art, since it has been held that the selection of a known material based on its suitability for its intended use to control the optical properties of the insulating layer of the wiring board. In re Leshin, 125 USPQ 146.
Re claim 4, Fortusini et al. discloses the optical circuit board according to claim 3, wherein the plurality of particles of the inorganic filler (air) are exposed from a wall surface of the cavity (fig. 2B).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fortusini et al. in view of Takahashi et al. (DE 69733115 T2).
Re claim 5, Fortusini et al. discloses the optical circuit board according to claim 1, but fails to teach the wiring board comprises a second conductor layer at a bottom portion of the cavity.
However, having a second conductor layer (102, 103) at a bottom portion of the cavity (109) is well-known in the art as evidenced by Takahashi et al. (fig. 1A-B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a conductor layer at a bottom portion of Fortusini et al.’s cavity since such modification would have been an obvious design variation, well within the ordinary skill in the art, for an intended use to provide an electromagnetic shield.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kitaoka et al. (US 6327289 B1) discloses a submount having a cavity interposed between an optical waveguide and a laser (fig. 4B).
Brusberg et al. (US 20210271037 A1) discloses an optical-electrical substrate having a cavity interposed between an optical waveguide and a laser (fig. 18).
白土 洋次 (JP 5444975 B2) discloses an opto-electric hybrid board having a cavity interposed between an optical waveguide and a laser, and a conductive layer protrudes above the cavity (fig. 7).
Hochberg et al. (US 10598876 B2) discloses a fiber support having a cavity interposed between an optical waveguide and a PIC, wherein the end surface of the PIC waveguide faces the end surface of the optical waveguide (fig. 3).
Choi (US 11852877 B2) discloses a waveguide disposed on a conductive layer (fig. 7).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Uyen-Chau N. Le whose telephone number is (571)272-2397. The examiner can normally be reached Monday-Friday, 9:00am-5:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kiesha R. Bryant can be reached at (571) 272-3606. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/UYEN CHAU N LE/ Supervisory Patent Examiner, Art Unit 2874
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