Prosecution Insights
Last updated: April 19, 2026
Application No. 18/033,745

SIGNAL PROCESSING DEVICE, SIGNAL PROCESSING METHOD, AND IMAGING APPARATUS

Non-Final OA §102§103
Filed
Apr 25, 2023
Examiner
BORROMEO, JUANITO C
Art Unit
2184
Tech Center
2100 — Computer Architecture & Software
Assignee
Sony Semiconductor Solutions Corporation
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
3y 1m
To Grant
89%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allow Rate
460 granted / 608 resolved
+20.7% vs TC avg
Moderate +13% lift
Without
With
+13.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
33 currently pending
Career history
641
Total Applications
across all art units

Statute-Specific Performance

§101
3.9%
-36.1% vs TC avg
§103
53.4%
+13.4% vs TC avg
§102
34.0%
-6.0% vs TC avg
§112
5.3%
-34.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 608 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 2, 4 and 10 – 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ouyang et al. (US Pub. No. 20190130533), hereinafter referred to as Ouyang. As to claim 1, Ouyang discloses a signal processing device (image processing apparatus / mobile terminal, 1000, Fig. 6) comprising: multiple input units (primary camera and secondary camera, 1112 / 1113, Fig. 6) that add additional information necessary for signal processing (ISO sensitivity, ambient light brightness, depth disparity used as processing control information, 302–304 / 309, Fig. 3A) to each of multiple pieces of data inputted from respective multiple external devices (images captured from dual camera sensors, 1112 / 1113, Fig. 6), and output the multiple pieces of data (image data output to ISP pipeline, 940, Fig. 7); and multiple stages of processing units (acquiring module, denoising module, calculating module, processing module, 41–44, Fig. 4) each configured to perform common signal processing (shared denoising, depth calculation, and blurring operations applied across image streams, 42–44, Fig. 4) on a basis of the additional information (processing controlled based on ISO, depth information, and ambient light parameters, 302–304 / 309–310, Fig. 3A). As to claim 2, Ouyang discloses the signal processing device of claim 1, wherein the additional information includes instruction information indicating an instruction (processing control information directing ISP operation flow, 950, Fig. 7) as to signal processing using which processing unit, out of the multiple stages of processing units (selection and control of ISP processing modules, 940 / 41–44, Fig. 7; Fig. 4), is to be performed on each of the multiple pieces of data (processing flow control between ISP modules based on control parameters, logic controller 950 directing ISP operations, Fig. 7) and setting information indicating a setting value to be used for signal processing in each of the multiple stages of processing units (ISO sensitivity, ambient light brightness, depth parameters used as processing settings, 302–304 / 309–310, Fig. 3A; ISP control parameters, Fig. 7). As to claim 4, Ouyang discloses the signal processing device of claim 1, further comprising a controller (logic controller, 950, Fig. 7) that instructs each of the multiple input units as to signal processing using which processing unit, out of the multiple stages of processing units, is to be performed (controller directing image equipment and ISP processing operations, 950 controlling ISP processor 940, Fig. 7). Claims 10 and 11 recite the corresponding limitation of claim 1. Therefore, they are rejected accordingly. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Ouyang et al. (US Pub. No. 20190130533), hereinafter referred to as Ouyang in view of Walden et al. (US Pat. No. 8595352), hereinafter referred to as Walden. As to claim 3, Walden discloses, what Ouyang lacks, the signal processing device of claim 1, wherein the additional information includes information indicating a priority (fabric service uses priority information to control processing order of frames, Fig. 4B; e.g. routing attributes that determines routes, col. 7, lines 1 - 15) for signal processing of each of the multiple pieces of data in each of the multiple stages of processing units (service module attributes and negotiated capabilities determining handling precedence within fabric services, ESC frame attributes, 306/308, Fig. 3). Ouyang and Walden are analogous art because they are from the same field of endeavor, namely multi-stage signal processing systems that process multiple data streams using control information to manage processing behavior. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Ouyang and Walden before him or her, to modify the multi-stage image signal processing pipeline of Ouyang to include the packet-based data formatting with header-carried control and priority information of Walden. The suggestion and motivation for doing so would have been to enable more efficient and flexible control of processing across multiple stages and multiple data streams by embedding processing-relevant information (including priority) directly with the data being processed. Therefore, it would have been obvious to combine Walden with Ouyang to obtain the invention as specified in the instant claim. As to claim 5, Walden discloses, what Ouyang lacks, the signal processing device of claim 1, wherein the multiple input units each include a first packet generator that generates a packet of each of the multiple pieces of data (Fibre Channel frames exchanged between switch and intelligent service module, ELP / ESC frames, 302/306, Fig. 3), adds the additional information as a header to the packet (frame headers carrying link parameters, attributes, and service module information, ELP / ESC frame fields, Fig. 3), and outputs the packet (transmission of frames between director-level switch and intelligent service module over fabric links, 210/302/306, Fig. 2; Fig. 3). Allowable Subject Matter Claims 6 – 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Davila et al. (US Pat. No. 11307900) discloses plurality of CPU for task processing. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUANITO C BORROMEO whose telephone number is (571)270-1720. The examiner can normally be reached on Monday - Friday 9 - 5. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached on 5712724176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /J.C.B/ Assistant Examiner, Art Unit 2184 /HENRY TSAI/ Supervisory Patent Examiner, Art Unit 2184
Read full office action

Prosecution Timeline

Apr 25, 2023
Application Filed
Dec 18, 2025
Non-Final Rejection — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12591534
APPARATUSES, COMPUTER-IMPLEMENTED METHODS, AND COMPUTER PROGRAM PRODUCTS FOR CONNECTED DEVICE CONTROL AND USE
2y 5m to grant Granted Mar 31, 2026
Patent 12585613
DETECTION OF AN ERROR CONDITION ON A SERIAL DATA BUS
2y 5m to grant Granted Mar 24, 2026
Patent 12579091
SECURE DUAL FUNCTION USB CONNECTOR
2y 5m to grant Granted Mar 17, 2026
Patent 12572488
UNIVERSAL SERIAL BUS REPEATER WITH IMPROVED REMOTE WAKE CAPABILITY
2y 5m to grant Granted Mar 10, 2026
Patent 12572481
INTELLIGENTLY MANAGING SPOOL DATA SETS
2y 5m to grant Granted Mar 10, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
89%
With Interview (+13.0%)
3y 1m
Median Time to Grant
Low
PTA Risk
Based on 608 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month