DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
2. Claims 1 and 3-20 have been examined. Claims 1, 3-17, 19, and 20 are rejected. Claim 18 is objected to. This Office action is responsive to the amendment filed on April 10, 2026, which has been entered in the above identified application.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1, 3, 5, 6, 8, 9, 11, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hashiguchi et al (Pub. No. US 2016/0139580), in view of Kobayashi et al (Pub. No. US 2017/0246741), and further in view of Wu et al (Pub. No. US 2014/0208093).
4-1. Regarding claim 1, Hashiguchi teaches the claim comprising: processing circuitry including an input terminal to receive an input signal, including an output terminal to output a signal, by disclosing a process control system 1 that includes an I/O module 12 [paragraph 48] having a lower-level layer interface 21 that includes I/O ports P connected to field devices 11 and that transmits and receives a variety of signals to and from the field device 11 connected to the I/O ports P [paragraph 57]. Process values measured by a sensor device 11a may be acquired and operation may be transmitted to a valve device 11b [paragraph 52].
Hashiguchi teaches processing circuitry to receive first setting information from a host controller, the first setting information being information for setting a condition of a value of the signal to be output from the output terminal or a condition between a value of the input signal received by the input terminal and a value of the signal to be output from the output terminal and being information for controlling an operation of an external device connected to the input-output module, by disclosing that engineering terminal 15 generates information to be set to the field device 11, the I/O module 12, and the controller 13, based on process design information, which is design information of the process control system 1, and such information generated by the engineering terminal 15 includes information relating to input and output between the field device 11 and the I/O module 12 [paragraph 54].
Hashiguchi teaches processing circuitry to receive second setting information, the second setting information being information for setting the condition of the value of the signal to be output from the output terminal or the condition between the value of the input signal received by the input terminal and the value of the signal to be output from the output terminal and being information for controlling an operation of an external device connected to the input-output module, by disclosing a maintenance port 23 that transmits and receives various signals to and from the setting apparatus 16 [paragraph 58, lines 4-6]. The setting apparatus 16 and maintenance port 23 provide various settings for the field device 11 and the I/O module 12 [paragraph 80, lines 6-10; paragraph 82, lines 3-6].
Hashiguchi does not expressly teach processing circuity to store the received first setting information or the received second setting information, to, based on the stored first setting information or the stored second setting information cause the output terminal to output a signal with the set value or cause the output terminal to output a signal with a value in accordance with the set condition and the value of the input signal received by the input terminal. Kobayashi discloses that it was well known to store setting information in a memory of a command executor of a slave device [paragraphs 84, 113]. This would allow such setting information to be accessed more quickly. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to store received setting information, as taught by Kobayashi. This would allow such setting information to be accessed more quickly.
Hahiguchi-Kobayashi do not expressly teach processing circuitry to store a startup determination flag corresponding to a startup determination mode in a flag storage, wherein the startup determination flag is set on when the startup determination mode is in a startup mode and the startup determination flag is set off when the startup determination mode is in a non-startup mode. Wu discloses a buffer unit within a control module of an electronic device that stores a flag, used to control a booting procedure, according to content of a first signal S1 received in response to a press of a button unit [paragraphs 17, 31]. When the electronic device boots, a BIOS reads the states (the flag) recorded in the buffer unit, loads the corresponding parameters to the electronic component in the electronic device, and causes the electronic device to boot [paragraphs 20, 34]. This would allow a user to easily switch between different booting procedures without physically altering the device’s main storage. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide, in the control device of Hashiguchi-Kobayashi, a buffer unit that stores a flag used to determine a bootup configuration, as taught by Wu. This would allow a user to easily switch between different booting procedures without physically altering the device’s main storage.
Hashiguchi-Kobayashi-Wu teach processing circuitry to switch a startup determination mode between a startup mode and a non-startup mode, wherein when the startup determination mode is in the non-startup mode and the startup determination flag stored in the flag storage is off, the processing circuitry, based on the first setting information, causes the output terminal to output the signal with the set value or causes the output terminal to output the signal with the value in accordance with the set condition and the value of the input signal received by the input terminal, and when the startup determination mode is in the startup mode and the startup determination flag stored in the flag storage is on, the processing circuitry receives the second setting information from a device other than the host controller, and, based on the second setting information, causes the output terminal to output the signal with the set value or causes the output terminal to output the signal with the value in accordance with the set condition and the value of the input signal received by the input terminal, by disclosing that under a control of control device 26, switch 24 switches between connecting the higher-level layer interface 22 to the lower-level layer interface 21 (online state) and connecting the maintenance port 23 to the lower-level layer interface 21 (maintenance state) [Hashiguchi, paragraph 59]. The online state may be considered the non-startup mode in the claim since the lower-level layer interface is connected to the high-level layer interface, which, if there is a connection to controller 13, will allow setting information to be received from controller 13. The maintenance state may be considered the startup mode in the claim since the lower-level layer interface is connected to the maintenance port, which is connected to setting apparatus for receiving setting information. During the initial launch stage of the process control system 1, the I/O module 12 and the controller 13 are not connected [Hashiguchi, paragraph 80, lines 1-6] and the I/O module 12 transitions from the online state ST11 (i.e. the claimed non-startup mode) to the maintenance state 12 (i.e. the claimed startup mode) so that setting apparatus 16 is connected to maintenance port 23 to perform various settings on the field device 11 and the I/O module 12 [Hashiguchi, paragraph 80, lines 6-10; paragraph 81; paragraph 82, lines 1-6]. This initial configuration is considered to be in a startup mode performing startup operations since the I/O module is being installed at a site, and is in the initial launch stage without being connected to controller 13. As discussed above, the combination of Hashiguchi-Kabayashi-Wu disclose using a stored flag in a buffer unit of the control device to determine which booting procedure to load [Wu, paragraphs 17, 20, 31, 34].
4-2. Regarding claim 3, Hashiguchi-Kabayashi-Wu teach all the limitations of claim 1, wherein when the startup determination mode is in the startup mode and the processing circuitry receives the first setting information from the host controller, the startup determination mode is switched from the startup mode to the non-startup mode, by disclosing that the I/O module may transition from the maintenance state to the online state [Hashiguchi, paragraph 74, lines 5-10; paragraph 77].
4-3. Regarding claims 5 and 9, Hashiguchi-Kabayashi-Wu teach all the limitations of claims 1 and 3 respectively, wherein the processing circuitry connects a terminal device to receive the second setting information, by disclosing that I/O module is connected to setting apparatus 16 which provides setting information [Hashiguchi, paragraph 58, lines 4-6; paragraph 80, lines 6-10; paragraph 82, lines 3-6].
4-4. Regarding claims 6 and 11, Hashiguchi-Kabayashi-Wu teach all the limitations of claims 1 and 3 respectively, wherein the processing circuitry receives the second setting information being input, by disclosing that an operator operates the setting apparatus 16 to perform various settings, adjustments, etc., on the field device 11 and the I/O module 12 [Hashiguchi, paragraph 82, lines 3-6].
4-5. Regarding claim 8, Hashiguchi-Kabayashi-Wu teach all the limitations of claim 1, wherein the processing circuitry causes the output terminal to output the signal based on the second setting information before the input-output module is connected to the host controller, by disclosing that during the initial launch stage of the process control system 1, the I/O module 12 and the controller 13 are not connected [Hashiguchi, paragraph 80, lines 1-6] and the setting apparatus 16 is connected to maintenance port 23 to perform various settings on the field device 11 and the I/O module 12 [Hashiguchi, paragraph 80, lines 6-10; paragraph 81; paragraph 82, lines 1-6].
4-6. Regarding claim 20, Hashiguchi-Kobayashi-Wu teach all the limitations of claim 1, wherein the processing circuitry causes an external device connected to the input-output module to operate based on the second setting information before the input-output module is connected to the host controller, by disclosing that the setting apparatus 16 and maintenance port 23 provide various settings for the field device 11 and the I/O module 12 [Hashiguchi, paragraph 80, lines 6-10; paragraph 82, lines 3-6].
5. Claims 4, 10, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Hashiguchi et al (Pub. No. US 2016/0139580), in view of Kobayashi et al (Pub. No. US 2017/0246741), in view of Wu et al (Pub. No. US 2014/0208093), and further in view of Iriguchi et al (U.S. Patent No. 11,435,716).
5-1. Regarding claim 4, Hashiguchi-Kobayashi-Wu teach all the limitations of claim 3. Hashiguchi-Kobayashi-Wu do not expressly teach wherein when the second setting information is stored in the processing circuitry and the processing circuitry receives the first setting information from the host controller, the second setting information stored in the processing circuitry is overwritten with the first setting information. Iriguchi discloses that it was well known to overwrite stored configuration information with updated configuration information [column 6, lines 5-10]. This would save storage space. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to overwrite stored setting information, as taught by Iriguchi. This would save storage space.
5-2. Regarding claim 10, Hashiguchi-Kobayashi-Wu-Iriguchi teach all the limitations of claim 4, wherein the processing circuitry connects a terminal device to receive the second setting information, by disclosing that I/O module is connected to setting apparatus 16 which provides setting information [Hashiguchi, paragraph 58, lines 4-6; paragraph 80, lines 6-10; paragraph 82, lines 3-6].
5-3. Regarding claim 12, Hashiguchi-Kobayashi-Wu-Iriguchi teach all the limitations of claim 4, wherein the processing circuitry receives the second setting information being input, by disclosing that an operator operates the setting apparatus 16 to perform various settings, adjustments, etc., on the field device 11 and the I/O module 12 [Hashiguchi, paragraph 82, lines 3-6].
6. Claims 7, 13, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Hashiguchi et al (Pub. No. US 2016/0139580), in view of Kobayashi et al (Pub. No. US 2017/0246741), in view of Wu et al (Pub. No. US 2014/0208093), in view of Jinzenji et al (U.S. Patent No. 7,505,875), and further in view of Walker et al (U.S. Patent No. 10,082,782).
6-1. Regarding claims 7, 13, 15, and 16, Hashiguchi-Kabayashi-Wu teach a control system, comprising, the input-output module according to claims 1, 3, 5, and 6 respectively, by disclosing process control system 1 [Hashiguchi, paragraph 48; figure 1].
Hashiguchi-Kabayashi-Wu do not expressly teach a display connectable to the input-output module, the display being configured to display an input state of the input terminal as ON or OFF, an output state of the output terminal as ON or OFF, a bit value corresponding to the input state, a bit value corresponding to the output state. Jinzenji discloses a system for collecting a plurality of control data from a programmable controller (PLC) memory and outputting these collected data to a monitor device such as an image display, and causing these control data to be displayed sequentially in time and monitored by the monitor device [column 1, lines 10-16]. An I/O unit of a PLC is connected to a plurality of input and output apparatus and is provided with a memory for storing data corresponding to each of these apparatus, serving to periodically accept input data (inclusive of bit variable data which are on-off data and analog variable data which are numerical data) from an external sensor and to store them [column 6, lines 7-13]. Such data is stored in a data collecting unit of the PLC [column 6, lines 29-51]. A monitoring screen displays a bit variable waveform display area 110 and a bit variable data display area 130 for displaying the states of signals comprising an on or off condition [column 7, lines 14-21; column 10, lines 31-67; figure 9]. A bit value of 1 or 0 indicates whether the signal is on or off [column 7, lines 57-60] and thus, the bit variable waveform indicates the bit value corresponding to an input and output state. This would allow a technician to more easily verify operation of the system. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to display a monitoring screen comprising a bit variable waveform display area and a bit variable data display area, as taught by Jinzenji. This would allow a technician to more easily verify operation of the system.
Hashiguchi-Kabayashi-Wu-Jinzenji do not expressly teach display a hexadecimal numerical value representing the bit values. Walker discloses providing a display interface for a PLC that displays various conditions of the PLC [column 4, lines 21-35]. A menu within the interface allows a user to switch display of units to hexadecimal [column 5, lines 38-45, 56-58]. This would allow a user to more quickly monitor state changes of an I/O module with a plurality of inputs and outputs. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a menu that allows the user to display the bit values of Hashiguchi-Kabayashi-Wu-Jinzenji as a hexadecimal numerical value, as taught by Walker. This would allow a user to more quickly monitor state changes of an I/O module with a plurality of inputs and outputs.
7. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Hashiguchi et al (Pub. No. US 2016/0139580), in view of Kobayashi et al (Pub. No. US 2017/0246741), in view of Wu et al (Pub. No. US 2014/0208093), in view of Iriguchi et al (U.S. Patent No. 11,435,716), in view of Jinzenji et al (U.S. Patent No. 7,505,875), and further in view of Walker et al (U.S. Patent No. 10,082,782).
7-1. Regarding claim 14, Hashiguchi-Kobayashi-Wu-Iriguchi teach a control system, comprising: the input-output module according to claim 4, by disclosing process control system 1 [Hashiguchi, paragraph 48; figure 1].
Hashiguchi-Kobayashi-Wu-Iriguchi do not expressly teach a display connectable to the input-output module, the display being configured to display an input state of the input terminal as ON or OFF. an output state of the output terminal as ON or OFF, a bit value corresponding to the input state, a bit value corresponding to the output state. Jinzenji discloses a system for collecting a plurality of control data from a programmable controller (PLC) memory and outputting these collected data to a monitor device such as an image display, and causing these control data to be displayed sequentially in time and monitored by the monitor device [column 1, lines 10-16]. An I/O unit of a PLC is connected to a plurality of input and output apparatus and is provided with a memory for storing data corresponding to each of these apparatus, serving to periodically accept input data (inclusive of bit variable data which are on-off data and analog variable data which are numerical data) from an external sensor and to store them [column 6, lines 7-13]. Such data is stored in a data collecting unit of the PLC [column 6, lines 29-51]. A monitoring screen displays a bit variable waveform display area 110 and a bit variable data display area 130 for displaying the states of signals comprising an on or off condition [column 7, lines 14-21; column 10, lines 31-67; figure 9]. A bit value of 1 or 0 indicates whether the signal is on or off [column 7, lines 57-60] and thus, the bit variable waveform indicates the bit value corresponding to an input and output state. This would allow a technician to more easily verify operation of the system. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to display a monitoring screen comprising a bit variable waveform display area and a bit variable data display area, as taught by Jinzenji. This would allow a technician to more easily verify operation of the system.
Hashiguchi-Kabayashi-Wu-Iriguchi-Jinzenji do not expressly teach display a hexadecimal numerical value representing the bit values. Walker discloses providing a display interface for a PLC that displays various conditions of the PLC [column 4, lines 21-35]. A menu within the interface allows a user to switch display of units to hexadecimal [column 5, lines 38-45, 56-58]. This would allow a user to more quickly monitor state changes of an I/O module with a plurality of inputs and outputs. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a menu that allows the user to display the bit values of Hashiguchi-Kabayashi-Wu-Iriguchi-Jinzenji as a hexadecimal numerical value, as taught by Walker. This would allow a user to more quickly monitor state changes of an I/O module with a plurality of inputs and outputs.
8. Claims 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Hashiguchi et al (Pub. No. US 2016/0139580), in view of Kobayashi et al (Pub. No. US 2017/0246741), in view of Wu et al (Pub. No. US 2014/0208093), and further in view of Rudaitis (U.S. Patent No. 11,275,359).
8-1. Regarding claim 17, Hashiguchi-Kobayashi-Wu teach all the limitations of claim 1. Hashiguchi-Kobayashi-Wu do not expressly teach wherein the processing circuitry is further configured to detect a forced output command transmitted from a setting tool and, in response to detecting the forced output command, cause the output terminal to output a predetermined value independently of the value of the input signal received by the input terminal. Rudaitis discloses providing a control interface that enables a user to directly control a state of each I/O module, wherein the user can force a state of an output module TRUE or FALSE [column 10, lines 9-20]. This would aid in integration check out and debut when a PLC is not connected to a fieldbus controller [column 10, lines 20-26]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an interface to force a state of an output module, as taught by Rudaitis. This would aid in integration check out and debut when a PLC is not connected to a fieldbus controller.
8-2. Regarding claim 19, Hashiguchi-Kobayashi-Wu teach all the limitations of claim 1. Hashiguchi-Kobayashi-Wu do not expressly teach wherein when the startup determination mode is in the startup mode, the processing circuitry causes each of a plurality of output terminals to output a signal with a value of 1 independently of a value of a signal input into each of a plurality of input terminals to enable examination of operation of an external device connected to the output terminal. Rudaitis discloses providing a control interface that enables a user to directly control a state of each I/O module, wherein the user can force a state of an output module TRUE (e.g., logic 1) or FALSE (e.g., logic 0) [column 10, lines 9-20]. This would aid in integration check out and debut when a PLC is not connected to a fieldbus controller [column 10, lines 20-26]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an interface to force a state of an output module, as taught by Rudaitis. This would aid in integration check out and debut when a PLC is not connected to a fieldbus controller.
Allowable Subject Matter
9. Claim 18 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
10. The Examiner acknowledges the Applicant’s amendments to claims 1, 3, 7, 13-16 and the addition of claims 17-20.
Regarding independent claim 1, Applicant alleges that Hashiguchi et al (Pub. No. US 2016/0139580) in view of Kobayashi et al (Pub. No. US 2017/0246741) do not teach or suggest a flag storage that stores a startup determination flag corresponding to a startup determination mode, wherein the startup determination flag is set on when the startup determination mode is in a startup mode and set off when in a non-startup mode, as has been amended to the claim. Examiner has rejected claim 1 under 35 U.S.C. 103 as being unpatentable over Hashiguchi, in view of Kobayashi, and further in view of Wu et al (Pub. No. US 2014/0208093). Applicant’s arguments have been considered but are moot in view of the new grounds of rejection.
Regarding dependent claims 7 and 13-16, Applicant alleges that Hashiguchi, Kobayashi, and Iriguchi et al (U.S. Patent No. 11,435,716) do not teach or suggest a display configured to display the input state as ON or OFF, the output state as ON or OFF, bit values corresponding to these states, and a hexadecimal numerical value representing the bit values, as has been amended to the claims. Examiner has rejected claims 7, 13, 15, and 16 under 35 U.S.C. 103 as being unpatentable over Hashiguchi, in view of Kobayashi, in view of Wu, in view of Jinzenji et al (U.S. Patent No. 7,505,875), and further in view of Walker et al (U.S. Patent No. 10,082,782), and claim 14 under 35 U.S.C. 103 as being unpatentable over Hashiguchi, in view of Kobayashi, in view of Wu, in view of Iriguchi, in view of Jinzenji, and further in view of Walker. Applicant’s arguments have been considered but are moot in view of the new grounds of rejection.
Applicant states that dependent claims 3-20 recite all the limitations of the independent claims, and thus, are allowable in view of the remarks set forth regarding independent claim 1. However, as discussed above, Hashiguchi, in view of Kobayashi, and further in view of Wu are considered to teach claim 1, and consequently, claims 3-17 and 19-20 are rejected. Examiner notes that claim 18 has been objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims
Conclusion
11. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALVIN H TAN whose telephone number is (571)272-8595. The examiner can normally be reached M-F 10AM-6PM.
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/ALVIN H TAN/Primary Examiner, Art Unit 2118
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