DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “pre-loading capacitor of the common power unit” of claim 17 must be shown or the feature canceled from the claim. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered, and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
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Fig. 10 of Harris annotated by the examiner for ease of reference.
Claims 1-10, and 15-18 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over Harris et al. (US 2002/0158689 A1).
Regarding claims 1 and 8, A modular amplifier (Figs. 10-14, The modular power amplifier 300 packaged as amplifier module (311) with plurality of modules selectively switchable between the input and output) comprising:
- an amplifier housing (Figs. 10-14, The modular power amplifier 300 includes a power amplifier housing assembly 301 which is two chassis, although one housing or more than two housings would be sufficient, and 16 power amplifier slices, 3101 -31016, §0114), said housing provided with;
- an amplifier power input connection (annotated by the examiner as ‘RFIN’, Fig. 10),
- at least one amplifier signal input connection for receiving at least one input signal to be amplified (Fig. 10 shows selective input connection to each of the plurality of modular PA slices 1-n through a power divider 130 from main RF input of the packaged amplifier),
- at least one amplifier signal output connection (annotated by the examiner as ‘RFOUT’, Fig. 10), for delivering at least one amplified signal;
- a plurality of amplifier modules (at least 16 power amplifier slices, 3101 -31016, §0114, wherein each module (375) is packaged as shown in Fig. 12), each module comprising:
- a module power connection (RF input to each of PA slices from 16 different outputs of the power divider 130, Fig. 10) coupled to the amplifier power input connection (RF input connected to the input of the power divider 130);
- a module (375) signal input connection (RF Input, Fig. 14);
- a module signal output connection (RF output, Fig. 14);
- amplification hardware (375, Fig. 12), having an amplifying power;
- a controller (micro-controller module 325), configured for:
- selectively connecting, based on an algorithm (state diagram implemented in computer software, Fig. 20A), the at least one amplifier signal input connection to one or more module signal input connections of amplifier modules (desired power level is achieved by adding the appropriate number of PA slice modules to the modular power amplifier, §0297), for amplifying the at least one input signal to be amplified, and
- connecting the module signal output connection of said one or more amplifier modules to one or more amplifier signal output connections (radial combiner, 400, §0018, Fig. 5A, §0183, Fig. 28).
Further per claim 8, Harris also teaches that the Modular amplifier assembly (Figs. 37A-front view, 37B-side view and 37C-back view), comprising;
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Fig. 37A (left) and Fig. 13 (right) of Harris for ease of reference.
- an assembly housing (rack 900, see Figs. 37A-37C), said housing (rack 900) provided with;
- at least one assembly signal input (entry point to the N-way splitter 130, Fig. 37B), for receiving at least one signal (modulated RFIN signal) to be amplified,
- at least one assembly signal output (output of the radial combiner 400 as shown in Fig. 37C), for delivering at least one amplified signal (RFOUT);
- a common power unit (an auxiliary AC/DC converter 701, and a main AC rectifier circuit 702, §0175, Fig. 37A), for delivering a power to the assembly,
- a plurality of slots (a total of 16 slots in two rows of PA slices with eight slots 3101-8 and 3109-16 for each row, Fig. 37A), each slot is configured for receiving a modular amplifier (PA slices 3101-31016), wherein each slot comprising;
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Fig. 12 of Harris reproduced for ease of reference.
- a power connector (P/S Module, 350, Fig. 12) connected to the common power unit (701, 702, Fig. 37A) on one end and the amplifier power input connection of an inserted amplifier on the other end, for powering the inserted amplifier (say 3101)
- a signal input connector (entry point to the N-way splitter 130, Fig. 37B), connected to the assembly signal input on one end (see Fig. 12), and the at least one amplifier signal input connection (one of the I/O connectors, 318) of an inserted amplifier (say 3101) on the other end, for providing the inserted amplifier with at least a portion of the least one signal to be amplified,
- a signal output connector (other one of the I/O connectors, 318), connected to the assembly signal output on one end (to the radial combiner 400, see Fig. 37C) and the at least one amplifier signal output of an inserted amplifier (say PA slice 3101) on the other end, for delivering an amplified signal,
- a controller unit (325, Fig. 12), wherein the controller unit (325) is configured for;
- selectively forming, based on the algorithm (state diagram of Fig. 20A and flow chart of Fig. 36), one or more amplifier module groups, wherein said groups are formed out of one or more inserted amplifiers (3101-31016), forming one or more virtual amplifiers (keeping them in hot standby mode), and
- connecting the one or more amplifier signal output connections (as inputs to the radial combiner 400, see Fig. 37C) to the one or more assembly signal output connections (to the radial combiner 400, see Fig. 37C).
Wherein per claim 10, the controller unit (for controlling peripherals, such as, power supply unit, cooling mechanism, baseband processing of the power amplifier assembly) of the amplifier assembly and the controller (325) of the amplifier (PA slices 3101-31016) together form an overall controller, said overall controller configured for;
- selecting, out of all available modules (PA slices 3101-31016), one or more groups of modules (depending on the power, gain and linearity requirements), thus forming one or more virtual amplifiers (hot standby mode of PA slices 3101-31016).
Further per claims 3, wherein the at least one amplifier signal input connection (one RF signal enters into the power divider 130) is configured for simultaneously receiving a plurality of signals (divided into 16 different input signal segments, see annotated Fig. 10 of Harris) to be amplified, or wherein the amplifier comprises a plurality of amplifier signal input connections (each input signal segments enter into each PA slice as shown in Fig. 14), each for receiving one signal to be amplified, wherein the controller is further configured for;
- selectively forming, based on the algorithm (Fig. 36), a plurality of one or more amplifier module groups, each for amplifying a signal, forming one or more virtual amplifiers (keeping amplifiers in hot standby mode, Fig. 2oA, §0143).
Also, per claims 2, 4 and 9, Harris teaches (exemplarily shown in the flow chart of Fig. 36) that wherein the algorithm comprises the step of;
- receiving a requested amplification power related (step S40, Fig. 36) to the at least one input signal to be amplified
- monitoring an available amplification power of each module (Steps S41-S43, Fig. 36), and wherein the algorithm further comprises the step of;
- determining, based on the requested amplification power and/or available amplification power of each module, if one amplifier module or a combination of amplifier modules has the requested power available (Steps S44-S45, Fig. 36).
wherein, per claim 5, the controller (microcontroller module 325, Fig. 14) is further configured for;
- determining if an actual performance of at least one amplifier module is exceeding a predetermined performance threshold value (§0187),
- if at least one amplifier module is exceeding the threshold value, assigning an additional amplifier module to the signal (§0142), such that preferably all amplifier modules assigned to the signal meet the performance threshold value (§0142),
- if all amplifier modules are operating at their performance threshold value, equally dividing the request over all amplifier modules (exemplarily taught for the fourth embodiment, Fig. 41, §0293).
wherein per claim 6, the performance threshold value is chosen from the group consisting of;
- an actual power of a module (§0286, as more power is demanded of the transmitter, more number of PA slices are added);
- a temperature of a module (§0147);
- frequencies available in the signal (frequency of operation dictates the available power and gain of the amplifier modules, §0189, §193-§0195);
- moisture inside the amplifier (although Harris is silent about the moisture in the amplifier, since it is a member of a Markush group of alternatively useable members, presence of one member among the many suffice meeting the claim limitation, See MPEP § 2117).
Further per claim 7, Harris also teaches that the wherein the at least one amplifier signal input connection (the incoming RFIN signal is a modulated RF signal) is configured for;
- receiving a composed signal (which enters the divider 130, Fig. 10),
- decomposing (dividing the signal into pluralities of RF input signals, see Figs. 10 and 14) the received composed said composed signal into a plurality of signals to be amplified.
Further per claim 15, Harris also teaches that the system comprises a converter, for converting the digital signal into an analog signal (§0153, §0198, Fig. 19).
Also, per claim 16, Harris teaches that the controller unit is configured to redirecting a requested amplification power over the available amplifier modules if a hardware failure occurs in the assembly (if the controller 326 identifies a fault condition in the hot standby state 1705, the PA module will return to the cold standby state 1700 and redirect the RF signal to a functional hot standby PA module, Fig. 20A, §0156).
wherein per claim 17, Harris teaches that the common power unit (the common power unit (701, 702, Fig. 37A)) is configured for converting a power (an auxiliary AC/DC converter 701, and a main AC rectifier circuit 702) supplied to the assembly (common power unit) into a power (P/S Module, 350, Fig. 12) required by the inserted amplifiers (modules 310 of PA slices), and the controller unit (325) is further configured for pre-loading (a power factor correction and boost regulation circuit 711, a pair of power switching FETs 713, 713a, a load resistor 714 and a load capacitor 715, §0178, Fig. 27) at least one capacitor of the common power unit and/or module (350, Fig. 27).
And finally, per claim 18, the controller unit (325) of Harris is configured for continuously monitoring (SPI bus 720 of the respective PA slices 3101 -310n) the instantaneous power of each module (§0301, Fig. 44), and redirecting the requested amplification power based on the algorithm (Fig. 36).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 11 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Harris.
Regarding claim 11, Harris teaches advanced microprocessor ran microcontroller for RF power amplifier operations for a modern wireless transceiver system having modular architecture.
Harris, however, is not explicit about the algorithm is predetermined or ran by artificial intelligence (AI).
However, it is a common knowledge in sophisticated high power wireless transceiver systems, such as, Harris to implement AI routines to automate the microcontroller decisions under diverse operating conditions. As a teaching reference one can refer to the article of Rui et. al., entitled: “A New Frontier for Power Amplifier enabled by Machine Learning” and published in Microwave Journal on April 17, 2021, by Mitsubishi Electric Research Laboratories, Inc. 201 Broadway, Cambridge, Massachusetts 02139.
In this age of ubiquitous application of AI and machine learning, it would have been obvious to a person of ordinary skill in the art to implement AI routines to automate the microcontroller decisions under diverse operating conditions of the modern wireless transceiver system having modular architecture, such as, Harris. Especially to exploit the optimum performance and speed of machine learning algorithms for radio frequency power amplifiers online operational conditions.
Regarding claim 14, Harris although doesn’t explicitly mention that the controller unit is configured to directing the signals to the inserted amplifiers, such that each signal travels substantially the same path length from input to output, preventing mutual delays between signals.
It is well-known in the art of modular amplifiers where plurality of identical amplifier modules are combined to produce an aggregate power, it is imperative that each signal through each amplifier module path travels substantially the same path length from input to output, preventing mutual delays between signals such that they combine with each other at same phase.
Thus even if it is not explicitly mentioned, it would have been obvious to a person of ordinary skill in the art to making sure that the controller time the switching in and out of amplifier modules synchronized with other amplifier modules such that mutual delays between signals from different paths are prevented (minimized) and combining is done in equal phase for maximizing the output.
Allowable Subject Matters
Claims 12-13 are objected to as being dependent upon a rejected base claim 8 but would be allowable if rewritten in independent form including all the limitations of the base claim 8 and any intervening claims.
Claim 12-13 are allowable because the closest prior art of record, Harris doesn’t teach explicitly that the inserted modular amplifiers mutually communicate through the controller unit.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on (571) 272-1769. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.