Prosecution Insights
Last updated: April 19, 2026
Application No. 18/037,251

LOW-DIVERGENCE MULTI-JUNCTION VCSEL

Non-Final OA §103
Filed
May 16, 2023
Examiner
PARK, KINAM
Art Unit
2828
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Shenzhen Raysees AI Technology Co. Ltd.
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
89%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allow Rate
680 granted / 829 resolved
+14.0% vs TC avg
Moderate +7% lift
Without
With
+7.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
14 currently pending
Career history
843
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
33.8%
-6.2% vs TC avg
§102
40.2%
+0.2% vs TC avg
§112
13.6%
-26.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 829 resolved cases

Office Action

§103
DETAILED ACTION 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 2. The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action: (a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made. 3. Claims 1-20 are rejected under 35 U.S.C. 103(a) as being unpatentable over YANG et al. ( US 20220385041), and further in view of Tan et al. (US 20210336422). Regarding claim 1, YANG et al. discloses in fig. 7 and specification: a Vertical Cavity Surface Emitting Laser (VCSEL) device, comprising: a substrate (see, 202, fig. 7, see also, paragraph [0036]); a first reflector region (see, 206, fig. 7) over the substrate; a second reflector region (see, 215, fig. 7) over the first reflector region; a plurality of active regions (see, 210a, 210b, fig. 7) between the first reflector region and second reflector region; an oxide aperture (see, 214, OA, fig. 7, see also, paragraph [0037], here, oxidation aperture (OA)) between the first reflector region and second reflector region; and a surface relief structure (see, 216, fig. 7, see also, paragraph [0044], here, a curved surface, or the like) over the second reflector region. PNG media_image1.png 358 436 media_image1.png Greyscale However, YANG et al. is silent as to the limitation of “an implantation region between the first reflector region and second reflector region for electrical confinement”. Tan et al. discloses that the electrical and optical confinement, also referred to herein as a confinement layer (or multi-layered structure), can be achieved by, for example, buried tunnel junction (BTJ), or lateral oxidation, ion implantation or other techniques that are known in the art (see, paragraph [0018]). Even though Tan et al. does not disclose that “an implantation region between the first reflector region and second reflector region for electrical confinement” as claimed, Tan et al. discloses the limitation can be realized for electrical confinement. Therefore, it would have been obvious to a person of ordinary skill in the art at the time of invention to combine the limitation of “an implantation region between the first reflector region and second reflector region for electrical confinement” with a VCSEL of YANG et al. because the limitation allows for achieving the electrical confinement of the VCSEL (see, paragraph [0018] of Tan et al.). Regarding claim 2, the modified device of YANG et al. discloses in fig. 7 and specification (YANG et al.) the VCSEL device of claim 1, wherein the first reflector region and the second reflector region each comprise a Distributed Bragg Reflector (DBR) structure (see, n-DBR, p-DBR, fig. 7). Regarding claim 3, the modified device of YANG et al. discloses in fig. 7 and specification (YANG et al.) the VCSEL device of claim 1, wherein the plurality of active regions each include a quantum- well configuration (see, MQW, fig. 7). Regarding claim 4, the modified device of YANG et al. discloses in fig. 7 and specification (YANG et al.) the VCSEL device of claim 1, the oxide aperture is between the second reflector region and the plurality of active regions (see, MQW, fig. 7). Regarding claim 5, the modified device of YANG et al. discloses in fig. 7 and specification (YANG et al.) the VCSEL device of claim 1, wherein the implantation region is between two of the plurality of active regions. Even though Tan et al. does not disclose that the limitation of “an implantation region between wherein the implantation region is between two of the plurality of active regions” as claimed, Tan et al. discloses the limitation can be realized because the limitation allows for achieving the electrical confinement of the VCSEL using the multi-layered structure (see, paragraph [0018] of Tan et al.). Regarding claim 6, claim 6 is rejected for the same reasons applied to claim 5 because the limitation allows for achieving the electrical confinement of the VCSEL using the multi-layered structure (see, paragraph [0018] of Tan et al.). Regarding claim 7, the modified device of YANG et al. discloses in fig. 7 and specification (YANG et al.) the VCSEL device of claim 1, wherein the surface relief structure has a mechanism to suppress higher-order modes of an output beam of the VCSEL device (see, paragraph [0045]). Regarding claims 8-14 , method claims 8-14 are rejected for the same reasons applied to device claims 1-7 since the limitations of method claims 8-15 are implemented by the limitations of device claim 1-7. Regarding claims 15-20 , device claims 15-20 are rejected for the same reasons applied to device claims 1-7 since the limitations of device claims 15-20 are implemented by the limitations of device claims 1-7. Conclusion 4. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kinam Park whose telephone number is (571) 270-1738. The examiner can normally be reached on from 9:00 AM-5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, MINSUN HARVEY, can be reached on (571) 272-1835. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). /KINAM PARK/Primary Examiner, Art Unit 2828
Read full office action

Prosecution Timeline

May 16, 2023
Application Filed
Nov 29, 2025
Non-Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12603480
SEMICONDUCTOR LASER WITH METAL PULL-BACK DBR GRATING
2y 5m to grant Granted Apr 14, 2026
Patent 12603478
SEMICONDUCTOR LASER AND SEMICONDUCTOR LASER DEVICE
2y 5m to grant Granted Apr 14, 2026
Patent 12603472
TIME-OF-FLIGHT SENSOR AND MANUFACTURING METHOD THEREOF
2y 5m to grant Granted Apr 14, 2026
Patent 12597751
LASER-INDUCED GRAPHENE DEVICE BUILT ON WOOD, AND FABRICATION METHOD THEREOF
2y 5m to grant Granted Apr 07, 2026
Patent 12592538
SOLID-STATE LASER SYSTEM, PHASE MATCHING METHOD, AND ELECTRONIC DEVICE MANUFACTURING METHOD
2y 5m to grant Granted Mar 31, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
89%
With Interview (+7.3%)
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 829 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month