Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
In view of Applicant’s amendments, the objection the claims are withdrawn except those addressed below.
In view of Applicant’s amendments, the claim limitation interpreted under 35 USC 112(f) is addressed below.
The amendment integrates the abstract idea into a practical application by imposing a meaningful limit on the abstract idea. In view of Applicant's amendments, the rejection under 35 USC § 101 is withdrawn.
Claim Objections
Claims 1-10 are objected to because of the following informalities:
Claim 1, line 17, replace “that” with – each started -- should be inserted.
Claim 1, line 21, before “LET1”, -- the -- should be inserted.
Claim 1, line 25, before “TD”, -- the -- should be inserted.
Claim 1, line 25, before “LET1”, -- the -- should be inserted.
Claim 2, line 7, “the original start cycle” lacks proper antecedent basis.
Claim 3, line 2, “each cycle” lacks proper antecedent basis.
Claim 4, line 3, “the same core” lacks proper antecedent basis.
Claim 5, line 3, before “LET1”, -- the -- should be inserted.
Claim 5, line 3, “the restarted first processor portion” lacks proper antecedent basis.
Claim 6, line 8, “the substitution timing” lacks proper antecedent basis.
Claim 9, line 3, before “at least one process portion”, -- the -- should be inserted.
Claim 9, line 7, “the supervisory scheduler’s actions” lacks proper antecedent basis.
Claim 10, line 13, “the recorded passage-time value” lacks proper antecedent basis.
Claim 10, line 14, before “LET1”, -- the -- should be inserted.
Claim 10, line 17, “the recorded passage-time value” lacks proper antecedent basis.
Claim 10, line 18, before “LET1”, -- the -- should be inserted.
Claim 10, line 21, before “LET1”, -- the -- should be inserted.
Claims 7-8 depends on objected claims and inherit the same issues as objected claims.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation is: “a data synchronization portion” in claim 1.
Because these claim limitation(s) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. The corresponding structure can be found in paragraph [0129] that discloses:
“Some or all of the above constituent elements, functions, process portions, process means, and the like may be provided in the form of hardware by packaging them in an integrated circuit, or in the form of software by causing a processor to interpret and execute programs that implement respective functions.”
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 1-10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites a data-synchronization portion configured to enforce LET semantics by causing each process portion to read inputs at a defined logical read instant and to publish outputs only at a defined logical write instant.
The specification recites (see paragraph [0040] and [0041]):
The data synchronization portion (1012) may be implemented as an input portion and an output portion separate from each other. In this case, the input portion is started at every execution cycle of the process portion (1011), while the output portion is started after the passage of a LET shorter than the execution cycle set on the process portion (1011).
Data exchange between the process portions (1011) is carried out only through the data synchronization portion (1012). As a result, regardless of execution times of the process portions (1011), the data synchronization portion (1012) operates for a constant execution time. For example, when the process portion B (1011-B) operates at a 30 ms cycle, an interval between an input process of the data synchronization portion (1012) and an output process at the next cycle of the data synchronization portion (1012) is 30 ms. The execution time of the data synchronization portion (1012) is a constant time of 30 ms, regardless of the presence/absence of a different process portion with high priority in the current cycle or the size of the execution time of the process portion B (1011-B) itself. In this case 30 ms is equivalent to a logical execution time (LET) of the process portion B (1011-B).
The specification recites a data synchronization portion may be implemented as an input portion and an output portion and data exchange between process portions is carried out through the data synchronization portion. However, the specification does not disclose each process portion reading inputs at a defined logical read instant or publishing outputs at a defined logical write instant. Thus, the specification does not support “a data-synchronization portion configured to enforce LET semantics by causing each process portion to read inputs at a defined logical read instant and to publish outputs only at a defined logical write instant” of claim 1.
Claim 1 recites “program instructions that, when executed by the multi-core processor, implement a supervisory scheduler that:
(a) records for each started process portion a passage-time value from a start of that process portion within a processing cycle;
(b) compares, for the first process portion, the passage-time value to a determination threshold TD that is shorter LET1 and not greater than an assumed standby time of at least one downstream process portion; and
(c) when the passage-time value for the first process portion exceeds TD before LET₁ elapses, issues an interrupt that stops execution of the first process portion within the same cycle.”
The specification recites (see paragraphs [0055], [0011], [0061], and [0062]):
The time monitoring unit 201 calculates a passage time from the start of execution of the process, based on a process start time notification sent from the process start time notifying unit 202.
A control device has a plurality of cores that execute a plurality of process portions that are started cyclically. The control device includes: a first process portion having a given logical execution time set therefor; and a time monitoring unit that determines an execution state of each of the process portions in a determination time shorter than the logical execution time of the first process portion. The time monitoring determines whether a passage time from the start of the first process portion exceeds the determination time.
The time monitoring unit 2101 compares the process start time imparted by the process portion A with the current time, and determines whether a passage time from the process start time has exceeded an excess risk determination time set on the process portion A (1011-A).
When determining that the passage time has exceeded the excess risk determination time set on the process portion on A (1011-A), the time monitoring unit 201 sends an interruption instruction to the process portion A (1011-A) while sending a start instruction to the process portion B (1011-B).
The specification recites a time monitoring unit calculates a passage time for a process portion, the time monitoring unit determines if the passage time for the process portion exceeds an excess risk determination time set for the process portion, and the time monitoring unit sending an interrupt to the process portion if the passage time exceeds the excess risk determination time set for the process portion. However, the specification does not disclose a supervisory scheduler preforming operations (a), (b), and (c) or comparing, for a processor portion, a passage time to an excess risk determination time shorter than a logical execution time and not greater than an assumed standby time of at least one downstream process portion. Thus, the specification does not support “program instructions that, when executed by the multi-core processor, implement a supervisory scheduler that:” or “(b) compares, for the first process portion, the passage-time value to a determination threshold TD that is shorter LET1 and not greater than an assumed standby time of at least one downstream process portion; and” of claim 1.
Claim 2 recites wherein the supervisory scheduler starts a second process portion as a substitution at a substitution timing selected within the assumed standby time of a downstream process portion and different from the original start cycle of the second process portion, and the second process portion outputs a result capable of substituting for a result of the first process portion.
The specification recites (see paragraph [0069], [0070], and [0125]):
According to this embodiment, in addition to the software configuration of the second, embodiment, the control device further includes a substitution process portion A' (1013-A) substituting for the process portion A (1011-A). The substitution process portion A' (1013-A) is a simple process by which a result that can be used as a substitution for the process portion A (1011-A) is derived in a short time. For example, such a result may be produced by a simple computation process with less input data, or may be outputted simply as a substitution value as a constant.
According to this embodiment, after determining that the processing time of the process portion A (1011-A) has exceeded the excess risk determination time, the time monitoring unit 201 sends an interruption instruction and a start instruction respectively to the process portion A (1011-A) and the process portion B (1011-B) in the same manner as in the second embodiment. In this embodiment, a start instruction is sent to the substitution process portion A' (1013-A) at this point of time. Timing of sending the start instruction to the substitution process portion A' (1013-A) and timing of sending the interruption instruction to the process portion A (1011-A) can be selected arbitrarily, providing that the substitution process portion A' is started after interruption of the process portion A (1011-A). Because the substitution process portion A' (1013-A) has priority lower than that of the process portion B (1011-B), the substitution process portion A' (1013-A) is executed after the end of the process portion B (1 011-B).
“Substitution timing'' is entered in the row corresponding to the process portion B (1011-B) in the high-load module column 2011. This value defined in the table means that as a result of the process portion A (1011-B) having become a high-load state and the LET time having passed, the data exchange portion (1012-C) of the process portion C (1011-C) abandons execution of the process in the cycle and tries restarting at substitution timing, as described in the seventh embodiment.
The specification recites a substitution process portion that can produce a result in place of a result of a first process portion, sending a start instruction to a substitution process portion arbitrarily, and substitution timing at which a process portion restarts. The specification does not disclose a supervisory scheduler that starts a substitution process portion at a substitution timing within an assumed standby time of a downstream process portion and different from an original start cycle of the substitution process portion. Thus, the specification does not support “the supervisory scheduler starts a second process portion as a substitution at a substitution timing selected within the assumed standby time of a downstream process portion and different from the original start cycle of the second process portion” of claim 2.
Claim 4 recites after determining that a further process portion on the same core as the first process portion has ended, the supervisory scheduler issues a restart instruction that causes the first process portion to resume execution within the cycle.
The specification recites (see paragraph [0011] and [0087]):
A control device has a plurality of cores that execute a plurality of process portions that are started cyclically.
In this embodiment, an end time notifying unit (203-B) of the process portion B (1011-B) notifies the time monitoring unit 201 of an end time. When determining that the entire process has been completed, the time monitoring unit 201 sends a restart instruction to the process portion 1011 in an interrupted state. In the example shown in FIG. 1O, the time monitoring unit 201 sends a restart instruction to the process portion A (1011-A). Upon receiving the restart instruction, the process portion A (1011-A) restarts its suspended process.
The specification recites multiple process portions can be executed on the same core and a time monitoring unit issuing a restart instruction to a first process portion after determining a second process portion has ended. However, the specification does not disclose a supervisor scheduler issuing a restart instruction to a first process portion after determining a second process portion has ended. Thus, the specification does not support “after determining that a further process portion on the same core as the first process portion has ended, the supervisory scheduler issues a restart instruction that causes the first process portion to resume execution within the cycle” of claim 4.
Claim 6 recites the supervisory scheduler determines whether the passage-time value from start of the first process portion exceeds the assumed standby time to trigger the substitution timing for the fourth process portion.
The specification recites (see para [0122] and [0125]):
A value indicating ''waiting for the assumed standby time'' is entered in the row corresponding to the process portion C (1011-C) in the high-load module column 2011. This value defined in the table means that as a result of the process portion A (1011-A) having become a high-load state and the LET time having passed, the data exchange portion (1012-B) of the process portion B (1011-B) waits to refrain from starting until the assumed standby time of the process portion A (1011-A) passes. As described in the sixth embodiment, the time monitoring unit 201 calculates a passage time from the start of the cycle, and determines whether the process portion B (1011-B) has waited for a time equal to or longer than the assumed standby time of the process portion A (1011-A). When determining that the process portion B (1011-B) has waited for a time equal to or longer than the assumed standby time of the process portion A (1011-A), the time monitoring unit 201 sends an interruption instruction to the process portion A (1011-A).
“Substitution timing'' is entered in the row corresponding to the process portion B (1011-B) in the high-load module column 2011. This value defined in the table means that as a result of the process portion A (1011-B) having become a high-load state and the LET time having passed, the data exchange portion (1012-C) of the process portion C (1011-C) abandons execution of the process in the cycle and tries restarting at substitution timing, as described in the seventh embodiment.
The specification recites a second process portion waits to start execution until after an assumed standby time for a first process portion has passed and substitution timing at which a process portion restarts. The specification does not disclose a supervisory scheduler determining whether a passage-time value of a first process portion exceeds an assumed standby time to trigger a substitution timing of a second process portion. Thus, the specification does not support “the supervisory scheduler determines whether the passage-time value from start of the first process portion exceeds the assumed standby time to trigger the substitution timing for the fourth process portion” of claim 6.
Claim 7 recites the supervisory scheduler indexes the table to determine substitution timing and which process portions to start or hold.
The specification recites (see para [0113] and [0114]):
The standby time selection table holds, for each process portion 1011, a standby time of the process portion 1011 execution of which is affected by the high-load state of the process portion 1011. In a high-load module column 2011, information for uniquely identifying each process portion 1011 is entered. For example, a unique value is entered in the form of a combination of integers, character strings, or bit patterns. A process portion operation definition column 2012 has the same number of entries as the number of process portions 1011. In each of rows making up the process portion operation definition column 2102, information on the operation of the process portion 1011, such as waiting for a certain period of time or executing the process at substitution timing or suspending the process, is entered. Operation information entries are not limited to the entries mentioned above.
When the operation of the process portion is ''waiting for a certain period of time", time information, such as a fixed time of 1 ms or so, an excess risk determination time of a high-load module, and an assumed standby time held by the process portion 1011 indicated by the process portion operation, definition column 2012, is entered. Time information entries are not limited to the entries mentioned above.
The specification recites a standby time selection table with rows detailing operation of a process portion, such as waiting for a certain period of time or executing the process at substitution timing or suspending the process. The specification does not disclose a supervisory scheduler that indexes a table to determine substitution timing or which process portions to start or hold. Thus, the specification does not support “the supervisory scheduler indexes the table to determine substitution timing and which process portions to start or hold” in claim 7.
Claim 8 recites the supervisory scheduler enforces that outputs produced by any substitution or third process portion are published at their logical write instants so that downstream consumers observe constant LET timing independent of physical preemption of the first process portion.
The specification recites (see paragraph [0040] and [0041]):
The data synchronization portion (1012) may be implemented as an input portion and an output portion separate from each other. In this case, the input portion is started at every execution cycle of the process portion (1011), while the output portion is started after the passage of a LET shorter than the execution cycle set on the process portion (1011).
Data exchange between the process portions (1011) is carried out only through the data synchronization portion (1012). As a result, regardless of execution times of the process portions (1011), the data synchronization portion (1012) operates for a constant execution time. For example, when the process portion B (1011-B) operates at a 30 ms cycle, an interval between an input process of the data synchronization portion (1012) and an output process at the next cycle of the data synchronization portion (1012) is 30 ms. The execution time of the data synchronization portion (1012) is a constant time of 30 ms, regardless of the presence/absence of a different process portion with high priority in the current cycle or the size of the execution time of the process portion B (1011-B) itself. In this case 30 ms is equivalent to a logical execution time (LET) of the process portion B (1011-B).
The specification recites a data synchronization portion may be implemented as an input portion and an output portion and data exchange between process portions is carried out through the data synchronization portion. However, the specification does not disclose a supervisory scheduler that enforces publishing outputs produced by processor portions at their logical write instants. Thus, the specification does not support “the supervisory scheduler enforces that outputs produced by any substitution or third process portion are published at their logical write instants so that downstream consumers observe constant LET timing independent of physical preemption of the first process portion” of claim 8.
Claim 9 recites wherein at least one process portion outputs, via the data-synchronization portion, a control instruction to an actuator and the supervisory scheduler's actions maintain actuator-update determinism by ensuring all publications occur at logical write instants.
The specification recites (see paragraph [0009], [0040], and [0041]):
However, in running control software, the order of execution of processes independent of each other or real-time processing of data may become important factors in some, cases. For example, in a case where an instruction value process portion that calculates a control instruction value in terms of a physical value and an output process portion that outputs a control instruction value to drive equipment, such as a motor, operate independent of each other, if the priority order of the instruction value process portion is lowered, the output process portion becomes unable to acquire continuous values, which affects control performance, e.g., rendering motor control inefficient, in some cases.
The data synchronization portion (1012) may be implemented as an input portion and an output portion separate from each other. In this case, the input portion is started at every execution cycle of the process portion (1011), while the output portion is started after the passage of a LET shorter than the execution cycle set on the process portion (1011).
Data exchange between the process portions (1011) is carried out only through the data synchronization portion (1012). As a result, regardless of execution times of the process portions (1011), the data synchronization portion (1012) operates for a constant execution time. For example, when the process portion B (1011-B) operates at a 30 ms cycle, an interval between an input process of the data synchronization portion (1012) and an output process at the next cycle of the data synchronization portion (1012) is 30 ms. The execution time of the data synchronization portion (1012) is a constant time of 30 ms, regardless of the presence/absence of a different process portion with high priority in the current cycle or the size of the execution time of the process portion B (1011-B) itself. In this case 30 ms is equivalent to a logical execution time (LET) of the process portion B (1011-B).
The specification recites a process portion that outputs a control instruction value to drive equipment, a data synchronization portion may be implemented as an input portion and an output portion, and data exchange between process portions is carried out through the data synchronization portion. The specification does not disclose a supervisory scheduler’s actions maintain actuator-update determinism by ensuring all publications occur at logical write instants. Thus, the specification does not disclose “the supervisory scheduler's actions maintain actuator-update determinism by ensuring all publications occur at logical write instants” of claim 9.
Claim 10 recites comparing, for the first process portion, the recorded passage-time value to a determination threshold shorter than LET1 and not greater than an assumed standby time;
The specification recites (see paragraph [0055]):
The time monitoring unit 2101 compares the process start time imparted by the process portion A with the current time, and determines whether a passage time from the process start time has exceeded an excess risk determination time set on the process portion A (1011-A).
The specification recites a time monitoring unit calculates a passage time for a process portion, the time monitoring unit determines if the passage time for the process portion exceeds an excess risk determination time set for the process portion. The specification does not disclose comparing, for a processor portion, a passage time to an excess risk determination time shorter than a logical execution time and not greater than an assumed standby time of at least one downstream process portion. Thus, the specification does not support “comparing, for the first process portion, the recorded passage-time value to a determination threshold shorter than LET1 and not greater than an assumed standby time;” of claim 10.
Claim 10 recites issuing an interrupt and stopping execution of the first process portion when the recorded passage-time value exceeds the determination threshold before LET1; and then either (i) starting a second process portion at a substitution timing within an assumed standby time, or (ii) using a concurrently executing third process portion on a different core, until the first process portion is restarted and completes within LET₁, whereupon results from the first process portion are selected for downstream consumption at logical write instants.
The specification recites (see paragraphs [0069], [0070, [0125], [0075], [0088], and [0089]):
When determining that the passage time has exceeded the excess risk determination time set on the process portion on A (1011-A), the time monitoring unit 201 sends an interruption instruction to the process portion A (1011-A) while sending a start instruction to the process portion B (1011-B).
According to this embodiment, in addition to the software configuration of the second, embodiment, the control device further includes a substitution process portion A' (1013-A) substituting for the process portion A (1011-A). The substitution process portion A' (1013-A) is a simple process by which a result that can be used as a substitution for the process portion A (1011-A) is derived in a short time. For example, such a result may be produced by a simple computation process with less input data, or may be outputted simply as a substitution value as a constant.
According to this embodiment, after determining that the processing time of the process portion A (1011-A) has exceeded the excess risk determination time, the time monitoring unit 201 sends an interruption instruction and a start instruction respectively to the process portion A (1011-A) and the process portion B (1011-B) in the same manner as in the second embodiment. In this embodiment, a start instruction is sent to the substitution process portion A' (1013-A) at this point of time. Timing of sending the start instruction to the substitution process portion A' (1013-A) and timing of sending the interruption instruction to the process portion A (1011-A) can be selected arbitrarily, providing that the substitution process portion A' is started after interruption of the process portion A (1011-A). Because the substitution process portion A' (1013-A) has priority lower than that of the process portion B (1011-B), the substitution process portion A' (1013-A) is executed after the end of the process portion B (1 011-B).
“Substitution timing'' is entered in the row corresponding to the process portion B (1011-B) in the high-load module column 2011. This value defined in the table means that as a result of the process portion A (1011-B) having become a high-load state and the LET time having passed, the data exchange portion (1012-C) of the process portion C (1011-C) abandons execution of the process in the cycle and tries restarting at substitution timing, as described in the seventh embodiment.
In this embodiment, as in the third embodiment, the core 0 (101-0) has an array of the process portion A (1011-A) and the process portion B (1011-B) and the core 1 (101-1) has a parallel process portion A (1014-A). The parallel process portion 1014, which is a substitution process for the corresponding process portion 1011, is always executed simultaneously with the process portion 1011.
In this embodiment, the process portion A (1011-A) having resumed its process and the parallel process portion A '' (1014-A) complete their calculations within the LET. At this time, both the data exchange portion (1012-A) of the process portion A (1011-A) and the data exchange portion (1012-A2) of the parallel process portion (1014 -A) can transmit calculation results to the data exchange portion (1012-B) of the process portion B (1011-B).
At this time, the data exchange portion (1012-B) of the process portion B (1011-B) selects data to acquire, depending on whether an end time notifying unit (203-A) of the process portion A (1011-A) has notified of an end time. When the end time notifying unit (2:103-A) has notified of the end time, the data exchange portion (1012-B) of the process portion B (1011-B) acquires a calculation result from the data exchange portion (1012-A) of the process portion A (1011-A). When the end time notifying unit (203-A) has not notified of the end time, on the other hand, the data exchange portion (1 012- B) of the process portion B (1011-B) acquires a calculation result from the data exchange portion (1012-A2) of the parallel process portion A'' (1014-A).
The specification recites, a time monitoring unit interrupts a process portion if a passage time for the process portion exceeds an excess risk determination time set for the process portion, a substitution process portion that can produce a result in place of a result of a first process portion, sending a start instruction to a substitution process portion arbitrarily, substitution timing at which a process portion restarts, executing a parallel process portion on a separate core than the first process portion, the first process portion resuming and completing calculations within LET1 , and a second process portion acquiring the result from the first process portion. However, the specification does not disclose starting a second process portion at a substitution timing within an assumed standby time or results from a first processor portion selected for downstream consumption at logical write instants. Thus, the specification does not support “(i) starting a second process portion at a substitution timing within an assumed standby time” or “whereupon results from the first process portion are selected for downstream consumption at logical write instants” of claim 10.
Claims 3 and 5 depend on the rejected claims and inherit the same issues.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6, lines 4-5, “the logical execution time” is unclear whether it refers to “a logical execution time” in lines 3-4 of claim 6 or “a logical execution time” in line 8 of claim 1. For the following prior art rejection, “the logical execution time” in lines 4-5 of claim 6 is treated as --the logical execution time for the fourth processor portion--.
Claim 6, line 7, “the assumed standby time” is unclear whether it refers to “an assumed standby time” in line 4 of claim 6 or “an assumed standby time” in line 22 of claim 1. For the following prior art rejection, “the assumed standby time” in line 7 of claim 6 is treated as --the assumed standby time for the fourth processor portion--.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
With respect to independent claim 1, the prior art of record does not teach or suggest, either solely, or in combination, the limitations “(b) compares, for the first process portion, the passage-time value to a determination threshold TD that is shorter LET1 and not greater than an assumed standby time of at least one downstream process portion; and” when considered in combination with the other limitations of claim 1.
With regard to claim 10, the prior art of record does not teach or suggest, either solely, or in combination, the limitations “comparing, for the first process portion, the recorded passage-time value to a determination threshold shorter LET1 and not greater than an assumed standby time;” when considered in combination with the other limitations of claim 10.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Suzuki (U.S. Patent Application Publication No. US 20130160023 A1) discloses “In the embodiment, when another core executes processes having a dependence relation, a standby time period may also occur by the time when the processes come to an end. However, in the embodiment, processes of another application are not executed in all the standby time periods as are in the conventional case but it is determined whether each of the processes of the other application is to be executed, based on the determination as to whether the length of each of the standby time periods is shorter than a predetermined value. For example, when it is determined that the length of the standby time period is shorter than the predetermined value, the processes of the other application are not executed (the process of (3) above). Therefore, even when a standby time period occurs, the cores do not always execute other processes. As a result, the number of occurrences of the cache-miss caused by the execution of the other processes is reduced. When it is determined that the standby time period is longer than the predetermined value, another process is executed using the standby time period and therefore, the processing efficiency of the core can also be maintained.” (Suzuki, para [0048]) and “Therefore, a case may be present where a core #0 executes the process 1 included in an application and another core (for example, a core #1) executes one of the other processes that precede the process 1. In this case, when no other executable process block is present for the core #0, the core #0 has to stand by until the preceding processes executed by the core #1 come to an end.” (Suzuki, para [0012]).
Yamauchi (U.S. Patent Application Publication No. US 20130138886 A1) discloses “The determining unit 1001 has a function of determining if the priority level of a process to be executed (hereinafter "given process") is greater than or equal to a threshold in the multi-core processor system 100. For example, the determining unit 1001 determines if the priority level of a given process assigned to each core and among a group of processes to be assigned for execution to cores (CPU #0 to CPU #n) of the multi-core processor system 100 is greater than or equal to the threshold. The result of determination by the determining unit 1001 is stored temporarily in a memory area, such as the other memory 1008.” (Yamauchi, para [0059]).
Ziegenbein (German Patent Application Publication No. DE 102016202305 A1) discloses “It is ensured that the communication between the tasks takes place only at certain times, with the aim of ensuring a deterministic and reproducible behavior of the entire system, regardless of the utilization of the executing processor.” (Ziegenbein, page 5, third paragraph, English translation), “shows a communication between a 5ms and a 10ms task. A program flow ensures that the transmission of the data from the sender to the receiver occurs exactly once per slower time interval. A counter mechanism ensures that data is transferred only after the last execution of the faster task within the time interval of the slower task. The counters counter_5ms, 5ms_ready and 10ms_ready of the counter mechanism are in 3 shown and with 22 . 20 and 21 designated. This ensures the deterministic behavior in the sense of the "Logical Execution Time".” (Ziegenbein, page 5, tenth paragraph, English translation), and “The tasks can be executed on the same or different cores.” (Ziegenbein, page 5, tenth paragraph, English translation).
Han (Resource-Aware Scheduling for Dependable Multicore Real-Time Systems: Utilization Bound and Partitioning Algorithm 2019) discloses “To guarantee the deadlines of tasks and meet different reliability targets, the overloading technique has been utilized in the fault-tolerant real-time scheduling [4], where multiple task copies execute in parallel and can overlap with their time intervals during executions. Notice that at least one copy of every task must complete before deadline even in the presence of faults [6]” (Han, page 2808, right column, second full paragraph).
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/S.S.N./Examiner, Art Unit 2192
/S. Sough/SPE, Art Unit 2192