DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim status
Claims 1-18 and 20 are pending; claim 1 is independent. Claim 19 has been cancelled.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Arguments
Applicant's arguments filed 04/30/2026 have been fully considered but they are not persuasive.
In response to applicant’s argument that Tian, Tian '64, Li, Zhang, and Zhang '40, either individually or in combination, fail to teach or suggest (i) improves scan-signal waveform adjustment in the display area; (ii) supports both forward scanning and reverse scanning through distinct transistor-controlled paths; and (iii) reduces coupling differences among data lines caused by introduced functional lines (e.g., control lines), thereby improving display uniformity. The cited combination does not teach or suggest this coordinated architecture.
However, the examiner respectfully disagrees Tian taught in figs 1, 2 and Paras 0033-0035, wherein If the N-th level scan signal is input from one end of the N-th scan line, a density of the connection nodes close to another end of the N-th scan line is greater than a density of the connection nodes close to the one end of the N-th scan line from which the N-th level scan signal is input. if the N-th level scan signal is input from two ends of the N-th scan line, a density of the connection nodes in a middle of the N-th scan line is greater than a density of the connection nodes close to any end of the N-th scan line). The auxiliary module 200 comprises a plurality of auxiliary units that contains a plurality of TFTs arranged at a terminal end of the scan line for scan signal transmission to enhance falling (pull-down) of the scan signal in a terminal end area, so as to further improve sharp falling of the falling edge of the scan signal, (i) improves scan-signal waveform adjustment in the display area.
Tian also taught in fig. 5, VGL and Para 0073, wherein a first line DDL can be a constant low-potential line VGL, and the constant low-potential line VGL is configured to connect a constant low-potential signal. The constant low-potential line VGL is connected to an input end of the (N−1)-th auxiliary unit 209, an input end of the N-th auxiliary unit 210, and an input end of the (N+1)-th auxiliary unit 220) and three scan lines to perform waveform compensation for both rising and falling edges of scan signals, the three scan lines respectively corresponding to an (N-1)-th, an N-th, and an (N+1)-th scan stage associated with the waveform adjustment module, wherein N varies according to the scan stage to which the waveform adjustment module belongs (fig. 5 and Paras 0070-0072, wherein an output end of an (N−1)-th auxiliary unit 209 is electrically connected to an (N−1)-th driving line. An output end of the N-th auxiliary unit 210 is electrically connected to the N-th driving line. An output end of an (N+1)-th auxiliary unit 220 is electrically connected to the (N+1)-th driving line), (ii) supports both forward scanning and reverse scanning through distinct transistor-controlled paths.
In response to applicant’s argument that Tian does not disclose (a) the electrical connection of each waveform adjustment module (WAM) to a potential transmission line, a forward control line, and a reverse control line; (b) a plurality of dummy traces parallel to the data lines, with a first side of each data line being provided with one trace selected from the potential transmission line, the forward scanning control line, the reverse scanning control line, or a dummy trace; or (c) a 4-transistor WAM in which separate transistor pairs independently connect the potential transmission line to the N-th scan line for forward and reverse scanning.
However, the examiner respectfully disagrees Tian taught in fig. 5, VGL and Para 0073, wherein a first line DDL can be a constant low-potential line VGL, and the constant low-potential line VGL is configured to connect a constant low-potential signal. The constant low-potential line VGL is connected to an input end of the (N−1)-th auxiliary unit 209, an input end of the N-th auxiliary unit 210, and an input end of the (N+1)-th auxiliary unit 220) and three scan lines to perform waveform compensation for both rising and falling edges of scan signals, the three scan lines respectively corresponding to an (N-1)-th, an N-th, and an (N+1)-th scan stage associated with the waveform adjustment module, wherein N varies according to the scan stage to which the waveform adjustment module belongs (fig. 5 and Paras 0070-0072, wherein an output end of an (N−1)-th auxiliary unit 209 is electrically connected to an (N−1)-th driving line. An output end of the N-th auxiliary unit 210 is electrically connected to the N-th driving line. An output end of an (N+1)-th auxiliary unit 220 is electrically connected to the (N+1)-th driving line (a) the electrical connection of each waveform adjustment module (WAM) to a potential transmission line, a forward control line, and a reverse control line;
“Zhang 40” to include a forward scanning process, the fourth transistor (fig. 5, transistor 506) and a fifth transistor (fig. 5, transistor 504) are turned on according to a signal from the forward scanning control line and a signal from the (N+1)-th scan line, respectively; and a reverse scanning process the sixth transistor (fig. 5, transistor 505) and the seventh transistor (fig. 5, transistor 503) are turned on according to a signal from the reverse scanning control line and a signal from the (N-1)-th scan line, respectively.
When combing the waveform adjustment module of Tian with the circuit (fig. 5) of “Zhang 40” to include fourth, fifth, sixth and seven transistors to enhance falling (pull-down) of the scan signal in a terminal end area, so as to further improve sharp falling of the falling edge of the scan signal.
In response to applicant’s argument that Tian '64 Does Not Cure the Deficiencies of Tian4 and Li Does Not Remedy the Deficiencies of Tian and Tian '64.
However, both references have been withdrawn from rejection to claim 1.
In response to applicant's argument that Zhang '40 is directed to circuitry in a different structural and functional context, namely GOA stabilization. The Office Action does not adequately explain why a skilled artisan would transplant that 4-transistor logic into Applicant's display-area waveform- adjustment architecture, much less combine it with the claimed trace arrangement adjacent to the data lines, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
In response to applicant's argument that (i) the specific trace arrangement in which a first side of each data line is provided with one trace selected from the potential transmission line, the forward scanning control line, the reverse scanning control line, or a dummy trace; and (ii) the specific four-transistor arrangement by which forward scanning and reverse scanning are respectively controlled through different transistor pairs to connect the potential transmission line and the N-th scan line, the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
The rest of applicant’s arguments with respect to claims 1-18 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
For the same reasons above rejection of claims 2-18 and 20 still stands.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 10-15 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tian (CN 113257134), provided by applicant’s IDS, using US 2024/0038130 as English translation, hereinafter Tian, in view of Sun (CN114141794 A), using (US 2023/0178564), as English translation, hereinafter Sun, and further in view of Zhang (CN 106782240), using English translation, hereinafter “Zhang 40”.
Regarding claim 1, Tian teaches a display panel (fig. 1), comprising:
a display area (fig. 1, a display area AA and Para 0036);
a plurality of scan lines comprising an (N-1)-th, an N-th, and an (N+1)-th scan line (figs 1, 2 and Para 0049), and
a plurality of data lines (fig. 1 and Para 0052).
a plurality of waveform adjustment modules disposed in the display area (fig. 1 and Para 0049, wherein the auxiliary module 200 is located in the display area AA, and the auxiliary module 200 comprises a plurality of auxiliary units 210); and
at least one gate driving circuit disposed on two sides of the display area (fig. 1 and Para 0036, wherein the driving module 100 can be a GOA circuit or a gate driving circuit, located on both sides of the display area),
wherein a distribution density of the waveform adjustment modules in an area away from the gate driving circuit is greater than a distribution density of the waveform adjustment modules in an area close to the gate driving circuit (figs 1, 2 and Paras 0033-0035, wherein If the N-th level scan signal is input from one end of the N-th scan line, a density of the connection nodes close to another end of the N-th scan line is greater than a density of the connection nodes close to the one end of the N-th scan line from which the N-th level scan signal is input. if the N-th level scan signal is input from two ends of the N-th scan line, a density of the connection nodes in a middle of the N-th scan line is greater than a density of the connection nodes close to any end of the N-th scan line);
a potential transmission line, a forward scanning control line, and a reverse scanning control line electrically connected to each waveform adjustment module (fig. 5, VGL and Para 0073, wherein a first line DDL can be a constant low-potential line VGL, and the constant low-potential line VGL is configured to connect a constant low-potential signal. The constant low-potential line VGL is connected to an input end of the (N−1)-th auxiliary unit 209, an input end of the N-th auxiliary unit 210, and an input end of the (N+1)-th auxiliary unit 220) and three scan lines to perform waveform compensation for both rising and falling edges of scan signals, the three scan lines respectively corresponding to an (N-1)-th, an N-th, and an (N+1)-th scan stage associated with the waveform adjustment module, wherein N varies according to the scan stage to which the waveform adjustment module belongs (fig. 5 and Paras 0070-0072, wherein an output end of an (N−1)-th auxiliary unit 209 is electrically connected to an (N−1)-th driving line. An output end of the N-th auxiliary unit 210 is electrically connected to the N-th driving line. An output end of an (N+1)-th auxiliary unit 220 is electrically connected to the (N+1)-th driving line); and
Tian does not expressly disclose a plurality of dummy traces parallel to the data lines, wherein a first side of each data line is provided with one trace selected from the potential transmission line, the forward scanning control line, the reverse scanning control line, or the dummy traces.
However, Sun discloses” a plurality of dummy traces parallel to the data lines, wherein a first side of each data line is provided with one trace selected from the potential transmission line, the forward scanning control line, the reverse scanning control line, or the dummy traces”, see fig. 4 and Paras 0048-0050.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the display panel of Tian by applying the teaching of “Sun” including an electrical potential transmission line VGLL and/or a control line CTRL which are extend synchronously or in parallel with the data lines to reduce a coverage area of the black matrix and increase the aperture ratio, as a known technique to get a predictable result.
Tian in view of Sun does not expressly disclose wherein each waveform adjustment module comprises a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; wherein in a forward scanning process, the fourth transistor is turned on according to a signal from the forward scanning control line and the fifth transistor is turned on according to a signal from the (N+1)-th scan line to connect the potential transmission line and the N-th scan line; and wherein in a reverse scanning process, the sixth transistor is turned on according to a signal from the reverse scanning control line and the seventh transistor is turned on according to a signal from the (N-1)-th scan line to connect the potential transmission line and the N-th scan line.
However, “Zhang 40” discloses wherein each waveform adjustment module comprises a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor (fig. 5, transistors 506, 504, 505 and 503, respectively).
wherein in a forward scanning process, the fourth transistor is turned on according to a signal from the forward scanning control line (fig. 5, transistor 506) and the fifth transistor is turned on according to a signal from the (N+1)-th scan line to connect the potential transmission line and the N-th scan line (fig. 5, transistor 504); and
wherein in a reverse scanning process, the sixth transistor is turned on according to a signal from the reverse scanning control line (fig. 5, transistor 505) and the seventh transistor is turned on according to a signal from the (N-1)-th scan line to connect the potential transmission line and the N-th scan line (fig. 5, transistor 503), see fig. 5 and Pages 5-7.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the display panel of Tian in view of Sun with the teaching of “Zhang 40” to include adjustment circuit including four transistors, wherein a gate terminal of the fourth transistor receives a first control signal, a gate terminal of the fifth transistor receives a scan signal, a gate terminal of the sixth transistor receives a second control signal and a gate terminal of the seventh transistor receives the other of the scan signal, to connect a low voltage signal (VGL) to the nth scan line during a forward or reverse scanning period (fig. 5), as a known technique to get a predictable result.
Regarding claim 2, Tian in view of Sun and in view of “Zhang 40” teaches the display panel according to claim 1, wherein the display area comprises a first display region and a second display region sequentially arranged along a direction perpendicular to an extension direction of the scan lines (fig. 1, two display regions upper region (a first region) and lower region ( a second region), see reproduce figure 1 below, Tian);
an effective display width of the first display region is greater than an effective display width of the second display region; the first display region comprises a plurality of first sub-areas; and the second display region comprises a plurality of second sub-areas (figs 1, 2 and Paras 0033-0034, from the figure below a width of first display region is greater than the width of a second display region because the first region includes a middle region which it’s density of the connection nodes is greater than a density of the connection nodes close to any end of the N-th scan line, Tian).
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Regarding claim 3, Tian in view of Sun and in view of “Zhang 40” teaches the display panel according to claim 2, wherein two gate driving circuits are arranged on two sides of the display area respectively, and a width from left to right of the first display region is equal to a width from left to right of the second display region (fig. 1 and Para 0036, wherein the driving module 100 can be a GOA circuit or a gate driving circuit, located on both sides of the display area, Tian); and
a distribution density of the waveform adjustment modules in the first sub-area farthest from the gate driving circuit is greater than a distribution density of the waveform adjustment modules in the second sub-area farthest from the gate driving circuit (Paras 0033-0034, wherein If the N-th level scan signal is input from one end of the N-th scan line, a density of the connection nodes close to another end of the N-th scan line is greater than a density of the connection nodes close to the one end of the N-th scan line from which the N-th level scan signal is input. if the N-th level scan signal is input from two ends of the N-th scan line, a density of the connection nodes in a middle of the N-th scan line is greater than a density of the connection nodes close to any end of the N-th scan line, Tian).
Regarding claim 4, Tian in view of Sun and in view of “Zhang 40” teaches the display panel according to claim 2, wherein two gate driving circuits are disposed on two sides of the first display region respectively, and one gate driving circuit is disposed on one of two sides of the second display region (fig. 1 and Para 0036, wherein the driving module 100 can be a GOA circuit or a gate driving circuit, located on both sides of the display area, Tian); and
a distribution density of the waveform adjustment modules in the first sub-area farthest from the gate driving circuit is less than a distribution density of the waveform adjustment modules in the second sub-area farthest from the gate driving circuit (Paras 0033-0034, wherein If the N-th level scan signal is input from one end of the N-th scan line, a density of the connection nodes close to another end of the N-th scan line is greater than a density of the connection nodes close to the one end of the N-th scan line from which the N-th level scan signal is input. if the N-th level scan signal is input from two ends of the N-th scan line, a density of the connection nodes in a middle of the N-th scan line is greater than a density of the connection nodes close to any end of the N-th scan line, Tian).
Regarding claim 5, Tian in view of Sun and in view of “Zhang 40” teaches the display panel according to claim 2, wherein a first difference is a difference between a distribution density of the waveform adjustment modules in the first sub-area far away from the gate driving circuit and a distribution density of the waveform adjustment modules in the first sub-area close to the gate driving circuit; a second difference is a difference between a distribution density of the waveform adjustment modules in the second sub-area far away from the gate driving circuit and a distribution density of the waveform adjustment modules in the second sub-area close to the gate driving circuit; and the first difference is greater than the second difference (fig. 1 and Para 0034, (see the figure in rejection to claim 1 above), wherein, a width of first display region is greater than the width of a second display region because the first region includes a middle region which it’s density of the connection nodes is greater than a density of the connection nodes close to any end of the N-th scan line, Tian).
Regarding claim 6, Tian in view of Sun and in view of “Zhang 40” Tian teaches the display panel according to claim 2 and the display device according to claim 11, at least one of the forward scanning control line, the reverse scanning control line, or the potential transmission line extends into the display area from a non-display area which is arranged on a different side from a side where the gate driving circuit is disposed (fig. 5, VGL and Para 0073-0074, Tian).
Regarding claim 10, Tian in view of Sun and in view of “Zhang 40” teaches a display device, comprising the display panel of claim 1, wherein the waveform adjustment modules increase verticality of end edges of scan signals during a forward scanning process or a reverse scanning process (Para 0033, wherein, if the N-th level scan signal is input from one end of the N-th scan line, a density of the connection nodes close to another end of the N-th scan line is greater than a density of the connection nodes close to the one end of the N-th scan line from which the N-th level scan signal is input, considering the N-th scan line located vertically, Tian).
Regarding claim 11, Tian in view of Sun and in view of “Zhang 40” teaches the display device according to claim 10, wherein the display area comprises a first display region and a second display region sequentially arranged along a direction perpendicular to an extension direction of the scan lines (fig. 1, two display regions upper region (a first region) and lower region ( a second region), see reproduce figure 1 in rejection claim 2 above, Tian);
an effective display width of the first display region is greater than the effective display width of the second display region; the first display region comprises a plurality of first sub-areas; and the second display region comprises a plurality of second sub-areas (fig. 1 and Para 0034, (see the figure in rejection to claim 2 above), wherein, a width of first display region is greater than the width of a second display region because the first region includes a middle region which it’s density of the connection nodes is greater than a density of the connection nodes close to any end of the N-th scan line, Tian).
Regarding claim 12, Tian in view of Sun and in view of “Zhang 40” teaches the display device according to claim 11, wherein two gate driving circuits are arranged on two sides of the display area respectively, and a width from left to right of the first display region is equal to a width from left to right of the second display region (fig. 1 and Para 0036, wherein the driving module 100 can be a GOA circuit or a gate driving circuit, located on both sides of the display area, Tian); and
a distribution density of the waveform adjustment modules in the first sub-area farthest from the gate driving circuit is greater than a distribution density of the waveform adjustment modules in the second sub-area farthest from the gate driving circuit (Paras 0033-0034, wherein If the N-th level scan signal is input from one end of the N-th scan line, a density of the connection nodes close to another end of the N-th scan line is greater than a density of the connection nodes close to the one end of the N-th scan line from which the N-th level scan signal is input. if the N-th level scan signal is input from two ends of the N-th scan line, a density of the connection nodes in a middle of the N-th scan line is greater than a density of the connection nodes close to any end of the N-th scan line, Tian).
Regarding claim 13, Tian in view of Sun and in view of “Zhang 40” teaches the display device according to claim 11, wherein two gate driving circuits are disposed on two sides of the first display region respectively, and one gate driving circuit is disposed on one of two sides of the second display region (fig. 1 and Para 0036, wherein the driving module 100 can be a GOA circuit or a gate driving circuit, located on both sides of the display area, Tian); and
a distribution density of the waveform adjustment modules in the first sub-area farthest from the gate driving circuit is less than a distribution density of the waveform adjustment modules in the second sub-area farthest from the gate driving circuit (Paras 0033-0034, wherein If the N-th level scan signal is input from one end of the N-th scan line, a density of the connection nodes close to another end of the N-th scan line is greater than a density of the connection nodes close to the one end of the N-th scan line from which the N-th level scan signal is input. if the N-th level scan signal is input from two ends of the N-th scan line, a density of the connection nodes in a middle of the N-th scan line is greater than a density of the connection nodes close to any end of the N-th scan line, Tian).
Regarding claim 14, Tian in view of Sun and in view of “Zhang 40” teaches the display device according to claim 11, wherein a first difference is a difference between a distribution density of the waveform adjustment modules in the first sub-area far away from the gate driving circuit and a distribution density of the waveform adjustment modules in the first sub-area close to the gate driving circuit; a second difference is a difference between a distribution density of the waveform adjustment modules in the second sub-area far away from the gate driving circuit and a distribution density of the waveform adjustment modules in the second sub-area close to the gate driving circuit; and the first difference is greater than the second difference (fig. 1 and Para 0034, (see the figure in rejection to claim 2 above), wherein, a width of first display region is greater than the width of a second display region because the first region includes a middle region which it’s density of the connection nodes is greater than a density of the connection nodes close to any end of the N-th scan line, Tian).
Regarding claim 15, Tian in view of Sun and in view of “Zhang 40” Tian teaches the display device according to claim 11, wherein the scan lines extend from the at least one gate driving circuit to the display area; and at least one of the forward scanning control line, the reverse scanning control line, or the potential transmission line extends into the display area from a non-display area which is arranged on a different side from a side where the gate driving circuit is disposed(fig. 5, VGL and Para 0073-0074, Tian).
Regarding claim 20, Tian in view of Sun and in view of “Zhang 40” teaches the display device according to claim 10, wherein a first electrode of the fourth transistor is electrically connected to a potential transmission line, and a gate of the fourth transistor is electrically connected to a forward scanning control line (fig. 5, transistor 506, “Zhang 40”);
a first electrode of the fifth transistor is electrically connected to a second electrode of the fourth transistor, a gate of the fifth transistor is electrically connected to an (N+1)-th scan line, and a second electrode of the fifth transistor is electrically connected to an N-th scan line (fig. 5, transistor 504, “Zhang 40”);
a first electrode of the sixth transistor is electrically connected to a first electrode of the fourth transistor, and a gate of the sixth transistor is electrically connected to a reverse scanning control line (fig. 5, transistor 505, “Zhang 40”); and
a first electrode of the seventh transistor is electrically connected to a second electrode of the sixth transistor, a gate of the seventh transistor is electrically connected to an (N−1)-th scan line, and a second electrode of the seventh transistor is electrically connected to the N-th scan line (fig. 5, transistor 503), (fig. 5 and Pages 5-7, “Zhang 40”).
Claim(s) 7-9 and 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tian (CN 113257134), provided by applicant’s IDS, using US 2024/0038130 as English translation, hereinafter Tian, in view of Sun (CN 114141794), using (US 2023/0178564) as English translation, hereinafter Sun, in view of Zhang (CN 106782240), using English translation, hereinafter “Zhang 40”, and further in view of Tian (CN 114170985), provided by applicant’s IDS, using (US 2024/0221564), as English translation, hereinafter “Tian 64”.
Regarding claims 7-9 and 16-18, Tian in view of Sun and in view of “Zhang 40” teaches the display panel according to claim 6, wherein in a same width range, a distribution density of the waveform adjustment modules in the first sub-area is greater than “less than, claims 8-9 and 17-18” a distribution density of the waveform adjustment modules in the second sub-area (figs 1, 2 and Paras 0033-0035, from the figure 1, wherein, if the N-th level scan signal is input from two ends of the N-th scan line, a density of the connection nodes in a middle of the N-th scan line is greater than a density of the connection nodes close to any end of the N-th scan line, Tian)
However, the examiner maintains that it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art as design choice arrange a width, the first sub-area and the second sub-area in the display area. It is noted by the examiner that ‘it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)”. Examiner respectfully submits that if there is no evidence in applicant’s specification that such specific “width range, the first sub-area and the second sub-area” will yield unpredictable result, the examiner assumes that it is obvious to reach such width range, the first sub-area and the second sub-area through experimentation to reach the optimized level, and
a potential transmission supplementary line electrically connected to the waveform adjustment modules (fig. 5, VGL and Para 0073, Tian); and
at least one of the forward scanning control supplementary line, the reverse scanning control supplementary line, or the potential transmission supplementary line extends into the corresponding first sub-area from a non-display area which is on a different side from a side where the gate driving circuit is disposed and is close to the first display region (fig. 5, VGL and Para 0073-0074, Tian).
Tian in view of Sun and in view of “Zhang 40” does not expressly disclose the display panel further comprises a forward scanning control supplementary line, a reverse scanning control supplementary line
However, “Tian 64” discloses “the display panel further comprises a forward scanning control supplementary line, a reverse scanning control supplementary line”, see fig. 3 and Paras 0069-0070.
a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the display panel of Tian in view of Sun and in view of “Zhang 40” with the teaching of “Tian 64” to include a forward and backward scan control module which is configured to control a Nth stage gate driving unit to perform forward scan or backward scan according to a forward scan control signal or a backward scan control signal, as a known technique to yield a predictable result.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Du (US 2021/0118390), relates to the field of display techniques, and to
a gate driver on array (GOA) circuit for display panels.
Lee (US 2016/0189664) relates to a non-quadrangular display and a driving method thereof.
Ono (US 11,348,533), elates generally to electronic devices with displays and more
particularly, to display driver circuitry for displays such as organic light-emitting diode (OLED) displays.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for replying to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAIFELDIN E ELNAFIA whose telephone number is (571)270-5852. The examiner can normally be reached 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM BODDIE can be reached at (571) 272-0666. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S.E.E/Examiner, Art Unit 2625 8/24/2026
/WILLIAM BODDIE/Supervisory Patent Examiner, Art Unit 2625
Prosecution Insights