DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/23/2025 has been entered.
Claim status
Claims 1-20 are pending; claim 1 is independent.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in People’s Republic of China on 03/28/2023. It is noted, however, that applicant has not filed a certified copy of the CN 202310317472.9 application as required by 37 CFR 1.55.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tian (CN 113257134), provided by applicant’s IDS, using US 2024/0038130 as English translation, hereinafter Tian, in view of Tian (CN 114170985), provided by applicant’s IDS, using (US 2024/0221564), as English translation, hereinafter “Tian 64”, and further in view of Li (US 2018/0342194), hereinafter Li.
Regarding claim 1, Tian teaches a display panel (fig. 1), comprising:
a display area (fig. 1, a display area AA and Para 0036);
a plurality of waveform adjustment modules disposed in the display area (fig. 1 and Para 0049, wherein the auxiliary module 200 is located in the display area AA, and the auxiliary module 200 comprises a plurality of auxiliary units 210); and
at least one gate driving circuit disposed on two sides of the display area (fig. 1 and Para 0036, wherein the driving module 100 can be a GOA circuit or a gate driving circuit, located on both sides of the display area);
wherein a distribution density of the waveform adjustment modules in an area away from the gate driving circuit is greater than a distribution density of the waveform adjustment modules in an area close to the gate driving circuit (figs 1, 2 and Paras 0033-0034, wherein If the N-th level scan signal is input from one end of the N-th scan line, a density of the connection nodes close to another end of the N-th scan line is greater than a density of the connection nodes close to the one end of the N-th scan line from which the N-th level scan signal is input. if the N-th level scan signal is input from two ends of the N-th scan line, a density of the connection nodes in a middle of the N-th scan line is greater than a density of the connection nodes close to any end of the N-th scan line).
wherein the display area comprises a first display region and a second display region each extending along an extension direction of the scan lines, and the first display region and the second display region are sequentially arranged along a direction perpendicular to the extension direction of the scan lines (fig. 1, two display regions upper region (a first region) and lower region ( a second region), see reproduce figure 1 below);
wherein when the width of the first display region is different from a width of the second display region, and in respective farthest areas of the first and second display region to the gate driving circuit, a distribution density of the waveform adjustment modules per unit area in the first display region is different from a distribution density of the waveform adjustment modules per unit area in the second display region (figs 1, 2 and Para 0035, from the figure below width of the first display region is different from a width of the second display region, wherein the farther the scan signal is transmitted in the corresponding scan line, the more serious transmission delay of the scan signal. Therefore, more TFTs are arranged at a terminal end of the scan line for scan signal transmission to enhance falling (pull-down) of the scan signal in a terminal end area, so as to further improve sharp falling of the falling edge of the scan signal);
wherein a distribution density of the waveform adjustment modules in an area in each of the first and second display regions is adapted based on respective distances of these two areas to the gate driving circuit to achieve uniform display across varying regional widths (figs 1, 2 and Paras 0033-0035, wherein If the N-th level scan signal is input from one end of the N-th scan line, a density of the connection nodes close to another end of the N-th scan line is greater than a density of the connection nodes close to the one end of the N-th scan line from which the N-th level scan signal is input. if the N-th level scan signal is input from two ends of the N-th scan line, a density of the connection nodes in a middle of the N-th scan line is greater than a density of the connection nodes close to any end of the N-th scan line).
wherein each waveform adjustment module is electrically connected to a potential transmission line (fig. 5, VGL and Para 0073, wherein a first line DDL can be a constant low-potential line VGL, and the constant low-potential line VGL is configured to connect a constant low-potential signal. The constant low-potential line VGL is connected to an input end of the (N−1)-th auxiliary unit 209, an input end of the N-th auxiliary unit 210, and an input end of the (N+1)-th auxiliary unit 220) and three scan lines to perform waveform compensation for both rising and falling edges of scan signals, the three scan lines respectively corresponding to an (N-1)-th, an N-th, and an (N+1)-th scan stage associated with the waveform adjustment module, wherein N varies according to the scan stage to which the waveform adjustment module belongs (fig. 5 and Paras 0070-0072, wherein an output end of an (N−1)-th auxiliary unit 209 is electrically connected to an (N−1)-th driving line. An output end of the N-th auxiliary unit 210 is electrically connected to the N-th driving line. An output end of an (N+1)-th auxiliary unit 220 is electrically connected to the (N+1)-th driving line);
Tian does not expressly disclose wherein each waveform adjustment module is electrically connected to a forward scanning control line, a reverse scanning control line.
However, “Tian 64” discloses “wherein each waveform adjustment module is electrically connected to a forward scanning control line, a reverse scanning control line”, see fig. 3 and Paras 0069-0071.
a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the display panel of Tian by applying the teaching of “Tian 64” to include forward and backward scan control module is configured to control the Nth stage gate driving unit to perform forward scan or backward scan according to a forward scan control signal U2D or a backward scan control signal D2U, so that the display panel further includes a scan line, a forward scan control line, a reverse scan control line, and a potential transmission line electrically connected to the waveform adjusting module, the scan line extending from the gate drive circuit to the display area, gives technical insight into the waveform adjusting module connection line arrangement for optimizing circuit impedance, and the like, as a known technique to get a predictable result.
Tian in view of “Tian 64” does not expressly disclose the first display region and the second display region having different effective display widths resulting from a non-rectangular outer contour of the display area
However, Li disclosed “the first display region and the second display region having different effective display widths resulting from a non-rectangular outer contour of the display area”, see fig. 5 and Paras 0068-0069.
a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the display panel of Tian in view of “Tian 64” by applying the teaching of Li to include a circular display area provided with a plurality of scan lines and a plurality of data signal lines and a non-display area including a plurality of gate driving circuits and at least one load compensating unit to corresponds to one gate driving circuit to compensate a load of one gate driving circuit which can improve the phenomena of non-uniform brightness of the display panel, so as to improve display quality of the display panel, as a known technique to get a predictable result.
PNG
media_image1.png
633
595
media_image1.png
Greyscale
Regarding claim 2, Tian teaches the display panel according to claim 1, wherein an effective display width of the first display region is greater than an effective display width of the second display region; the first display region comprises a plurality of first sub-areas; and the second display region comprises a plurality of second sub-areas (figs 1, 2 and Paras 0033-0034, from the figure above a width of first display region is greater than the width of a second display region because the first region includes a middle region which it’s density of the connection nodes is greater than a density of the connection nodes close to any end of the N-th scan line).
Regarding claim 3, Tian teaches the display panel according to claim 2, wherein two gate driving circuits are arranged on two sides of the display area respectively, and a width from left to right of the first display region is equal to a width from left to right of the second display region (fig. 1 and Para 0036, wherein the driving module 100 can be a GOA circuit or a gate driving circuit, located on both sides of the display area); and
a distribution density of the waveform adjustment modules in the first sub-area farthest from the gate driving circuit is greater than a distribution density of the waveform adjustment modules in the second sub-area farthest from the gate driving circuit (Paras 0033-0034, wherein If the N-th level scan signal is input from one end of the N-th scan line, a density of the connection nodes close to another end of the N-th scan line is greater than a density of the connection nodes close to the one end of the N-th scan line from which the N-th level scan signal is input. if the N-th level scan signal is input from two ends of the N-th scan line, a density of the connection nodes in a middle of the N-th scan line is greater than a density of the connection nodes close to any end of the N-th scan line).
Regarding claim 4, Tian teaches the display panel according to claim 2, wherein two gate driving circuits are disposed on two sides of the first display region respectively, and one gate driving circuit is disposed on one of two sides of the second display region (fig. 1 and Para 0036, wherein the driving module 100 can be a GOA circuit or a gate driving circuit, located on both sides of the display area); and
a distribution density of the waveform adjustment modules in the first sub-area farthest from the gate driving circuit is less than a distribution density of the waveform adjustment modules in the second sub-area farthest from the gate driving circuit (Paras 0033-0034, wherein If the N-th level scan signal is input from one end of the N-th scan line, a density of the connection nodes close to another end of the N-th scan line is greater than a density of the connection nodes close to the one end of the N-th scan line from which the N-th level scan signal is input. if the N-th level scan signal is input from two ends of the N-th scan line, a density of the connection nodes in a middle of the N-th scan line is greater than a density of the connection nodes close to any end of the N-th scan line).
Regarding claim 5, Tian teaches the display panel according to claim 2, wherein a first difference is a difference between a distribution density of the waveform adjustment modules in the first sub-area far away from the gate driving circuit and a distribution density of the waveform adjustment modules in the first sub-area close to the gate driving circuit; a second difference is a difference between a distribution density of the waveform adjustment modules in the second sub-area far away from the gate driving circuit and a distribution density of the waveform adjustment modules in the second sub-area close to the gate driving circuit; and the first difference is greater than the second difference (fig. 1 and Para 0034, (see the figure in rejection to claim 1 above), wherein, a width of first display region is greater than the width of a second display region because the first region includes a middle region which it’s density of the connection nodes is greater than a density of the connection nodes close to any end of the N-th scan line).
Regarding claims 6 and 15, Tian teaches the display panel according to claim 2 and the display device according to claim 11, at least one of the forward scanning control line, the reverse scanning control line, or the potential transmission line extends into the display area from a non-display area which is arranged on a different side from a side where the gate driving circuit is disposed (fig. 5, VGL and Para 0073-0074).
Regarding claims 7-9 and 16-18, Tian teaches the display panel according to claim 6, wherein in a same width range, a distribution density of the waveform adjustment modules in the first sub-area is greater than “less than, claims 8-9 and 17-18” a distribution density of the waveform adjustment modules in the second sub-area (figs 1, 2 and Paras 0033-0035, from the figure 1, wherein, if the N-th level scan signal is input from two ends of the N-th scan line, a density of the connection nodes in a middle of the N-th scan line is greater than a density of the connection nodes close to any end of the N-th scan line)
However, the examiner maintain that is it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art as design choice arrange a width, the first sub-area and the second sub-area in the display area. It is noted by the examiner that ‘it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)”. Examiner respectfully submits that if there is no evidence in applicant’s specification that such specific “width range, the first sub-area and the second sub-area” will yield unpredictable result, the examiner assumes that it is obvious to reach such width range, the first sub-area and the second sub-area through experimentation to reach the optimized level, and
a potential transmission supplementary line electrically connected to the waveform adjustment modules (fig. 5, VGL and Para 0073); and
at least one of the forward scanning control supplementary line, the reverse scanning control supplementary line, or the potential transmission supplementary line extends into the corresponding first sub-area from a non-display area which is on a different side from a side where the gate driving circuit is disposed and is close to the first display region (fig. 5, VGL and Para 0073-0074).
Tian does not expressly disclose the display panel further comprises a forward scanning control supplementary line, a reverse scanning control supplementary line
However, “Tian 64” discloses “the display panel further comprises a forward scanning control supplementary line, a reverse scanning control supplementary line”, see fig. 3 and Paras 0069-0070.
a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the display panel of Tian by applying the teaching of “Tian 64” to include a forward and backward scan control module which is configured to control a Nth stage gate driving unit to perform forward scan or backward scan according to a forward scan control signal or a backward scan control signal as a known technique to get a predictable result.
Regarding claim 10, Tian teaches a display device, comprising the display panel of claim 1, wherein the waveform adjustment modules increase verticality of end edges of scan signals during a forward scanning process or a reverse scanning process (Para 0033, wherein, if the N-th level scan signal is input from one end of the N-th scan line, a density of the connection nodes close to another end of the N-th scan line is greater than a density of the connection nodes close to the one end of the N-th scan line from which the N-th level scan signal is input, considering the N-th scan line located vertically).
Regarding claim 11, Tian teaches the display device according to claim 10, wherein the effective display width of the first display region is greater than the effective display width of the second display region; the first display region comprises a plurality of first sub-areas; and the second display region comprises a plurality of second sub-areas (fig. 1 and Para 0034, (see the figure in rejection to claim 1 above), wherein, a width of first display region is greater than the width of a second display region because the first region includes a middle region which it’s density of the connection nodes is greater than a density of the connection nodes close to any end of the N-th scan line).
Regarding claim 12, Tian teaches the display device according to claim 11, wherein two gate driving circuits are arranged on two sides of the display area respectively, and a width from left to right of the first display region is equal to a width from left to right of the second display region (fig. 1 and Para 0036, wherein the driving module 100 can be a GOA circuit or a gate driving circuit, located on both sides of the display area); and
a distribution density of the waveform adjustment modules in the first sub-area farthest from the gate driving circuit is greater than a distribution density of the waveform adjustment modules in the second sub-area farthest from the gate driving circuit (Paras 0033-0034, wherein If the N-th level scan signal is input from one end of the N-th scan line, a density of the connection nodes close to another end of the N-th scan line is greater than a density of the connection nodes close to the one end of the N-th scan line from which the N-th level scan signal is input. if the N-th level scan signal is input from two ends of the N-th scan line, a density of the connection nodes in a middle of the N-th scan line is greater than a density of the connection nodes close to any end of the N-th scan line).
Regarding claim 13, Tian teaches the display device according to claim 11, wherein two gate driving circuits are disposed on two sides of the first display region respectively, and one gate driving circuit is disposed on one of two sides of the second display region (fig. 1 and Para 0036, wherein the driving module 100 can be a GOA circuit or a gate driving circuit, located on both sides of the display area); and
a distribution density of the waveform adjustment modules in the first sub-area farthest from the gate driving circuit is less than a distribution density of the waveform adjustment modules in the second sub-area farthest from the gate driving circuit (Paras 0033-0034, wherein If the N-th level scan signal is input from one end of the N-th scan line, a density of the connection nodes close to another end of the N-th scan line is greater than a density of the connection nodes close to the one end of the N-th scan line from which the N-th level scan signal is input. if the N-th level scan signal is input from two ends of the N-th scan line, a density of the connection nodes in a middle of the N-th scan line is greater than a density of the connection nodes close to any end of the N-th scan line).
Regarding claim 14, Tian teaches the display device according to claim 11, wherein a first difference is a difference between a distribution density of the waveform adjustment modules in the first sub-area far away from the gate driving circuit and a distribution density of the waveform adjustment modules in the first sub-area close to the gate driving circuit; a second difference is a difference between a distribution density of the waveform adjustment modules in the second sub-area far away from the gate driving circuit and a distribution density of the waveform adjustment modules in the second sub-area close to the gate driving circuit; and the first difference is greater than the second difference (fig. 1 and Para 0034, (see the figure in rejection to claim 1 above), wherein, a width of first display region is greater than the width of a second display region because the first region includes a middle region which it’s density of the connection nodes is greater than a density of the connection nodes close to any end of the N-th scan line).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tian, in view of “Tian 64”, In view of Li and further in view of Zhang (US 2020/0273418).
Regarding claim 19, Tian, in view of “Tian 64”and In view of Li teaches the display device according to claim 10, but Tian, in view of “Tian 64”and In view of Li does not expressly disclose wherein each of the waveform adjustment modules comprises a first transistor, a second transistor, and a third transistor; a first electrode of the first transistor is electrically connected to a reverse scanning control line, and a gate of the first transistor is electrically connected to an (N−1)-th scan line; a first electrode of the second transistor is electrically connected to the forward scanning control line, and a gate of the second transistor is electrically connected to an (N+1)-th scan line; a gate of the third transistor is electrically connected to a second electrode of the first transistor and a second electrode of the second transistor; and a first electrode of the third transistor is electrically connected to a potential transmission line, and a second electrode of the third transistor is electrically connected to an N-th scan line.
However, Zhang discloses wherein each of the waveform adjustment modules comprises a first transistor (NT1), a second transistor (NT2), and a third transistor (NT6);
a first electrode of the first transistor is electrically connected to a reverse scanning control line, and a gate of the first transistor is electrically connected to an (N−1)-th scan line (fig. 5, NT1 and Para 039);
a first electrode of the second transistor is electrically connected to the forward scanning control line, and a gate of the second transistor is electrically connected to an (N+1)-th scan line (fig. 5, NT2 and Para 0040);
a gate of the third transistor is electrically connected to a second electrode of the first transistor and a second electrode of the second transistor; and a first electrode of the third transistor is electrically connected to a potential transmission line, and a second electrode of the third transistor is electrically connected to an N-th scan line (fig. 5, NT6 and Para 0042).
a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the display panel of Tian, in view of “Tian 64” and view of Li by applying the teaching of Zhang to include a forward and reverse scan control module which includes a first transistor (NT1), a second transistor (NT2), and a third transistor (NT6) to provide a gate driver on array (GOA) circuit can improve the stability of the gate driver on array circuit.as a known technique to get a predictable result.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tian, in view of “Tian 64”, In view of Li, and further in view of Zhang (CN 106782240), suing English translation, hereinafter “Zhang 40”.
Regarding claim 20, Tian, in view of “Tian 64”and In view of Li teaches the display device according to claim 10, but Tian, in view of “Tian 64”and In view of Li does not expressly disclose wherein each of the waveform adjustment modules comprises a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; a first electrode of the fourth transistor is electrically connected to a potential transmission line, and a gate of the fourth transistor is electrically connected to a forward scanning control line; a first electrode of the fifth transistor is electrically connected to a second electrode of the fourth transistor, a gate of the fifth transistor is electrically connected to an (N+1)-th scan line, and a second electrode of the fifth transistor is electrically connected to an N-th scan line; a first electrode of the sixth transistor is electrically connected to a first electrode of the fourth transistor, and a gate of the sixth transistor is electrically connected to a reverse scanning control line; and a first electrode of the seventh transistor is electrically connected to a second electrode of the sixth transistor, a gate of the seventh transistor is electrically connected to an (N−1)-th scan line, and a second electrode of the seventh transistor is electrically connected to the N-th scan line.
However, “Zhang 40” discloses wherein each of the waveform adjustment modules comprises a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor (fig. 5, transistors 503-506);
a first electrode of the fourth transistor is electrically connected to a potential transmission line, and a gate of the fourth transistor is electrically connected to a forward scanning control line (fig. 5, transistor 504);
a first electrode of the fifth transistor is electrically connected to a second electrode of the fourth transistor, a gate of the fifth transistor is electrically connected to an (N+1)-th scan line, and a second electrode of the fifth transistor is electrically connected to an N-th scan line (fig. 5, transistor 506);
a first electrode of the sixth transistor is electrically connected to a first electrode of the fourth transistor, and a gate of the sixth transistor is electrically connected to a reverse scanning control line (fig. 5, transistor 503); and
a first electrode of the seventh transistor is electrically connected to a second electrode of the sixth transistor, a gate of the seventh transistor is electrically connected to an (N−1)-th scan line, and a second electrode of the seventh transistor is electrically connected to the N-th scan line (fig. 5, transistor 505), see fig. 5 and Pages 5-7.
a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the display panel of Tian, in view of “Tian 64”and In view of Li by applying the teaching of “Zhang 40” to include adjustment circuit including four transistors, wherein a gate terminal of the fourth transistor receives a first control signal, a source/drain terminal of the fourth transistor is connected to source/drain terminal of the fifth transistor, and source/drain terminal of the fourth transistor is connected to a low potential voltage, wherein a gate terminal of the fifth transistor receives the scan signal, source/drain terminal of the fifth transistor connected to an N-th scan line, wherein a gate terminal of the sixth transistor receives one of the scan signal, source/drain terminal of the sixth transistor is connected to source/drain terminal of the fourth transistor, and wherein a gate terminal of the seventh transistor receives the other of the scan signal, source/drain terminal of the seventh transistor is connected to the nth scan line (fig. 5), as a known technique to get a predictable result.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Du (US 2021/0118390), relates to the field of display techniques, and in particular to
a gate driver on array (GOA) circuit for display panel.
Lee (US 2016/0189664), relates to a non-quadrangular display and a driving method thereof.
Ono (US 11,348,533), elates generally to electronic devices with displays and, more
particularly, to display driver circuitry for displays such as organic light-emitting diode (OLED) displays.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAIFELDIN E ELNAFIA whose telephone number is (571)270-5852. The examiner can normally be reached 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM BODDIE can be reached at (571) 272-0666. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/S.E.E/Examiner, Art Unit 2625 1/24/2026
/WILLIAM BODDIE/Supervisory Patent Examiner, Art Unit 2625