DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to Applicant’s Amendment and Remarks filed on 12 November 2025.
Claims 1-9 are pending in this application. Claims 7-9 are newly added.
Claim objections
Claim 6 is objected to because of the following informalities:
In claim 6, line 8, it recites “changing a processing content of processing a process”. It should be amended as “changing a processing content of a process”. (see claim 1 above).
Appropriate corrections are required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-9 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more.
Claim 1 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1, Statutory Category: Yes, the claim 1 is a control apparatus that controls a processing device that recites a series of steps and therefore falls in the statutory category of a machine.
Step 2A- Prong 1: Judicial Exception Recited: Yes, the claim recites: “to monitor a buffer used by each of the plurality of processes executed by the processing device in order to transfer a task and estimate a load on the processing device based on an amount of data waiting to be processed in the buffer; and to change a processing content of a process having a lowest priority among the plurality of processes executed by the processing device to decrease a load of the process having the lowest priority in a case where the load on the processing device is larger than a first threshold.” As drafted, the claim as a whole recites a control apparatus that including steps could be performed in the human mind, but for the recitation of generic computing components. The human mind can easily judging/evaluating/monitoring the usage of the buffer to determine/estimate the load, and to adjusting/changing/modifying(planning to change) the processing content having a lowest priority among the plurality of processes executed by the processing device to decrease a load of the process having the lowest priority in a case where the load on the processing device is larger than a first threshold (i.e., based on the determination/comparing). Therefore, but for the recitation of generic computing components, these steps may be a Mental Processes that can be performed in the human mind (including an observation, evaluation, judgment, opinion).
Therefore, yes, the claims do recite judicial exceptions.
Step 2A- Prong 2: Integrated into a practical Application: No, this judicial exception is not integrated into a practical application. In particular, the claim recites an additional limitations that “a monitoring unit, comprising one or more processors, configured to monitor” and “a change unit, comprising one or more processors, configured to change” which is directed to Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a generic computer as a tool to perform an abstract idea (see MPEP 2106.05(f)). In addition, “A control apparatus that controls a processing device that executes a plurality of processes” is an attempt to generally link the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))). Accordingly, even in combination, these additional elements do not integrate the abstract idea into a practical application because they not impose any meaningful limits on practicing the abstract idea. Therefore, the claim is directed to the abstract idea.
Step 2B: Claim provides an Inventive Concept: No. The additional element “A control apparatus that controls a processing device that executes a plurality of processes” is an attempt to generally link the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))). In addition, the limitation of “a monitoring unit, comprising one or more processors, configured to monitor” and “a change unit, comprising one or more processors, configured to change” which is directed to Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a generic computer as a tool to perform an abstract idea (see MPEP 2106.05(f)). These additional elements and combination of the elements does not amount to significant more than the exception itself or provide an inventive concept in Step 2B.
For these reasons, there is no inventive concept in the claim, and thus the claim is ineligible.
Independent claims 5 and 6 are rejected for the same reason as claim 1 above. Claim 5 further recites “a computer” and claim 6 further recites “A non-transitory computer readable storage medium having stored there on a program for causing one or more processors”. These additional elements implement an abstract idea on a generic computer, or merely uses a generic computer or computer components as a tool to perform the abstract idea, thus is not a practical application under Prong 2, or amount to significantly more than the judicial exception under Step 2B. See MPEP 2106.05(f).
With respect to the dependent claim 2, the claim elaborates that wherein the change unit is configured to change a processing content of one of the plurality of processes executed by the processing device to increase a load of the one of the plurality of processes, in a case where the load on the processing device is smaller than a second threshold (“change a processing content…to increase a load” as being treated as part of abstract idea and is analogous to Mental processes, such that concept can be performed in the human mind. Further, the claim as a whole is a Mental Processes that can be performed in the human mind (including an observation, evaluation, judgment, opinion)).
With respect to the dependent claim 3, the claim elaborates that wherein the processing device executes each of the plurality of processes using a Graphics Processing Unit (GPU), and the monitoring unit is configured to monitor the buffer and estimate a load on the GPU (“executes each of the plurality of processes using a Graphics Processing Unit (GPU)” which is merely applying the judicial exception or abstract idea (See MPEP 2106.05(f)) and “monitor the buffer and estimate a load on the GPU” as being treated as part of abstract idea and is analogous to Mental processes, such that concept can be performed in the human mind. Further, the claim as a whole is a Mental Processes that can be performed in the human mind (including an observation, evaluation, judgment, opinion)).
With respect to the dependent claim 4, the claim elaborates that wherein the processing device is configured to connect a plurality of images together and synthesize a wide image, and the change unit is configured to change a processing content of a process of combining overlapping areas overlapping between adjacent images (“connect a plurality of images together and synthesize a wide image” and “change a processing content of a process of combining overlapping areas overlapping between adjacent images” as being treated as part of abstract idea and is analogous to Mental processes, such that concept can be performed in the human mind. Further, the claim as a whole is a Mental Processes that can be performed in the human mind (including an observation, evaluation, judgment, opinion)).
With respect to the dependent claim 7, the claim elaborates that wherein the processing content comprises one or more of a blending scheme, a seam generation interval, or a seam search scheme (the claim recite instructions to implement an abstract idea on a generic computer, or merely uses a generic computer or computer components as a tool to perform the abstract idea, thus is not a practical application under Prong 2, or amount to significantly more than the judicial exception. See MPEP 2106.05(f)).
Dependent claims 8-9 recite the same features as applied to claim 7 above, therefore they are also rejected under the same rationale.
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over SHIMAMURA et al. (US Pub. 2019/0095247 A1) in view of McCrary et al. (US Pub. 2011/0050713 A1) and further in view of Kitada et al. (US Pub. 2006/0067406 A1) and Adachi et al. (US Pub. 2009/0292404 A1)
SHIMAMURA was cited in the previous Office Action.
As per claim 1, SHIMAMURA teaches the invention substantially as claimed including A control apparatus that controls a processing device that executes a plurality of processes (SHIMAMURA, Fig. 4 100 control device, 160 application parsing part, 32 application programs; Abstract, lines 1-3, A configuration of a control device capable of efficiently operating multiple types of programs in different execution formats on a single control device is provided; [0008] lines 1-4, realizing multiple types of programs (e.g., ladder program, CNC program, robot program, etc.) in different execution formats with one single control device), the control apparatus comprising:
monitor a buffer used by each of the plurality of processes executed by the processing device and estimate a load on the processing device based on amount of data waiting to be processed in the buffer (SHIMAMURA, Fig. 4, 170 shared memory, 32 different types of application programs are input to 160 application parsing part; [0190] lines 4-7, in the shared memory 170, an internal command buffer 60 is prepared for storing the internal command sequentially generated by the application parsing part 160 (as a buffer used by each of the plurality of processes executed by the processing device); [0188] lines 1-9, The aforementioned processing state of the task may be based on the number of buffers of the internal command 40 generated from the application program 32. That is, the information that indicates the load related to the generation process of the internal command may include the number of internal commands that have not yet been processed (as amount of data waiting to be processed in the buffer) by the control command calculation part 164 among the internal commands generated by the application parsing part 160 (i.e., high load based on large number of internal commands stored in the buffer); [0192] lines 1-4. The load state, etc. of the target task can be evaluated (as estimate the load on the processing device) based on the number of internal commands 40 stored in the internal command buffer 60, and the priority of the target task can be changed based on the evaluation result; [0195] lines 1-4 the load state of the target task can be evaluated by monitoring the number of internal commands stored in the internal command buffer 60 of the shared memory 170; also see Fig. 19, 170 inter command); and
a change unit, comprising one or more processors (SHIMAMURA, [0009] lines 1-2, a control device having one or more processors is provided; [0122] lines 1-5, The priority changing part 156 (as change unit) monitors the processing state of the application parsing part 160, and when the processing state of the application parsing part 160 meets a predetermined condition, the priority changing part 156 changes the priority that has been set to the task) configured to change priority of a process, in a case where the load on the processing device is larger than a first threshold (SHIMAMURA, [0152] lines 1-7, The control device 100 according to the embodiment monitors the processing state of the third task 20 (the parsing process for the application program 32), and when the processing state meets a predetermined condition, changes the priority that has been set to the third task 20 according to the condition. The change according to this condition may include raising the priority or lowering the priority; [0193] lines 1-5, using the number of internal commands (the internal command buffer number) stored in the internal command buffer 60 as shown in FIG. 11, for example, a condition of whether or not the internal command buffer number is lower than a predetermined threshold value can be adopted. When this condition is met, the priority of the target task may be raised; [0194] lines 1-4, if the internal command buffer number remains higher than the predetermined threshold value over a predetermined period, the priority of the target task may be lowered; (as change to a lower priority, in a case where the load on the processing device is larger than a first threshold); also see [0033] lines 3-6, the priority can be raised before the load of the parsing part becomes excessive; [0195] lines 1-4 the load state of the target task can be evaluated by monitoring the number of internal commands stored in the internal command buffer 60 of the shared memory 170; [0261] lines 2-4, wherein the information that indicates the load comprises a number of internal commands, which have not yet been processed by the command calculation part).
Although SHIMAMURA teaches monitor a buffer used by each of the plurality of processes executed by the processing device, SHIMAMURA fails to specifically teach a monitoring unit, comprising one or more processors, configured to monitor a buffer used in order to transfer a task.
However, McCrary teaches a monitoring unit, comprising one or more processors, configured to monitor a buffer used in order to transfer a task (McCrary, [0045] lines 2-9, GPU 104 (as monitoring unit, comprising one or more processors, see Fig. 1, 150 command processor) monitors the ring buffers to detect ring buffers available for processing. For example, as a game application executes on CPU 101, commands for operations requiring graphics processing are enqueued by CPU 101 to ring buffers 110 in the form of command buffers, as described in relation to step 305 of process 300. As command buffers are generated and enqueued to ring buffers in accordance with executing applications; [0036] lines 15-17, one or more ring buffers may be initialized for use in transferring instructions and data from subsequent applications to the GPU 104 (as used in order to transfer a task)).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of SHIMAMURA with McCrary because McCrary’s teaching of GPU that monitoring the buffer and using the buffer to transferring instruction for processing would have provided SHIMAMURA’s system with the advantage and capability to allow the system to easily managing and scheduling the instructions/commands for processing within the GPU which improving the system performance and efficiency (see McCrary, Abstract, “performing prioritization and scheduling of commands in the GPU, system performance is enhanced”).
SHIMAMURA and McCrary fail to specifically teach when configured to change priority of a process, it is to change a processing content of a process having a lowest priority among the plurality of processes executed by the processing device to decrease a load of the process having the lowest priority, in a case where the load on the processing device is larger than a first threshold.
However, Kitada teaches change a processing content of a process having a priority executed by the processing device to decrease a load of the process, in a case where the load on the processing device is larger than a first threshold (Kitada, Fig. 6, S102, YES or No, YES to S104; [0145] lines 2-14, it is possible to execute automatic switching between motion video reproduction with priority on image quality and motion video reproduction with priority on smoothness rather than the image quality, in accordance with the load on the computer 10. Specifically, if the system is in the low load state, motion video with high quality can be displayed by executing the normal decoding process. When the system is in the high load state, the load on the system is decreased by altering the content of the pixel interpolation process that requires a great amount of processing. Thereby, smooth motion video reproduction is realized without such problems as frame dropping or extreme slowness in motion of objects (as to change a processing content of a process having a priority to decrease load of the process, i.e., focus on smooth motion instead on image quality); [0018] lines 17-20, an interpolation prediction control process that alters a content of the pixel interpolation process, thereby to reduce the load on the information processing apparatus; [0115] lines 1-5, The video reproduction application program 201 checks whether the current load amount of the computer 10 is greater than a predetermined reference value, thereby determining whether the computer 10 is in the high load state or not).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of SHIMAMURA and McCrary with Kitada because Kitada’s teaching of altering the content of the pixel interpolation process in case the load is higher would have provided SHIMAMURA and McCrary’s system with the advantage and capability to allow the system to dynamically adjusting the process content based on the load which improving the user experience and system resource utilization.
SHIMAMURA, McCrary and Kitada fail to specifically teach when change the processing content of a process, it is the process having lowest priority among the plurality of processes.
However, Adachi teaches when change the processing content of a process, it is the process having lowest priority among the plurality of processes (Adachi, [0048] lines 1-9, When multiple types of applications are running concurrently, such types may be acquired so as to change the operation of a running application according to the combination of the types thus acquired. For example, a priority may be assigned to each type of application, and the operation may be changed according to the priorities of running applications so that the operation of a type of application having a lower priority is restrained first; also see [0081] lines 5-11, the image rendering function has a higher priority than the audio function for game applications. Accordingly, the reaction table 118 defines in the corresponding column therein the control method of "silent mode" as the first step for restraining the operation of a game application, so as to restrain the audio function having a lower priority first (as audio function is lowest priory among the audio function and image rendering function)).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of SHIMAMURA, McCrary and Kitada with Adachi because Adachi’s teaching of changing the processing content from lower priority first would have provided SHIMAMURA, McCrary and Kitada’s system with the advantage and capability to allow the system to ensuring the higher priority still processing under high load (heat) situation in order to efficient control of heat generated by hardware in a computer system (see Adachi, [0005]).
As per claim 2, SHIMAMURA, McCrary, Kitada and Adachi teach the invention according to claim 1 above. SHIMAMURA teaches wherein the change unit is configured to change a priority of one of the plurality of processes executed by the processing device, in a case where the load on the processing device is smaller than threshold. (SHIMAMURA, [0122] lines 1-5, The priority changing part 156 (as change unit) monitors the processing state of the application parsing part 160, and when the processing state of the application parsing part 160 meets a predetermined condition, the priority changing part 156 changes the priority that has been set to the task; [0033] lines 3-6, the priority can be raised before the load of the parsing part becomes excessive, so as to prevent occurrence of the situation that the internal command is not generated in time; [0193] lines 1-7, In the case of using the number of internal commands (the internal command buffer number) stored in the internal command buffer 60 as shown in FIG. 11, for example, a condition of whether or not the internal command buffer number is lower than a predetermined threshold value can be adopted. When this condition is met, the priority of the target task may be raised).
In addition, Kitada further teaches when change a priority, it is to change a processing content of one of the plurality of processes executed by the processing device to increase a load of the one of the plurality of processes, in a case where the load on the processing device is smaller than a second threshold (Kitada, Fig. 10, S401, NO, to S404, NO to S406. The content of processing (i.e., S402, S405, and S407) is changed if the load is not exceeding corresponding performance levels; [0138] lines 1-7, If the current load corresponds to decode performance level 1 (YES in step S401), the interpolation prediction unit 308 selects the above method (a) and executes the process of generating 1/2 pixel signals using the 6-tap filter (step S402). Then, the interpolation prediction unit 308 executes the motion compensation prediction process using the 1/2 pixel signals (step S403). [0139] lines 1-7, If the current load amount corresponds to decode performance level 2 (YES in step S404), the interpolation prediction unit 308 selects the above method (b), generates 1/2 pixel signals using the 2-tap filter, and then generates 1/4 pixel signals using the 2-tap filter (step S405) (as to increase load). Subsequently, the interpolation prediction unit 308 executes the motion compensation prediction process using the 1/4 pixel signals (step S403). [0140] lines 1-7, If the current load corresponds to decode performance level 3 (YES in step S406), the interpolation prediction unit 308 selects both the above methods (a) and (b), and generates 1/2 pixel signals using the 2-tap filter (step S407); [0141] lines 1-4, If the current load is higher than decode performance level 3 (NO in step S406), the interpolation prediction unit 308 selects the above method (c) and skips the pixel interpolation process (step S408) [Examiner noted: change a processing content of one of the plurality of processes executed by the processing device to increase a load of the one of the plurality of processes, in a case where the load on the processing device is smaller than a second threshold (i.e., smaller than level 3 as indicated in Fig. 10, S406)]; also see [0137] The high load state is classified into decode performance levels 1, 2 and 3. The load on the computer becomes higher in the order of levels 1, 2 and 3).
As per claim 5, it is a control method claim of claim 1 above. Therefore, it is rejected for the same reason as claim 1 above.
As per claim 6, it is a non-transitory computer readable storage medium claim of claim 1 above. Therefore, it is rejected for the same reason as claim 1 above.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over SHIMAMURA, McCrary, Kitada and Adachi, as applied to claim 1 above, and further in view of Chen (US Patent. 10,741,147 B1).
Chen was cited in the previous Office Action.
As per claim 3, SHIMAMURA, McCrary, Kitada and Adachi teach the invention according to claim 1 above. SHIMAMURA teaches wherein the processing device executes each of the plurality of processes and monitor the buffer and estimate a load (SHIMAMURA, Fig. 4 100 control device, 160 application parsing part, 32 application programs; Abstract, lines 1-3, A configuration of a control device capable of efficiently operating multiple types of programs in different execution formats on a single control device is provided; [0008] lines 1-4, realizing multiple types of programs (e.g., ladder program, CNC program, robot program, etc.) in different execution formats with one single control device; [0192] lines 1-4. The load state, etc. of the target task can be evaluated (as estimate the load) based on the number of internal commands 40 stored in the internal command buffer 60, and the priority of the target task can be changed based on the evaluation result; [0195] lines 1-4 the load state of the target task can be evaluated by monitoring the number of internal commands stored in the internal command buffer 60 of the shared memory 170; also see Fig. 19, 170 inter command).
In addition, McCrary teaches the monitoring unit is configured to monitor the buffer (McCrary, [0045] lines 2-9, GPU 104 (as monitoring unit, comprising one or more processors, see Fig. 1, 150 command processor) monitors the ring buffers to detect ring buffers available for processing. For example, as a game application executes on CPU 101, commands for operations requiring graphics processing are enqueued by CPU 101 to ring buffers 110 in the form of command buffers, as described in relation to step 305 of process 300. As command buffers are generated and enqueued to ring buffers in accordance with executing applications).
Further, Kitada teaches the processing device executes each of the plurality of processes using a Graphics Processing Unit (GPU) (Kitada, Fig. 4, 407 and 409 execute selected processes on GPU).
SHIMAMURA, McCrary, Kitada and Adachi fail to explicitly teach when estimate a load, it is estimate a load on the GPU.
However, Chen teaches when estimate a load, it is estimate a load on the GPU. (Chen, Fig. 3, 234 GPU, 320 load estimation circuit, 370 Frame buffer; Col 7, lines 32-39, the GPU 234 may include, among other components, an image processing circuit 315, a frame buffer 370 and a load estimation circuit 320. The image processing circuit 315 includes circuit components (e.g., transistors) for performing at least one of asynchronous time warp (ATW) and asynchronous space warp (ASW) frame-rate smoothing techniques on image data received from CPU or system memory of HMD 100; Col 7, lines 41-50, The load estimation circuit 320 is a circuit that generates a load signal 314 representing power estimated for displaying the processed images. The load estimation circuit 320 is coupled 313 to the frame buffer 370 to access the processed image stored in the frame buffer 370. The load estimation circuit 320 performs computation to estimate the power consumption for displaying the processed image by analyzing overall brightness of the pixels in the processed image and/or the dynamic change of pixel values in a current image relative to pixel values in a previous image (as monitor the buffer and estimates a load on the GPU).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of SHIMAMURA, McCrary, Kitada and Adachi with Chen because Chen’s teaching of estimating the load based on monitoring/accessing the data within the buffer of the GPU would have provided SHIMAMURA, McCrary, Kitada and Adachi’s system with the advantage and capability to allow the system to determining the power load of the GPU based on the data stored within the buffer in order to improving the system resource utilization and efficiency.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over SHIMAMURA, McCrary, Kitada, Adachi and Chen, as applied to claim 3 above, and further in view of Sasaki et al. (US Pub. 2013/0235270 A1)
Sasaki was cited in the previous Office Action.
As per claim 4, SHIMAMURA, McCrary, Kitada, Adachi and Chen teach the invention according to claim 3 above. SHIMAMURA, McCrary, Kitada, Adachi and Chen fail to specifically teach wherein the processing device is configured to connect a plurality of images together and synthesize a wide image, and the change unit is configured to change a processing content of a process of combining overlapping areas overlapping between adjacent images.
However, Sasaki further teaches wherein the processing device is configured to connect a plurality of images together and synthesize a wide image (Sasaki, Fig. 2, 200 playback apparatus (as processing device), 221 video synthesizing, 222 synthesis video plane; Fig. 7; Fig. 32A, 3202 and 3201 to 3211; [0017] lines 1-2, FIG. 7 is a view for illustrating synthesis of videos performed by the playback apparatus;)) , and
the change unit is configured to change a processing content of a process of combining overlapping areas overlapping between adjacent images (Sasaki, Fig. 7 see left bottom image has been changed to right image (combination of the three images); also see Fig. 32A; Fig. 35, 221 video synthesizing unit (as change unit); [0058] lines 1-4, FIG. 32A schematically shows the case of simply connecting an image from an additional video 3202 to the left edge of an image from a broadcast video 3201 to generate an image from a video 3211; [0059] lines 1-5, The image of the broadcast video 3201 shows a scene around the soccer ball having the highest degree of importance. The image of the video 3211 shows the scene around the soccer ball having the highest degree of importance, and the entire portion of an advertisement 3206 having the second highest degree of importance; also see [0193] lines 1-4, The video synthesizing unit 221 has a video synthesis function of synthesizing videos in accordance with the synthesis instructions 1-N notified by the video synthesis method setting unit 214 to reproduce a super-wide video).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of SHIMAMURA, McCrary, Kitada, Adachi and Chen with Sasaki because Sasaki’s teaching of image/video synthesizing to reproduce a super-wide video would have provided SHIMAMURA, McCrary, Kitada, Adachi and Chen’s system with the advantage and capability to allow the system to arranging the images (i.e., change processing content) to be displayed on a super-wide screen which improving the user experience and system efficiency.
Claims 7, 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over SHIMAMURA, McCrary, Kitada and Adachi, as applied to claims 1, 5 and 6 respectively above, and further in view of SEO et al. (US Pub. 2018/0033164 A1).
As per claim 7, SHIMAMURA, McCrary, Kitada and Adachi teach the invention according to claim 1 above. SHIMAMURA, McCrary, Kitada and Adachi fail to specifically teach wherein the processing content comprises one or more of a blending scheme, a seam generation interval, or a seam search scheme.
However, SEO teaches wherein the processing content comprises one or more of a blending scheme, a seam generation interval, or a seam search scheme (SEO, [0164] lines 1-4, apply the gradation effect through alpha-blending scheme to adjust transparency. For example, the processor 410 may set the alpha ratio of the alpha-blending scheme to be 40 to 50%).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of SHIMAMURA, McCrary, Kitada and Adachi with SEO because SEO’s teaching of apply the gradation effect through alpha-blending scheme would have provided SHIMAMURA, McCrary, Kitada and Adachi’s system with the advantage and capability to allow the system to adjusting the transparency of the images in order to improving the user experience and system efficiency.
As per claim 8, it is a control method claim of claim 7 above. Therefore, it is rejected for the same reason as claim 7 above.
As per claim 9, it is a non-transitory computer readable storage medium claim of claim 7 above. Therefore, it is rejected for the same reason as claim 7 above.
Response to Arguments
Applicant’s argument with respect to claims 1-9 under 35 U.S.C § 103 rejections have been fully considered but are deemed moot in view of the new grounds of rejection necessitated by Applicant’s amendment.
In the remark applicant’s argue in substance:
(a), Claim 1 is directed to a control apparatus including a monitoring unit and a change unit. The monitoring unit automatically monitors buffers used by concurrently executing processes and estimates the system load based on the amount of data waiting to be processed. The change unit then changes the processing content of a lowest-priority process to decrease its load when the total load exceeds a predetermined threshold. This configuration addresses a specific technical problem-the overloading of a processing device due to excessive concurrent task execution-and provides a technical solution that dynamically redistributes processing workloads in real time.
(b), The Claimed Elements Are Not Merely Generic or Abstract
Claim 1 does not merely invoke a computer as a tool to perform a mental process or mathematical calculation. Rather, the recited "monitoring unit" and "change unit" perform specific control functions tied to the architecture of the processing device… These features are integrated into a practical application that improves the operation of the processing device itself by preventing overload, reducing latency, and improving throughput.
(c), Claim 1 provides a technical improvement in process scheduling and load control that results in better utilization of processor resources.
(d), Even if the claims were viewed as involving an abstract concept, they recite significantly more than the alleged judicial exception, because the claimed combination of features provides a non-conventional and non-routine arrangement of control logic that dynamically adjusts processing content based on buffer monitoring and load estimation. This specific architecture is not a mere generic computer implementation, but a purpose-built control apparatus designed to improve how a processing device allocates resources under high-load conditions.
Examiner respectfully disagreed with Applicant’s argument for the following reasons:
As to point (a), in response to applicant’s argument that “This configuration addresses a specific technical problem-the overloading of a processing device due to excessive concurrent task execution-and provides a technical solution that dynamically redistributes processing workloads in real time”. Examiner respectfully disagreed.
The claim does NOT recites “dynamically redistributes processing workloads in real time”. In fact, the claim, at the best, it recites a generic computer component (i.e., monitoring unit comprising processors, change unit comprising processor) to perform the steps of to monitor the buffer and estimate load based on the data waiting in the buffer and to change a processing content based on the load (i.e., which can be merely performed by mentally, see 101 rejection above). And, the claim does NOT provide any details on how the steps of monitoring and change/adjusting processing content are related to dynamically redistributes processing workloads in real time.
As to point (b), in response to applicant’s argument that “the recited "monitoring unit" and "change unit" perform specific control functions tied to the architecture of the processing device… These features are integrated into a practical application that improves the operation of the processing device itself by preventing overload, reducing latency, and improving throughput”. Examiner respectfully disagreed.
The cited "monitoring unit" and "change unit" are just black box which including generic computer component (i.e., one or more processors) to perform the respective functions. In addition, the claim does not even mention how the monitoring and changing the processing content are related to reducing latency, and improving throughput.
Further, the claim merely requires the “change unit” “configured to” change a processing content of a process, the claim do not require the processing content to be actually changed, merely that they be configured for change.
Therefore, the claim is not integrated into a practical application that improves the operation of the processing device itself by preventing overload, reducing latency, and improving throughput.
As to point (c), please refers to point (a) and (b) above.
As to point (d), please refers to points (a) to (c) above. In addition, MPEP 2106.05(a) discloses that “It is important to note, the judicial exception alone cannot provide the improvement. The improvement can be provided by one or more additional elements. See the discussion of Diamond v. Diehr, 450 U.S. 175, 187 and 191-92, 209 USPQ 1, 10 (1981)) in subsection II, below. In addition, the improvement can be provided by the additional element(s) in combination with the recited judicial exception”. Here, the claim does NOT providing any additional limitations other than the generic computing components/Functions that perform the abstract idea (i.e., monitoring unit and change unit with one or more processors). Therefore, the claim cannot provide the improvement.
For the reasons above, Applicant’s argument has not been found to be persuasive, and therefore the rejections are maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ZUJIA XU/Examiner, Art Unit 2195