Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
RCE filed on 12/09/2025 has been acknowledged. Claims 1-9, are currently pending and have been considered below. Claim 1 and 9 are independent claims. Claim 1 and 9 have been amended. Claim 10 has been cancelled. No claim is added new.
Continued Examination under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/09/2025 has been entered.
Priority
This application is a 371 of PCT/EP2021/083850 filed on 12/01/2021. The application claims the foreign priority EP 20306477.9 filed on 12/01/2020.
Drawings
The drawings filed on 05/31/2023 are objected by the examiner as Fig.1-3 do not contain any legend.
Remarks and Response
Applicant’s arguments filed in the amendments on 12/09/2025 have been fully considered but moot in view of new ground of rejection. The reasons set forth below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-3 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Sanders (US Patent Application No 2018/0121280 A1) and in view of Lentz (US Patent Application Publication No 2021/0396789 A1) and further in view of Carlile (US Patent Application No 2007/0120584 A1).
Regarding Claim 1, Sanders discloses a system on chip comprising:
a processing unit and a memory controller that handles data communication between the processing unit and a memory and having a clock synchronization circuitry based on a locked loop (Sanders, ¶[0032],the dedicates configuration processor does not execute user specified program code. PROC receives the configuration bitstream, load the configuration bitstream into appropriate configuration memory and extract program code for execution. Fig- 4, ¶[0060], synchronizer is capable of synchronizing signal 458 and outputting a synchronized version of signal 458 and 460),
said clock synchronization circuitry synchronizing data transfer between the processing unit and the memory (Sanders, Fig-4, ¶[0071], signal 472, 476 and 478 are provided to control circuitry that generates an interrupt signal responsive to the detection of an error condition on any monitored clock signal),
Sanders does not explicitly teach the following limitation that Lentz teaches:
wherein the system comprises a voltage glitch attack detector configured to monitor a clock synchronization signal generated by the clock synchronization circuitry and (Lentz, ¶[0027], the capture section includes one or more capture flip-flops constructed and arranged to synchronize a bit level signal and capture the count values output from the ripple counter with the system clock domain as part of a synchronization process. ¶[0042], Fig-7 for detecting and preventing glitch attacks on data processing system. ¶[0044], the oscillator clock signal is used to clock a counter for a predetermined amount of time defined by the system clock. ¶[0050]- ¶[0051], the capture section synchronizes the count value into system clock domain);
check whether the monitored clock synchronization signal is a nominal signal or a signal characteristic of a voltage glitch attack (Lentz, ¶[0057], generates an error signal when the at least one count value is different than a reference value by a predetermined margin. ¶[0069], generating a first clock as a function of a supply voltage, generating a count value in response to the first clock and synchronizing the count value into a second clock domain to detect a voltage glitch in the supply voltage);
wherein said clock synchronization circuitry is further utilized as a fault detection mechanism by monitoring the clock synchronization signal generated by the clock synchronization circuitry including on-chip voltage fluctuations toward glitch detection (Lentz, ¶[00424]- ¶[0027] and ¶[0048], a voltage glitch detection processing system comprising an oscillator circuit that generates and outputs a local oscillator clock, which is a function of a supply voltage and a counter clocked by the ring oscillator to generate at least one count value and a capture section that synchronizes the at least one count value into a system clock domain for detecting a voltage glitch in the supply voltage).
Sanders in view of Lentz are analogous art because they are from the “same field of endeavor” and are from the same “problem solving area”. Namely, they pertain to the field of “glitch detection for protecting against fault attacks”. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the invention of Sanders in view of Lentz to include the idea of including a security detection system in a digital core for providing continuous protection against voltage glitch. Ripple counter is configured to receive a direct clock and conventional glitch detector relies on a delay line (Lentz, ¶[0012]- ¶[0013]).
Sanders in view of Lentz does not explicitly teach the following limitation that Carlile teaches:
locked loop (Carlile, ¶[0021], glitch detector and phase detector are operatively configured so that when the glitch detector detects at least one glitch in ref_clk signal, it triggers the phase detector).
Sanders in view of Lentz and Carlile are analogous art because they are from the “same field of endeavor” and are from the same “problem solving area”. Namely, they pertain to the field of “adaptive glitch detection for a system on a chip”. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the invention of Sanders in view of Lentz and Carlile to include the idea of monitoring or analyzing the main clock to detect glitches because if the frequency of the write signal deviates beyond the tight tolerance, data written will be corrupted and data may not be successfully read back (Carlile, ¶[0002]).
Regarding Claim 2, Sanders in view of Lentz and Carlile discloses the system on chip according to claim 1, wherein the voltage glitch attack detector is a software detector executed by the processing unit (Sanders, ¶[0003], a clock glitch may cause numerous problems such as causing a processor to skip the execution of an instruction. Also Lentz, ¶[0042], Fig-7 for detecting and preventing glitch attacks on data processing system).
Regarding Claim 3, Sanders in view of Lentz and Carlile discloses the system on chip according to claim 1, wherein to check whether the monitored clock synchronization signal is a nominal signal or a signal characteristic of a voltage glitch attack, the voltage glitch attack detector is configured to compare the monitored clock synchronization signal to a threshold (Sanders, ¶[0066], comparator 435 is capable of comparing signal 464 from counter 415 with signal 470 from control circuitry 310. Comparator 435 is capable of performing the comparison to determine whether clock signal is free running or stuck at 0 or 1. Also Lentz, ¶[0057], generates an error signal when the at least one count value is different than a reference value by a predetermined margin. ¶[0069], generating a first clock as a function of a supply voltage, generating a count value in response to the first clock and synchronizing the count value into a second clock domain to detect a voltage glitch in the supply voltage).
Regarding Claim 9, Sanders discloses a method for voltage glitch attack detection in a system on chip comprising:
a processing unit and a memory controller that handles data communication between the processing unit and a memory and having a clock synchronization circuitry based on a locked loop (Sanders, ¶[0032],the dedicates configuration processor does not execute user specified program code. PROC receives the configuration bitstream, load the configuration bitstream into appropriate configuration memory and extract program code for execution. Fig- 4, ¶[0060], synchronizer is capable of synchronizing signal 458 and outputting a synchronized version of signal 458 and 460);
said clock synchronization circuitry synchronizing data transfer between the processing unit (Sanders, Fig-4, ¶[0071], signal 472, 476 and 478 are provided to control circuitry that generates an interrupt signal responsive to the detection of an error condition on any monitored clock signal);
Sanders does not explicitly teach the following limitation that Lentz teaches:
wherein the method further comprises the steps of monitoring a clock synchronization signal generated by the clock synchronization circuitry and (Lentz, ¶[0027], the capture section includes one or more capture flip-flops constructed and arranged to synchronize a bit level signal and capture the count values output from the ripple counter with the system clock domain as part of a synchronization process. ¶[0042], Fig-7 for detecting and preventing glitch attacks on data processing system. ¶[0044], the oscillator clock signal is used to clock a counter for a predetermined amount of time defined by the system clock. ¶[0050]- ¶[0051], the capture section synchronizes the count value into system clock domain);
checking whether the monitored clock synchronization signal is a nominal signal or a signal characteristic of a voltage glitch attack (Lentz, ¶[0057], generates an error signal when the at least one count value is different than a reference value by a predetermined margin. ¶[0069], generating a first clock as a function of a supply voltage, generating a count value in response to the first clock and synchronizing the count value into a second clock domain to detect a voltage glitch in the supply voltage);
wherein said clock synchronization circuitry is further utilized as a fault detection mechanism by monitoring the clock synchronization signal generated by the clock synchronization circuitry including on-chip voltage fluctuations toward glitch detection (Lentz, ¶[00424]- ¶[0027] and ¶[0048], a voltage glitch detection processing system comprising an oscillator circuit that generates and outputs a local oscillator clock, which is a function of a supply voltage and a counter clocked by the ring oscillator to generate at least one count value and a capture section that synchronizes the at least one count value into a system clock domain for detecting a voltage glitch in the supply voltage).
Sanders in view of Lentz are analogous art because they are from the “same field of endeavor” and are from the same “problem solving area”. Namely, they pertain to the field of “glitch detection for protecting against fault attacks”. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the invention of Sanders in view of Lentz to include the idea of including a security detection system in a digital core for providing continuous protection against voltage glitch. Ripple counter is configured to receive a direct clock and conventional glitch detector relies on a delay line (Lentz, ¶[0012]- ¶[0013]).
Sanders in view of Lentz does not explicitly teach the following limitation that Carlile teaches:
locked loop (Carlile, ¶[0021], glitch detector and phase detector are operatively configured so that when the glitch detector detects at least one glitch in ref_clk signal, it triggers the phase detector).
Sanders in view of Lentz and Carlile are analogous art because they are from the “same field of endeavor” and are from the same “problem solving area”. Namely, they pertain to the field of “adaptive glitch detection for a system on a chip”. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the invention of Sanders in view of Lentz and Carlile to include the idea of monitoring or analyzing the main clock to detect glitches because if the frequency of the write signal deviates beyond the tight tolerance, data written will be corrupted and data may not be successfully read back (Carlile, ¶[0002]).
Claim 4-8 are rejected under 35 U.S.C. 103 as being unpatentable over Sanders (US Patent Application No 2018/0121280 A1) in view of Lentz (US Patent Application Publication No 2021/0396789 A1) and further in view of Carlile (US Patent Application No 2007/0120584 A1) and further in view of Goh (US Patent Application No 2020/0081062 A1).
Regarding Claim 4, Sanders in view of Lentz and Carlile does not disclose the following limitation that Goh teaches:
system on chip according to claim 3, wherein the threshold is periodically readjusted to take into account temperature variations (Goh, ¶[0003], due to temperature, a SOC may operate improperly. ¶[0016], if the delay of the delay chain begins at a low value while operating temperature of the SOC is high, is the temperature of the SOC reduces , then the delay of the delay chain may become less than ideal, making it possible that the glitch detector fails to detect some glitches).
Sanders in view of Lentz and Carlile and Goh are analogous art because they are from the “same field of endeavor” and are from the same “problem solving area”. Namely, they pertain to the field of “adaptive glitch detection for a system on a chip”. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the invention of Sanders in view of Lentz and Carlile and Goh to include the idea of monitoring or analyzing the main clock to detect glitches because temperature, age and other operating condition may cause improper operation of SOC and cause glitch (Goh, ¶[0003]).
Regarding Claim 5, Sanders in view of Lentz and Carlile and Goh discloses the system on chip according to claim 4, wherein the clock synchronization circuitry is a delay locked loop (Lentz, ¶[0013], a delay line can be used to determine whether a variation exits. ¶[0019], the voltage glitch detection processing system 100 requires fewer digital logic cells forming the delay line).
Regarding Claim 6, Sanders in view of Lentz and Carlile and Goh discloses the system on chip according to claim 5, wherein the clock synchronization signal is a delay applied to a clock by the delay locked loop (Lentz, ¶[0013], a delay line can be used to determine whether a variation exits. ¶[0019], the voltage glitch detection processing system 100 requires fewer digital logic cells forming the delay line).
Regarding Claim 7, Sanders in view of Lentz and Carlile and Goh discloses the system on chip according to claim 4, wherein the clock synchronization circuitry is a phase locked loop (Carlile, ¶[0016], PLL circuit is a novel frequency synthesizer capable of synthesizing an output signal. ¶[0017], PLL includes frequency synthesizer and glitch detector).
Regarding Claim 8, Sanders in view of Lentz and Carlile and Goh discloses the system on chip according to claim 7, wherein the clock synchronization signal is a voltage applied to a voltage-controlled oscillator of the phase locked loop (Carlile, ¶[0017], PLL circuit will have oscillator).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure (see PTO-Form 892).
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/WASIKA NIPA/ Primary Examiner, Art Unit 2433