DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed July 16, 2026 has been entered. Claims 1-7 and 11-14 remain pending in the application. Applicant’s amendments to the Claims have overcome each and every objections previously set forth in the Non-Final Office Action mailed January 30, 2026.
Claim Objections
Claims 4, 6, and 13 are objected to because of the following informalities:
In claim 4, line 4, “model plurality of” should read --model of the plurality of--.
In claim 6, line 20, “neurons model” should read --neuron models--.
In claim 13, line 1, “claim 9” should read --claim 12--.
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-7 and 11-14 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more.
Under the Step 1 of the Section 101 analysis, Claims 1-6 and 11-14 are drawn to a device which is within the four statutory categories (i.e. a machine), and Claim 7 is drawn to a method which is within the four statutory categories (i.e., a process),.
Since the claims are directed toward statutory categories, it must be determined if the claims are directed towards a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea). Based on consideration of all of the relevant factors with respect to the claim as a whole, claims 1-7 and 11-14 are determined to be directed to an abstract idea. The rationale for this determination is explained below:
Regarding Claims 1 and 7:
Claims 1 and 7 are drawn to an abstract idea without significantly more. The claims recite “a plurality of time-scheme spiking neuron models provided in a same layer, each of the plurality of time-scheme spiking neuron models outputting a signal when an internal state quantity that evolves over time in accordance with a signal input clock time becomes a threshold value or more; and a delay unit configured to output a signal obtained by delaying, by a time that is set as a delay amount common to the plurality of time-scheme spiking neuron models, a spike clock time that is represented by the output signal of each of the time-scheme spiking neuron models as a relative clock time with respect to a reference clock time.”
Under the Step 2A Prong One, the limitations, as underlined above, are processes that, under its broadest reasonable interpretation, cover Mental Processes such as concepts performed in the human mind (including an observation, evaluation, judgment, opinion). For example, but for the “time-scheme spiking neuron models”, “signal”, “unit”, and “spike clock time” language, the underlined limitations in the context of this claim encompass the human activity or mental processes. The series of steps belong to a typical observation, evaluation, judgment, or opinion, because data or information including signal, state, time, and value is processed just as human or human mind does.
Under the Step 2A Prong Two, this judicial exception is not integrated into a practical application. In particular, the claim only recites additional elements – “A neural network device comprising:”, “An information processing method comprising:”, “time-scheme spiking neuron models”, “signal”, “unit”, and “spike clock time”. The additional elements are recited at a high-level of generality (i.e., performing generic functions of an interaction) such that it amounts no more than mere instructions to apply the exception using a generic computer component, merely implementing an abstract idea on a computer, or merely using a computer as a tool to perform an abstract idea. Additionally, regarding the specification and claims, there is no improvement in the functioning of a computer or an improvement to other technology or technical field present, there is no applying or using the judicial exception to effect a particular treatment or prophylaxis for a disease or medical condition present, there is no implementing the judicial exception with or using the judicial exception in conjunction with a particular machine or manufacture that is integral to the claim present, there is no effecting a transformation or reduction of a particular article to a different state or thing present, and there is no applying or using the judicial exception in some other meaningful way beyond generally linking the use of the judicial exception to a particular technological environment present such that the claim as a whole is more than a drafting effort designed to monopolize the exception. Accordingly, these additional elements, individually or in combination, do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claims are directed to an abstract idea.
Under the Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements in the process amounts to no more than mere instructions to apply the exception using generic computer components. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. The claims are not patent eligible.
Regarding Claim 6:
Claim 6 is drawn to an abstract idea without significantly more. The claims recite “base network generating circuitry configured to generate a neural network, the neural network comprising a plurality of time-scheme spiking neuron models and a delay unit, the plurality of time-scheme spiking neuron models being provided in a same layer, each of the plurality of time-scheme spiking neuron models outputting a signal when an internal state quantity that evolves over time in accordance with a signal input clock time becomes a threshold value or more, the delay unit is configured to output a signal obtained by delaying, by a time that is set as a delay amount common to the plurality of time-scheme spiking neuron models, a spike clock time that is represented by the output signal of each of the plurality of time-scheme spiking neuron models as a relative clock time with respect to a reference clock time; weight setting circuitry configured to set a weight of an input signal to the plurality of time-scheme spiking neuron models to a weight based on an equation in which, when an input clock time of the input signal is a clock time in which a sign of a numerical value represented by the input signal is reversed, an output clock time of an output signal of the delay unit becomes a clock time in which a sign of a numerical value represented by the output signal is reversed; and delay setting unit configured to set the set time of the delay unit to a time based on an equation in which, when an input clock time of an input signal to the plurality of time-scheme spiking neuron models is a clock time in which a sign of a numerical value represented by the input signal is reversed, an output clock time of an output signal of the delay unit becomes a clock time in which a sign of a numerical value represented by the output signal is reversed.”
Under the Step 2A Prong One, the limitations, as underlined above, are processes that, under its broadest reasonable interpretation, cover Mental Processes such as concepts performed in the human mind (including an observation, evaluation, judgment, opinion). For example, but for the “base network generating circuitry”, “neural network”, “time-scheme spiking neuron model”, “signal”, “unit”, “spike clock time”, “weight setting circuitry”, and “delay setting unit” language, the underlined limitations in the context of this claim encompass the human activity or mental processes. The series of steps belong to a typical observation, evaluation, judgment, or opinion, because data or information including signal, state, time, and value is processed just as human or human mind does.
Under the Step 2A Prong Two, this judicial exception is not integrated into a practical application. In particular, the claim only recites additional elements – “A generation device comprising:”, “base network generating circuitry”, “neural network”, “time-scheme spiking neuron model”, “signal”, “unit”, “spike clock time”, “weight setting circuitry”, and “delay setting unit”. The additional elements are recited at a high-level of generality (i.e., performing generic functions of an interaction) such that it amounts no more than mere instructions to apply the exception using a generic computer component, merely implementing an abstract idea on a computer, or merely using a computer as a tool to perform an abstract idea. Additionally, regarding the specification and claims, there is no improvement in the functioning of a computer or an improvement to other technology or technical field present, there is no applying or using the judicial exception to effect a particular treatment or prophylaxis for a disease or medical condition present, there is no implementing the judicial exception with or using the judicial exception in conjunction with a particular machine or manufacture that is integral to the claim present, there is no effecting a transformation or reduction of a particular article to a different state or thing present, and there is no applying or using the judicial exception in some other meaningful way beyond generally linking the use of the judicial exception to a particular technological environment present such that the claim as a whole is more than a drafting effort designed to monopolize the exception. Accordingly, these additional elements, individually or in combination, do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claims are directed to an abstract idea.
Under the Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements in the process amounts to no more than mere instructions to apply the exception using generic computer components. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. The claims are not patent eligible.
Regarding Claims 2-5 and 11-14:
Dependent claims 2-5 and 11-14 include additional limitations, for example, “signal”, “time-scheme spiking neuron models”, and “delay unit” (Claim 2); “time-scheme ramp function circuitry”, “signal”, and “delay unit” (Claim 3); “set spike supplying circuitry”, “signal”, and “time-scheme spiking neuron models” (Claim 4); “time-scheme spiking neuron models”, “application specific integrated circuit (ASIC)”, and “field- programmable gate array (FPGA)” (Claim 5); “layer”, “time-scheme spiking neuron models”, and “delay unit” (Claim 11); “time-scheme spiking neuron models”, “synaptic circuit”, “capacitor”, “threshold power supply”, and “comparator” (Claim 12); “synaptic circuit”, “switching element”, and “variable capacitor” (Claim 13); and “delay unit” and “delay circuit” (Claim 14), but none of these limitations are deemed significantly more than the abstract idea because, as stated above, they require no more than generic computer structures or signals to be executed, and do not recite any Improvements to the functioning of a computer, or Improvements to any other technology or technical field.
Thus, taken alone, the additional elements do not amount to significantly more than the above-identified judicial exception (the abstract idea). Furthermore, looking at the limitations as an ordered combination adds nothing that is not already present when looking at the elements taken individually. There is no indication that the combination of elements improves the functioning of a computer or improves any other technology, and their collective functions merely provide conventional computer implementation or implementing the judicial exception on a generic computer.
Therefore, whether taken individually or as an ordered combination, claims 2-5 and 11-14 are nonetheless rejected under 35 U.S.C. 101 as being directed to non-statutory subject matter.
Claim Rejections - 35 USC § 103
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, 12, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sinyavskiy (US 20140032458 A1) in view of Onishi (JP 2010146514 A; already of record in IDS).
Regarding Claims 1 and 7, Sinyavskiy teaches A neural network device comprising (Sinyavskiy: Abstract): An information processing method comprising (Sinyavskiy: Abstract):
a plurality of time-scheme spiking neuron models provided in a same layer, each of the plurality of time-scheme spiking neuron models outputting a signal when an internal state quantity that evolves over time in accordance with a signal input clock time becomes a threshold value or more (Sinyavskiy: Paragraph(s) 0102, 0161, 0165, 0229, 0244, 0113, 0115 teach(es) facilitating learning spiking neuron networks by, inter alia, implementing efficient synaptic updates; The panel in FIG. 7 illustrates event sequence, comprising for example, neuron inputs (such as feed-forward input and/or a reinforcement spikes). In one implementation, (not shown) the event clock and the EDCC components computation clock may be synchronized and selected to be updated at regular network update intervals, for example 1 ms intervals; yd(t)=Σt k δ(t−tk d) denotes the teaching spike pattern, corresponding to the desired (or reference) signal that may be part of external signal of FIG. 4, where t_k^d denotes the times when the spikes of the reference signal are received by the neuron); and a delay unit configured to output a signal obtained by delaying, by a time …, a spike clock time that is represented by the output signal of each of the time-scheme spiking neuron models as a relative clock time with respect to a reference clock time (Sinyavskiy: Paragraph(s) 0061, 0165-0166, 0108-0112, 0229 teach(es) the update may be delayed until a next regular time interval occurring subsequent to occurrence of the data item of the one or more data items; The panel illustrates delayed synchronous on-demand updates, where the updates may be synchronized to a clock (e.g., local neuron clock or global network clock) and performed at the next following clock instance).
However, Sinyavskiy does not explicitly teach …by a time that is set as a delay amount common to the plurality of time-scheme spiking neuron models.
Onishi from same or similar field of endeavor teaches a delay unit configured to output a signal obtained by delaying, by a time that is set as a delay amount common to the plurality of time-scheme spiking neuron models (Onishi: Page 9, lines 12-13; 11/21-23; 14/6-11 teach(es) The spike Pi generated by the spike generator 15 is output as a spike Oi to another 12 neuron circuit after the propagation delay time set by the delay unit has elapsed).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Sinyavskiy to incorporate the teachings of Onishi for a delay unit configured to output a signal obtained by delaying, by a time that is set as a delay amount common to the plurality of time-scheme spiking neuron models.
There is motivation to combine Onishi into Sinyavskiy because Onishi’s teachings of delay unit would facilitate to executing the spiking neuron model (Onishi: Paragraph(s) 9/12-13; 11/21-23; 14/6-11).
Regarding Claim 6, the combination of Sinyavskiy and Onishi teaches A generation device comprising: base network generating circuitry configured to generate a neural network, the neural network comprising a plurality of time-scheme spiking neuron models and a delay unit, the plurality of time-scheme spiking neuron models being provided in a same layer, each of the plurality of time-scheme spiking neuron models outputting a signal when an internal state quantity that evolves over time in accordance with a signal input clock time becomes a threshold value or more, the delay unit is configured to output a signal obtained by delaying, by a time that is set as a delay amount common to the plurality of time-scheme spiking neuron models, a spike clock time that is represented by the output signal of each of the plurality of time-scheme spiking neuron models as a relative clock time with respect to a reference clock time, as stated above with respect to claims 1 and 7; and Sinyavskiy further teaches weight setting circuitry configured to set a weight of an input signal to the plurality of time-scheme spiking neuron models to a weight based on an equation in which, … (Sinyavskiy: Paragraph(s) 0052, 0108, 0113, 0134 teach(es) individual ones of the plurality of parameters may comprise a weight. The weight may be configured to modify a state of the node based on an occurrence of a data item of the one or more data items within the decay time scale); and delay setting unit configured to set the set time of the delay unit to a time based on an equation in which, … (Sinyavskiy: Paragraph(s) 0061, 0165-0166, 0108-0112, 0229 teach(es) the update may be delayed until a next regular time interval occurring subsequent to occurrence of the data item of the one or more data items; The panel illustrates delayed synchronous on-demand updates, where the updates may be synchronized to a clock (e.g., local neuron clock or global network clock) and performed at the next following clock instance).
However, the combination of Sinyavskiy and Onishi does not explicitly teach when an input clock time of the input signal is a clock time in which a sign of a numerical value represented by the input signal is reversed, an output clock time of an output signal of the delay unit becomes a clock time in which a sign of a numerical value represented by the output signal is reversed.
Onishi from same or similar field of endeavor teaches when an input clock time of the input signal is a clock time in which a sign of a numerical value represented by the input signal is reversed, an output clock time of an output signal of the delay unit becomes a clock time in which a sign of a numerical value represented by the output signal is reversed (Onishi: Page 3, lines 4-28; 7/39-45; 12/14-17 teach(es) When a spike pulse is input from an external or other neuron, a unimodal voltage change appears at the junction (synapse) between neurons. This is called a post-synaptic potential (hereinafter abbreviated as “PSP”). The direction of the voltage change of the PSP is positive or negative according to the sign (positive or negative) of the synaptic connection; a method of applying a reverse polarity pulse is called a “bipolar switching method (bipolar operation)”).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of the combination of Sinyavskiy and Onishi to incorporate the teachings of Onishi for when an input clock time of the input signal is a clock time in which a sign of a numerical value represented by the input signal is reversed, an output clock time of an output signal of the delay unit becomes a clock time in which a sign of a numerical value represented by the output signal is reversed.
There is motivation to combine Onishi into the combination of Sinyavskiy and Onishi because Onishi’s teachings of bipolar switching method would facilitate the spiking neuron model (Onishi: Paragraph(s) 3/4-28; 7/39-45; 12/14-17).
Regarding Claim 2, the combination of Sinyavskiy and Onishi teaches all the limitations of claim 1 above; and Sinyavskiy further teaches wherein a weight of an input signal to a time-scheme spiking neuron model of the plurality of time-scheme spiking neuron models is set to a weight based on an equation in which, … (Sinyavskiy: Paragraph(s) 0052, 0108, 0113, 0134 teach(es) individual ones of the plurality of parameters may comprise a weight. The weight may be configured to modify a state of the node based on an occurrence of a data item of the one or more data items within the decay time scale).
However, the combination of Sinyavskiy and Onishi does not explicitly teach when an input clock time of the input signal is a clock time in which a sign of a numerical value represented by the input signal is reversed, an output clock time of an output signal of the delay unit becomes a clock time in which a sign of a numerical value represented by the output signal is reversed.
Onishi from same or similar field of endeavor teaches when an input clock time of the input signal is a clock time in which a sign of a numerical value represented by the input signal is reversed, an output clock time of an output signal of the delay unit becomes a clock time in which a sign of a numerical value represented by the output signal is reversed (Onishi: 3/4-28; 7/39-45; 12/14-17 teach(es) When a spike pulse is input from an external or other neuron, a unimodal voltage change appears at the junction (synapse) between neurons. This is called a post-synaptic potential (hereinafter abbreviated as “PSP”). The direction of the voltage change of the PSP is positive or negative according to the sign (positive or negative) of the synaptic connection; a method of applying a reverse polarity pulse is called a “bipolar switching method (bipolar operation)”).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of the combination of Sinyavskiy and Onishi to incorporate the teachings of Onishi for when an input clock time of the input signal is a clock time in which a sign of a numerical value represented by the input signal is reversed, an output clock time of an output signal of the delay unit becomes a clock time in which a sign of a numerical value represented by the output signal is reversed.
There is motivation to combine Onishi into the combination of Sinyavskiy and Onishi because Onishi’s teachings of bipolar switching method would facilitate the spiking neuron model (Onishi: 3/4-28; 7/39-45; 12/14-17).
Regarding Claim 3, the combination of Sinyavskiy and Onishi teaches all the limitations of claim 2 above; and Sinyavskiy further teaches further comprising: time-scheme ramp function circuitry configured to output a signal at an earlier of an output clock time of the output signal of the delay unit or the reference clock time (Sinyavskiy: Paragraph(s) 0061, 0165-0166, 0108-0112, 0229 teach(es) the update may be delayed until a next regular time interval occurring subsequent to occurrence of the data item of the one or more data items; The panel illustrates delayed synchronous on-demand updates, where the updates may be synchronized to a clock (e.g., local neuron clock or global network clock) and performed at the next following clock instance).
Regarding Claim 4, the combination of Sinyavskiy and Onishi teaches all the limitations of claim 1 above; and Sinyavskiy further teaches further comprising: set spike supplying circuitry that outputs a signal to a time-scheme spiking neuron model of the plurality of time-scheme spiking neuron models at a clock time that does not depend on an input signal to the time-scheme spiking neuron model (Sinyavskiy: Paragraph(s) 0102, 0161, 0165, 0229, 0244, 0113, 0115, as stated above with respect to claim 1).
Regarding Claim 5, the combination of Sinyavskiy and Onishi teaches all the limitations of claim 1 above; and Sinyavskiy further teaches wherein at least either one of the plurality of the time-scheme spiking neuron models or the delay unit is configured using an application specific integrated circuit (ASIC) or a field-programmable gate array (FPGA) (Sinyavskiy: Paragraph(s) 0094-0095, 0266 teach(es) integrated circuits may include field programmable gate arrays (e.g., FPGAs), a programmable logic device (PLD), reconfigurable computer fabrics (RCFs), application-specific integrated circuits (ASICs), and/or other types of integrated circuits).
Regarding Claim 12, the combination of Sinyavskiy and Onishi teaches all the limitations of claim 1 above; however the combination does not explicitly teach wherein a time-scheme spiking neuron model of the plurality of time-scheme spiking neuron models comprises a synaptic circuit, a capacitor, a threshold power supply, and a comparator.
Onishi further teaches wherein a time-scheme spiking neuron model of the plurality of time-scheme spiking neuron models comprises a synaptic circuit, a capacitor, a threshold power supply, and a comparator (Onishi: 7/39-45; 8/16-40; 9/5-10).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of the combination of Sinyavskiy and Onishi to incorporate the teachings of Onishi for wherein a time-scheme spiking neuron model of the plurality of time-scheme spiking neuron models comprises a synaptic circuit, a capacitor, a threshold power supply, and a comparator.
There is motivation to combine Onishi into the combination of Sinyavskiy and Onishi because Onishi’s teachings of synaptic circuit, capacitor, threshold power supply, and comparator would facilitate executing the spiking neuron model (Onishi: 7/39-45; 8/16-40; 9/5-10).
Regarding Claim 14, the combination of Sinyavskiy and Onishi teaches all the limitations of claim 1 above; however the combination does not explicitly teach wherein the delay unit comprises a delay circuit.
Onishi further teaches wherein the delay unit comprises a delay circuit (Onishi: 14/6-24 teach(es) delay inversion circuit).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of the combination of Sinyavskiy and Onishi to incorporate the teachings of Onishi for wherein the delay unit comprises a delay circuit.
There is motivation to combine Onishi into the combination of Sinyavskiy and Onishi because Onishi’s teachings of delay inversion circuit would facilitate executing the spiking neuron model (Onishi: 14/6-24).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sinyavskiy (US 20140032458 A1) in view of Onishi (JP 2010146514 A; already of record in IDS), as applied to claim 1 above, and in further view of Cleland (WO 2020210673 A1).
Regarding Claim 11, the combination of Sinyavskiy and Onishi teaches all the limitations of claim 1 above; however the combination does not explicitly teach comprising: a first layer comprising the plurality of time-scheme spiking neuron models; and a second layer comprising the delay unit.
Cleland from same or similar field of endeavor teaches comprising: a first layer comprising the plurality of time-scheme spiking neuron models; and a second layer comprising the delay unit (Cleland: Page 77, lines 5-15; 28/16-27; 42/22-26 teach(es) The seven layers consisted of an input layer of 72 units, followed by five hidden layers of 720 units each and an output layer of 72 units; to delay principal neuron spike firing according to the inhibitory synaptic weight).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of the combination of Sinyavskiy and Onishi to incorporate the teachings of Cleland for comprising: a first layer comprising the plurality of time-scheme spiking neuron models; and a second layer comprising the delay unit.
There is motivation to combine Cleland into the combination of Sinyavskiy and Onishi because Cleland’s teachings of layers of autoencoder and spike propagation delays would facilitate executing the spiking neuron model (Cleland: Abstract; 77/ 5-15; 28/16-27).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sinyavskiy (US 20140032458 A1) in view of Onishi (JP 2010146514 A; already of record in IDS), as applied to claim 12 above, and in further view of Jang (US 20210125045 A1).
Regarding Claim 13, the combination of Sinyavskiy and Onishi teaches all the limitations of claim 12 above; however the combination does not explicitly teach wherein the synaptic circuit comprises a switching element and a variable resistor.
Jang from same or similar field of endeavor teaches wherein the synaptic circuit comprises a switching element and a variable resistor (Jang: Paragraph(s) 0144 teach(es) The first feed-back signals Sb1 divaricated from the output signals Sout of the comparator may be provided to the second electrode of the variable resistor through the first feed-back line and the second node N2, and may initialize the variable resistor. The output terminal of the comparator may be electrically connected with a gate electrode of the switching transistor of the synapse through the second feed-back line and/or the selection line SL2).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of the combination of Sinyavskiy and Onishi to incorporate the teachings of Jang for wherein the synaptic circuit comprises a switching element and a variable resistor.
There is motivation to combine Jang into the combination of Sinyavskiy and Onishi because Jang’s teachings of variable resistor and switching transistor would facilitate executing the spiking neuron model (Jang: Paragraph(s) 0144).
Response to Arguments
Applicant's arguments filed July 16, 2026 have been fully considered but they are not persuasive.
Regarding applicant’s argument under Claim Rejections - 35 USC § 101 that “the claims do not recite a mental process within the context of 35 U.S.C. § 101 analysis because they contain features that cannot be practically performed in the human mind. (See M.P.E.P. § 2106.04(a)(2)(III)(A)). For example, the features of claim 1 include "a plurality of time-scheme spiking neuron models provided in a same layer." For example, the features of claim 6 include "base network generating circuitry configured to generate a neural network, the neural network comprising a plurality of time-scheme spiking neuron models and delay unit",” examiner respectfully argues that the additional elements are recited in the claims without any technical details, neither providing any improvements in the functioning of computer or other technology or technical field, nor integrating the abstract idea into a practical application. It is recommend for the applicant to amend the claims with more technical details and technical contexts of the additional elements.
Regarding applicant’s argument under Claim Rejections - 35 USC § 102 that “Accordingly, Sinyavskiy discloses that the plurality of M-input connections 414 are set
to have synaptic delay of the parameter 412. Sinyavskiy, however, does not disclose "a delay unit configured to output a signal obtained by delaying, by a time that is set as a delay amount common to the plurality of time-scheme spiking neuron models," as recited by claim 1,” examiner respectfully argues that the features are taught by the combination of Sinyavskiy and Onishi, as stated above in the 103 rejections.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CLAY LEE whose telephone number is (571)272-3309. The examiner can normally be reached Monday-Friday 8-5pm EST.
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/CLAY C LEE/ Primary Examiner, Art Unit 3699
Prosecution Insights