DETAILED ACTION
Claim Status
This is first office action on the merits in response to the application filed on 6/1/2023.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-7 are currently pending and have been examined.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 6/1/2023 is(are) in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 1-5 are objected to because of the following informalities:
In claim 1, lines 6-7, “time-scheme spiking neuron model unit” should read --time-scheme spiking neuron model--.
Claim 5 is objected because of capital letters within body of claims, as in “Application Specific Integrated Circuit” and “Field-Programmable Gate Array”. Capital letter should only be used for first letter of claim or abbreviation.
Claims 2-5 are further objected due to their dependency.
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-7 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more.
Under the Step 1 of the Section 101 analysis, Claims 1-6 are drawn to a device which is within the four statutory categories (i.e. a machine), and Claim 7 is drawn to a method which is within the four statutory categories (i.e., a process),.
Since the claims are directed toward statutory categories, it must be determined if the claims are directed towards a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea). Based on consideration of all of the relevant factors with respect to the claim as a whole, claims 1-7 are determined to be directed to an abstract idea. The rationale for this determination is explained below:
Regarding Claims 1 and 7:
Claims 1 and 7 are drawn to an abstract idea without significantly more. The claims recite “a time-scheme spiking neuron model that outputs a signal when an internal state quantity that evolves over time in accordance with a signal input clock time, becomes a threshold value or more; and a delay unit that outputs a signal obtained by changing, by a set time, a spike clock time that is represented by the output signal of the time-scheme spiking neuron model unit as a relative clock time with respect to a reference clock time.”
Under the Step 2A Prong One, the limitations, as underlined above, are processes that, under its broadest reasonable interpretation, cover Mental Processes such as concepts performed in the human mind (including an observation, evaluation, judgment, opinion). For example, but for the “time-scheme spiking neuron model”, “signal”, “unit”, and “spike clock time” language, the underlined limitations in the context of this claim encompass the human activity or mental processes. The series of steps belong to a typical observation, evaluation, judgment, or opinion, because data or information including signal, state, time, and value is processed just as human or human mind does.
Under the Step 2A Prong Two, this judicial exception is not integrated into a practical application. In particular, the claim only recites additional elements – “A neural network device comprising:”, “An information processing method comprising:”, “time-scheme spiking neuron model”, “signal”, “unit”, and “spike clock time”. The additional elements are recited at a high-level of generality (i.e., performing generic functions of an interaction) such that it amounts no more than mere instructions to apply the exception using a generic computer component, merely implementing an abstract idea on a computer, or merely using a computer as a tool to perform an abstract idea. Additionally, regarding the specification and claims, there is no improvement in the functioning of a computer or an improvement to other technology or technical field present, there is no applying or using the judicial exception to effect a particular treatment or prophylaxis for a disease or medical condition present, there is no implementing the judicial exception with or using the judicial exception in conjunction with a particular machine or manufacture that is integral to the claim present, there is no effecting a transformation or reduction of a particular article to a different state or thing present, and there is no applying or using the judicial exception in some other meaningful way beyond generally linking the use of the judicial exception to a particular technological environment present such that the claim as a whole is more than a drafting effort designed to monopolize the exception. Accordingly, these additional elements, individually or in combination, do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claims are directed to an abstract idea.
Under the Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements in the process amounts to no more than mere instructions to apply the exception using generic computer components. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. The claims are not patent eligible.
Regarding Claim 6:
Claim 6 is drawn to an abstract idea without significantly more. The claims recite “a base network generating unit that generates a neural network, the neural network including a time-scheme spiking neuron model that outputs a signal when an internal state quantity that evolves over time in accordance with a signal input clock time, becomes a threshold value or more, and a delay unit that outputs a signal obtained by changing, by a set time, a spike clock time that is represented by the output signal of the time-scheme spiking neuron model as a relative clock time with respect to a reference clock time; a weight setting unit that sets a weight of an input signal to the time-scheme spiking neuron model to a weight based on an equation in which, when an input clock time of the input signal is a clock time in which a sign of a numerical value represented by the input signal is reversed, an output clock time of an output signal of the delay unit becomes a clock time in which a sign of a numerical value represented by the output signal is reversed; and a delay setting unit that sets the set time of the delay unit to a time based on an equation in which, when an input clock time of an input signal to the time-scheme spiking neuron model is a clock time in which a sign of a numerical value represented by the input signal is reversed, an output clock time of an output signal of the delay unit becomes a clock time in which a sign of a numerical value represented by the output signal is reversed.”
Under the Step 2A Prong One, the limitations, as underlined above, are processes that, under its broadest reasonable interpretation, cover Mental Processes such as concepts performed in the human mind (including an observation, evaluation, judgment, opinion). For example, but for the “base network generating unit”, “neural network”, “time-scheme spiking neuron model”, “signal”, “unit”, “spike clock time”, “weight setting unit”, and “delay setting unit” language, the underlined limitations in the context of this claim encompass the human activity or mental processes. The series of steps belong to a typical observation, evaluation, judgment, or opinion, because data or information including signal, state, time, and value is processed just as human or human mind does.
Under the Step 2A Prong Two, this judicial exception is not integrated into a practical application. In particular, the claim only recites additional elements – “A generation device comprising:”, “base network generating unit”, “neural network”, “time-scheme spiking neuron model”, “signal”, “unit”, “spike clock time”, “weight setting unit”, and “delay setting unit”. The additional elements are recited at a high-level of generality (i.e., performing generic functions of an interaction) such that it amounts no more than mere instructions to apply the exception using a generic computer component, merely implementing an abstract idea on a computer, or merely using a computer as a tool to perform an abstract idea. Additionally, regarding the specification and claims, there is no improvement in the functioning of a computer or an improvement to other technology or technical field present, there is no applying or using the judicial exception to effect a particular treatment or prophylaxis for a disease or medical condition present, there is no implementing the judicial exception with or using the judicial exception in conjunction with a particular machine or manufacture that is integral to the claim present, there is no effecting a transformation or reduction of a particular article to a different state or thing present, and there is no applying or using the judicial exception in some other meaningful way beyond generally linking the use of the judicial exception to a particular technological environment present such that the claim as a whole is more than a drafting effort designed to monopolize the exception. Accordingly, these additional elements, individually or in combination, do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claims are directed to an abstract idea.
Under the Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements in the process amounts to no more than mere instructions to apply the exception using generic computer components. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. The claims are not patent eligible.
Regarding Claims 2-5:
Dependent claims 2-5 include additional limitations, for example, “signal”, “time-scheme spiking neuron model”, and “delay unit” (Claim 2); “time-scheme spiking neuron model”, “signal”, and “delay unit” (Claim 3); “set spike supplying unit”, “signal”, and “time-scheme spiking neuron model” (Claim 4); and “time-scheme spiking neuron model”, “Application Specific Integrated Circuit (ASIC)”, and “Field- Programmable Gate Array (FPGA)” (Claim 5);, but none of these limitations are deemed significantly more than the abstract idea because, as stated above, they require no more than generic computer structures or signals to be executed, and do not recite any Improvements to the functioning of a computer, or Improvements to any other technology or technical field.
Thus, taken alone, the additional elements do not amount to significantly more than the above-identified judicial exception (the abstract idea). Furthermore, looking at the limitations as an ordered combination adds nothing that is not already present when looking at the elements taken individually. There is no indication that the combination of elements improves the functioning of a computer or improves any other technology, and their collective functions merely provide conventional computer implementation or implementing the judicial exception on a generic computer.
Therefore, whether taken individually or as an ordered combination, claims 2-5 are nonetheless rejected under 35 U.S.C. 101 as being directed to non-statutory subject matter.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4-5, and 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sinyavskiy (US 20140032458 A1).
Regarding Claims 1 and 7, Sinyavskiy teaches A neural network device comprising (Sinyavskiy: Abstract): An information processing method comprising (Sinyavskiy: Abstract):
a time-scheme spiking neuron model that outputs a signal when an internal state quantity that evolves over time in accordance with a signal input clock time, becomes a threshold value or more (Sinyavskiy: Paragraph(s) 0102, 0161, 0165, 0229, 0244, 0113, 0115 teach(es) facilitating learning spiking neuron networks by, inter alia, implementing efficient synaptic updates; The panel in FIG. 7 illustrates event sequence, comprising for example, neuron inputs (such as feed-forward input and/or a reinforcement spikes). In one implementation, (not shown) the event clock and the EDCC components computation clock may be synchronized and selected to be updated at regular network update intervals, for example 1 ms intervals; yd(t)=Σt k δ(t−tk d) denotes the teaching spike pattern, corresponding to the desired (or reference) signal that may be part of external signal of FIG. 4, where t_k^d denotes the times when the spikes of the reference signal are received by the neuron); and a delay unit that outputs a signal obtained by changing, by a set time, a spike clock time that is represented by the output signal of the time-scheme spiking neuron model unit as a relative clock time with respect to a reference clock time (Sinyavskiy: Paragraph(s) 0061, 0165-0166, 0108-0112, 0229 teach(es) the update may be delayed until a next regular time interval occurring subsequent to occurrence of the data item of the one or more data items; The panel illustrates delayed synchronous on-demand updates, where the updates may be synchronized to a clock (e.g., local neuron clock or global network clock) and performed at the next following clock instance).
Regarding Claim 4, Sinyavskiy teaches all the limitations of claim 1 above; and Sinyavskiy further teaches further comprising: a set spike supplying(Sinyavskiy: Paragraph(s) 0102, 0161, 0165, 0229, 0244, 0113, 0115, as stated above with respect to claim 1).
Regarding Claim 5, Sinyavskiy teaches all the limitations of claim 1 above; and Sinyavskiy further teaches wherein at least either the time- scheme spiking neuron model and the delay unit is configured using an Application Specific Integrated Circuit (ASIC) or a Field- Programmable Gate Array (FPGA) (Sinyavskiy: Paragraph(s) 0094-0095, 0266 teach(es) integrated circuits may include field programmable gate arrays (e.g., FPGAs), a programmable logic device (PLD), reconfigurable computer fabrics (RCFs), application-specific integrated circuits (ASICs), and/or other types of integrated circuits).
Claim Rejections - 35 USC § 103
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sinyavskiy (US 20140032458 A1) in view of Onishi (JP 2010146514 A; already of record in IDS).
Regarding Claim 6, Sinyavskiy teaches A generation device comprising: a base network generating unit that generates a neural network, the neural network including a time-scheme spiking neuron model that outputs a signal when an internal state quantity that evolves over time in accordance with a signal input clock time, becomes a threshold value or more, and a delay unit that outputs a signal obtained by changing, by a set time, a spike clock time that is represented by the output signal of the time-scheme spiking neuron model as a relative clock time with respect to a reference clock time, as stated above with respect to claims 1 and 7; and Sinyavskiy further teaches a weight setting unit that sets a weight of an input signal to the time-scheme spiking neuron model to a weight based on an equation in which, … (Sinyavskiy: Paragraph(s) 0052, 0108, 0113, 0134 teach(es) individual ones of the plurality of parameters may comprise a weight. The weight may be configured to modify a state of the node based on an occurrence of a data item of the one or more data items within the decay time scale); and a delay setting unit that sets the set time of the delay unit to a time based on an equation in which, … (Sinyavskiy: Paragraph(s) 0061, 0165-0166, 0108-0112, 0229 teach(es) the update may be delayed until a next regular time interval occurring subsequent to occurrence of the data item of the one or more data items; The panel illustrates delayed synchronous on-demand updates, where the updates may be synchronized to a clock (e.g., local neuron clock or global network clock) and performed at the next following clock instance).
However, Sinyavskiy does not explicitly teach when an input clock time of the input signal is a clock time in which a sign of a numerical value represented by the input signal is reversed, an output clock time of an output signal of the delay unit becomes a clock time in which a sign of a numerical value represented by the output signal is reversed.
Onishi further teaches when an input clock time of the input signal is a clock time in which a sign of a numerical value represented by the input signal is reversed, an output clock time of an output signal of the delay unit becomes a clock time in which a sign of a numerical value represented by the output signal is reversed (Onishi: Page 3, lines 4-28; 7/39-45; 12/14-17 teach(es) When a spike pulse is input from an external or other neuron, a unimodal voltage change appears at the junction (synapse) between neurons. This is called a post-synaptic potential (hereinafter abbreviated as “PSP”). The direction of the voltage change of the PSP is positive or negative according to the sign (positive or negative) of the synaptic connection; a method of applying a reverse polarity pulse is called a “bipolar switching method (bipolar operation)”).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Sinyavskiy to incorporate the teachings of Onishi for when an input clock time of the input signal is a clock time in which a sign of a numerical value represented by the input signal is reversed, an output clock time of an output signal of the delay unit becomes a clock time in which a sign of a numerical value represented by the output signal is reversed.
There is motivation to combine Onishi into Sinyavskiy because Onishi’s teachings of bipolar switching method would facilitate the spiking neuron model (Onishi: Paragraph(s) Page 3, lines 4-28; 7/39-45; 12/14-17).
Regarding Claim 2, Sinyavskiy teaches all the limitations of claim 1 above; and Sinyavskiy further teaches wherein a weight of an input signal to the time-scheme spiking neuron model is set to a weight based on an equation in which, … (Sinyavskiy: Paragraph(s) 0052, 0108, 0113, 0134 teach(es) individual ones of the plurality of parameters may comprise a weight. The weight may be configured to modify a state of the node based on an occurrence of a data item of the one or more data items within the decay time scale).
However, Sinyavskiy does not explicitly teach when an input clock time of the input signal is a clock time in which a sign of a numerical value represented by the input signal is reversed, an output clock time of an output signal of the delay unit becomes a clock time in which a sign of a numerical value represented by the output signal is reversed.
Onishi from same or similar field of endeavor teaches when an input clock time of the input signal is a clock time in which a sign of a numerical value represented by the input signal is reversed, an output clock time of an output signal of the delay unit becomes a clock time in which a sign of a numerical value represented by the output signal is reversed (Onishi: Page 3, lines 4-28; 7/39-45; 12/14-17 teach(es) When a spike pulse is input from an external or other neuron, a unimodal voltage change appears at the junction (synapse) between neurons. This is called a post-synaptic potential (hereinafter abbreviated as “PSP”). The direction of the voltage change of the PSP is positive or negative according to the sign (positive or negative) of the synaptic connection; a method of applying a reverse polarity pulse is called a “bipolar switching method (bipolar operation)”).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Sinyavskiy to incorporate the teachings of Onishi for when an input clock time of the input signal is a clock time in which a sign of a numerical value represented by the input signal is reversed, an output clock time of an output signal of the delay unit becomes a clock time in which a sign of a numerical value represented by the output signal is reversed.
There is motivation to combine Onishi into Sinyavskiy because Onishi’s teachings of bipolar switching method would facilitate the spiking neuron model (Onishi: Paragraph(s) Page 3, lines 4-28; 7/39-45; 12/14-17).
Regarding Claim 3, the combination of Sinyavskiy and Onishi teaches all the limitations of claim 2 above; and Sinyavskiy further teaches further comprising: a time-scheme ramp function unit that outputs a signal at earlier of an output clock time of the output signal of the delay unit or the reference clock time (Sinyavskiy: Paragraph(s) 0061, 0165-0166, 0108-0112, 0229 teach(es) the update may be delayed until a next regular time interval occurring subsequent to occurrence of the data item of the one or more data items; The panel illustrates delayed synchronous on-demand updates, where the updates may be synchronized to a clock (e.g., local neuron clock or global network clock) and performed at the next following clock instance).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kale (US 20210053418 A1) teaches Intelligent Climate Control In Vehicles, including weighted sum of its inputs, neuron network, and activation function of the neuron.
Cleland (WO 2020210673 A1) teaches Neuromorphic Algorithm For Rapid Online Learning And Signal Restoration, including spiking neural network (SNN), and Network output interpreted as an evolving series of representations.
Kozloski (US 20160224888 A1) teaches Discovering And Using Informative Looping Signals In A Pulsed Neural Network Having Temporal Encoders, including spiking, weighted, neuron, and FPGA.
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/CLAY C LEE/ Primary Examiner, Art Unit 3699