DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 2/15/2023 have been fully considered but they are not persuasive.
Applicant’s amendment to claim 1 has incorporated limitations from claims 6, 8, and 11 and moved them into claim 1 with some modifications. However, claim 1 does not include all of the limitations of a claim indicated allowable in the Office action mailed 10/29/2025. Firstly, claim 11 originally had a chain of dependency through claims 1 -> 2 -> 3 -> 4 -> 5 -> 8 -> 11, but those claims were not all incorporated into claim 1. Additionally, the scope of the limitations of claim 11 (now canceled and included in claim 1) have been broadened due to the limitation “a part of the second gate sub-line overlapping with the second active layer forms a gate electrode of the second transistor” being modified to “a part of the second gate line overlapping with the second active layer forms a gate electrode of the second transistor”. After consideration of the teachings of the prior art, the Examiner found US 20180151661 A1 (Oh et al) to render claim 1 obvious in its current scope.
Additionally, claims 4 and 12 retain some issues of indefiniteness under 35 U.S.C. 112(b).
Drawings
Applicant’s amendment to the claims have rendered the drawing objection detailed in the Office action mailed 10/29/2025 moot, and it is withdrawn. The drawings are now acceptable.
Claim Objections
Claim 14 is objected to because of the following informalities: the term “the respective third active layer” is recited. The word “respective” is not necessary to designate the third active layer. Appropriate correction is required.
Claim 17 is objected to because of the following informalities: the term “the respective third active layer” is recited. The word “respective” is not necessary to designate the third active layer. Appropriate correction is required.
Claim 19 is objected to because of the following informalities: the term “the respective data signal line” is recited. The word “respective” is not necessary to designate the data signal line. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-5, 8-10, 12, 14, 17, and 19-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites the limitations “the data signal line” and “the first voltage line” in line 7 of the claim. There is insufficient antecedent basis for these limitations in the claim, as they do not specify which of the at least one data signal lines and/or first voltage lines is being referred to; no singular data signal line or first voltage line were provided antecedent basis. It will be understood that any of the data signal lines and first voltage lines may respectively be referred to by the claimed “the data signal line” and “the first voltage line”.
In contrast, the phrase “the data signal line configured to provide the data signal to the pixel driving circuit of the first sub-pixel of the first pixel unit” is considered to have adequate antecedent basis as the data signal line is clearly identified in relation to a given pixel unit and pixel driving circuit.
Due to their dependence on claim 4, claims 5 and 8-10 are also rejected on this basis.
Claim 12 first recites the limitations “the first voltage line” and “the data signal line” in line 13 of the claim. Claim 12 currently depends on claim 1. Neither claim 1 nor claim 12 provide antecedent basis for those limitations; claim 4 is no longer in the dependency chain of claim 12. The limitations “the first voltage line” and “the data signal line” will respectively be understood to refer to “a first voltage line” and “a data signal line” in their initial recitation in claim 12.
Due to their dependence on claim 12, claims 14, 17, and 19-21 are also rejected on this basis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5, 8-10, 28 are rejected under 35 U.S.C. 103 as being unpatentable over US patent publication US 20180151661 A1 (Oh et al hereinafter Oh).
Regarding claim 1, Oh discloses a display substrate, comprising: a base substrate (FIG. 4, first substrate 150a ¶ [0052]); a plurality of pixel units (FIG. 4, a plurality of pixels P on substrate 150a ¶ [0053, 0005]) arranged on the base substrate, wherein the plurality of pixel units are arranged in an array (FIG. 1, the pixels of the display are formed in a matrix ¶ [0005]) in a first direction (a horizontal direction based on the plane layout of FIGS. 9-10) and a second direction (a vertical direction based on the plane layout of FIGS. 9-10), each of the pixel units comprises a plurality of sub-pixels (FIGS. 9-10, sub-pixels SPn1-SPn4 ¶ [0070-0072]), each of the sub-pixels comprises a light emitting element (FIGS. 9-10, an OLED is formed in emission area EMA ¶ [0071]) and a pixel driving circuit (FIGS. 9-10, circuit area DRA has transistors which drive the OLED ¶ [0072]) configured to drive the light emitting element, and the pixel driving circuit comprises a first transistor (FIGS. 3 and 10, switching transistor SW ¶ [0042-0046, 0075]), a second transistor (FIG. 10, a pixel driving circuit in sub-pixel SPn1 includes sensing transistor ST ¶ [0075]) and a third transistor (FIG. 10, a pixel driving circuit in sub-pixel SPn1 includes driving transistor DR ¶ [0074]);
and a plurality of gate lines (FIGS. 3 and 10, scan line GL1 is one of many scan lines GL1-GLm ¶ [0039, 0075]) arranged on the base substrate, wherein the plurality of gate lines comprise a plurality of first gate lines (FIGS. 3 and 10, scan lines GL1-GLm include first gate lines which route scanning signals to gates of switching transistors SW ¶ [0043-0047, 0075]) configured to provide a scanning signal to gate electrodes of the first transistors of the pixel driving circuits in a plurality of rows of sub-pixels respectively (FIG. 1, scan lines GL1-GLm are provided in rows to the sub-pixels SP ¶ [0039]);
wherein at least one of the first gate lines comprises a first gate sub-line (FIG. 10, first upper scan line GLT ¶ [0077]), a second gate sub-line (FIG. 10, first lower scan line GLB ¶ [0077]) and a plurality of connecting lines (FIG. 10, scan connection lines GLI ¶ [0077]), the first gate sub-line and the second gate sub-line extend in the first direction (FIG. 10, scan lines GLT and GLB extend along the horizontal direction), the plurality of connecting lines extend in the second direction (FIG. 10, scan connection lines GLI extend along the vertical direction), the first gate sub-line and the second gate sub-line are spaced apart in the second direction (FIG. 10, scan lines GLT and GLB are spaced apart along the vertical direction), the plurality of connecting lines are spaced apart in the first direction (FIG. 10, scan connection lines GLI are spaced apart along the horizontal direction), and at least one of the plurality of connecting lines is configured to connect the first gate sub-line and the second gate sub-line (FIG. 10, each of scan connection lines GLI connect first upper scan line GLT to first lower scan line GLB);
wherein the display substrate comprises: a first conductive film layer (FIG. 12, light shield layer including DL4_LS on substrate 150a ¶ [0078]) arranged on the base substrate; a semiconductor film layer (non-illustrated channel regions of the transistors form a semiconductor film layer ¶ [0050]) arranged on a side of the first conductive film layer away from the base substrate (the channel regions are above the light shield layer relative to the substrate ¶ [0050]); a second conductive film layer (FIG. 12, gate metal layer GL1_GAT ¶ [0077]) arranged on a side of the semiconductor film layer away from the base substrate (while not explicitly illustrated, this is implied by the fact that the gate insulation layer GI is between gate metal layer GL1_GAT and substrate 150a, FIG. 12 ¶ [0079, 0087]; gate insulation layers separate gates from channel regions); and a third conductive film layer (FIG. 12, source-drain metal layer VREFC_SD ¶ [0078]) arranged on a side of the second conductive film layer away from the base substrate (FIG. 12, the metal layer including VREFC_SD is above gate metal layer GL1_GAT relative to substrate 150a), and wherein at least one of the pixel driving circuits comprises a first active layer, a second active layer and a third active layer (each of transistors ST, SW, and DR include channel regions ¶ [0050]), and the first active layer, the second active layer and the third active layer are located in the semiconductor film layer (while not explicitly illustrated, this is implied by the fact that the gate insulation layer GI is between gate metal layer GL1_GAT and substrate 150a, a gate insulating layer separating the gate metal layer from channel regions); and a part of the first gate line overlapping with the first active layer forms the gate electrode of the first transistor (FIG. 10, switching transistor SW is formed by the overlap of first gate line GL and the first channel region corresponding to transistor SW ¶ [0050]).
Regarding the limitation “a plurality of second gate lines configured to provide a scanning signal to gate electrodes of the second transistors of the pixel driving circuits in a plurality of rows of sub-pixels respectively”, Oh further teaches that in an alternative embodiment, the first transistor connects to a first gate line (FIG. 3, scan line GL1a at gate of switching transistor SW) and the second transistor connects to a second gate line (FIG. 3, scan line GL1b at gate of sensing transistor ST) configured to provide a scanning signal to gate electrodes of the second transistors of the pixel driving circuits in a plurality of rows of sub-pixels respectively (FIG. 3, scan line GLb1 sends a scan signal to sensing transistor ST ¶ [0047]). Oh also teaches that having separate first and second gate lines allows for the transmission of different scan signals to each of the transistors, which a person of ordinary skill in the art before the effective filing date of the claimed invention would recognize as providing a configuration with a more versatile control mechanism for the first and second transistors. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Oh of FIGS. 9-13 (the embodiment of primary consideration) in view of the teaching in ¶ [0047] such that the plurality of gate lines comprise a plurality of second gate lines configured to provide a scanning signal to gate electrodes of the second transistors of the pixel driving circuits in a plurality of rows of sub-pixels respectively, for provide a configuration with a more versatile control mechanism for the first and second transistors.
Regarding the limitation “and a part of the second gate line overlapping with the second active layer forms a gate electrode of the second transistor”, subsequent the obvious modification described above, the portion of the second gate line overlapping with the second active layer forms a gate electrode of the second transistor (in this case, sensing transistor ST having its channel region and scan line GLb1 overlap ¶ [0047, 0050]).
Regarding claim 2, Oh discloses the limitations of claim 1 as detailed above and further discloses that a row of pixel units comprise a plurality of pixel unit groups (FIG. 4 having demonstrated that 4 sub-pixels form one pixel P ¶ [0053], and FIG. 1 illustrating n columns of data lines DL present in the device, the sub-pixels connected to 8 adjacent data lines DL may constitute 8 sub-pixels which form a pixel unit group having 2 pixel units P), and each of the pixel unit groups comprises a first pixel unit and a second pixel unit adjacent to each other in the first direction (FIGS. 1 and 4, any 8 adjacent data lines DL correspond to the 8 sub-pixels of 2 adjacent pixel units P, each pixel unit P having a structure as shown by FIGS. 9-10 ¶ [0071-0076]); and the plurality of connecting lines comprise a first connecting line (FIG. 10, the scan connection line GLI in the subpixel SPn1 area of the first pixel unit ¶ [0077]) and a second connecting line (FIG. 10, the scan connection line GLI in the subpixel SPn1 area of the second pixel unit ¶ [0077]), the first connecting line is located in a region where the first pixel unit in a pixel unit group is located (FIG. 10, the scan connection line GLI in the subpixel SPn1 area of the first pixel unit is in a region inclusive of the first pixel unit SPn1), and the second connecting line is located in a region where the second pixel unit in a same pixel unit group is located (FIG. 10, the scan connection line GLI in the subpixel SPn1 area of the second pixel unit is in a region that includes the second pixel unit).
Regarding claim 3, Oh discloses the limitations of claim 2 as detailed above and further discloses that each of the first pixel unit and the second pixel unit comprises a first sub-pixel (FIG. 10, a first sub-pixel SPn1 is in each of the first and second pixel units ¶ [0071]) and a second sub-pixel (FIG. 10, a second sub-pixel SPn2 is in each of the first and second pixel units ¶ [0071]); and the first connecting line is located in a region where the pixel driving circuit of the first sub-pixel of the first pixel unit is located (FIG. 10, the subpixel area marked SPn1 includes the first scan connection line GLI of the first pixel unit), and the second connecting line is located in a region where the pixel driving circuit of the second sub-pixel of the second pixel unit is located (FIG. 10, a region inclusive of both subpixel areas marked SPn1 and SPn2 includes the second scan connection line GLI of the second pixel unit as well as the pixel driving circuit of the second sub-pixel of the second pixel unit).
Regarding claim 4, Oh discloses the limitations of claim 3 as detailed above and further discloses at least one data signal line (FIG. 10, data lines DL1-DL4 in the first and second pixel units arranged over the substrate ¶ [0072-0073]) arranged in each of the first and second pixel units on the base substrate and at least one first voltage line (FIG. 10, first power lines EVDD are provided in the pixel units and arranged over the substrate ¶ [0072-0074]) arranged in each of the first and second pixel units on the base substrate, each of the at least one data signal line is configured to provide a data signal to the pixel driving circuit (data lines DL1-DL4 provides data signals to the subpixel SPn1-SPn4 ¶ [0038, 0072]), each of the at least one first voltage line is configured to provide a first voltage signal to at least one of the pixel driving circuits (first power line EVDD provides a first voltage signal to a pixel driving circuit through first power connection line EVDDC ¶ [0076]), and the data signal line and the first voltage line extend in the second direction (FIG. 10, data line DL1 and first power line EVDD both extend along the vertical direction);
the first connecting line is spaced apart from the data signal line configured to provide the data signal to the pixel driving circuit of the first sub-pixel of the first pixel unit (FIG. 10, in the first pixel unit, first scan connection line GLI in the SPn1 area is spaced apart from data line DL1), and the first connecting line is spaced apart from the first voltage line configured to provide the first voltage signal to the pixel driving circuit of the first sub-pixel of the first pixel unit (FIG. 10, in the first pixel unit, first scan connection line GLI in the SPn1 area is spaced apart from first power line EVDD); and the first connecting line is located, in the first direction, between the data signal line configured to provide the data signal to the pixel driving circuit of the first sub-pixel of the first pixel unit and the first voltage line configured to provide the first voltage signal to the pixel driving circuit of the first sub-pixel of the first pixel unit (FIG. 10, in the first pixel unit, first scan connection line GLI in the SPn1 area is located between data line DL1 and first power line EVDD).
Regarding claim 5, Oh discloses the limitations of claim 4 as detailed above and further discloses that the second connecting line is spaced apart from the data signal line configured to provide the data signal to the pixel driving circuit of the second sub-pixel of the second pixel unit (FIG. 10, in the second pixel unit, second scan connection line GLI in the SPn1 area is spaced apart from data line DL2), and the second connecting line is spaced apart from the first voltage line configured to provide the first voltage signal to the pixel driving circuit of the second sub-pixel of the second pixel unit (FIG. 10, in the second pixel unit, second scan connection line GLI in the SPn1 area is spaced apart from first power line EVDD);
and the second connecting line is located, in the first direction, between the data signal line configured to provide the data signal to the pixel driving circuit of the second sub-pixel of the second pixel unit and the first voltage line configured to provide the first voltage signal to the pixel driving circuit of the second sub-pixel of the second pixel unit (FIG. 10, in the second pixel unit, second scan connection line GLI in the SPn1 area is located between data line DL2 and first power line EVDD along the horizontal direction).
Regarding claim 8, Oh discloses the limitations of claim 5 as detailed above, and Oh further discloses that the first gate sub-line, the second gate sub-line and the plurality of connecting lines are located in the second conductive film layer (FIGS. 10 and 12, scan line GL1 which includes sub-lines and connecting lines GLT, GLB, and GLI is in gate metal layer GL1_GAT ¶ [0077]).
Regarding claim 9, Oh discloses the limitations of claim 8 as detailed above and further discloses that the first transistor comprises a first active layer located in the semiconductor film layer (a switching transistor SW includes a non-illustrated channel region ¶ [0050]); an orthographic projection of the first gate sub-line on the base substrate overlaps partially with an orthographic projection of the first active layer on the base substrate (this is implied in FIG. 10 where switching transistor SW is indicated to be formed at the first upper scan line GLT ¶ [0076-0077]; this is where the gate line GLT forms the gate of transistor SW by overlapping the non-illustrated channel region of transistor SW); and an orthographic projection of the second gate sub-line on the base substrate is spaced apart from the orthographic projection of the first active layer on the base substrate (this is implied in FIG. 10 where switching transistor SW is indicated to be formed at the first upper scan line GLT and does not overlap first lower scan line GLB ¶ [0076-0077]).
Regarding claim 10, Oh discloses the limitations of claim 8 as detailed above and further discloses that orthographic projections of the plurality of connecting lines on the base substrate are spaced apart from an orthographic projection of the semiconductor film layer on the base substrate (this is implied in FIG. 10 where switching transistor SW, sensing transistor ST, and drive transistor DR are all indicated to be formed at positions that do not overlap any of the scan connection lines GLI).
Regarding claim 28, Oh discloses a display device (the display device of FIG. 1 which includes the display substrate of claim 1 ¶ [0011, 0034, 0052, 0071]), comprising the display substrate of claim 1 (see rejection of claim 1 above).
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Oh as applied to claim 1 above, and further in view of US patent publication US 20220285474 A1 (Kim et al hereinafter Kim).
Regarding claim 6, Oh discloses the limitations of claim 1 as detailed above, but did not explicitly disclose that at least one of the second gate lines comprises a gate line body portion and a gate line additional portion connected to the gate line body portion, and the at least one of the second gate lines comprises a ring structure surrounded by the gate line body portion and the gate line additional portion.
However, Kim discloses a display device (the device of FIGS. 1-3, ¶ [0031-0033]) comprising a plurality of first gate lines (FIG. 2, gate scan lines GWL ¶ [0065-0068], which have a “double line” structure analogous to that of the gate lines GL of Oh FIG. 10), and a plurality of second gate lines (FIG. 3, gate initialization lines GIL_i ¶ [0065-0068]), wherein at least one of the second gate lines comprises a gate line body portion (FIG. 3, gate line GLI_i includes a line body portion that extends along the DR1 direction ¶ [0103-0107]) and a gate line additional portion (FIG. 3, gate line GLI_i includes an additional portion which branches out from the line body portion along the DR2 direction ¶ [0103-0106]; this portion is part of first portion P1) connected to the gate line body portion, and the at least one of the second gate lines comprises a ring structure (FIG. 3, a ring structure is surrounded by the line body and additional portions of GLI_i) surrounded by the gate line body portion and the gate line additional portion. Such a configuration would inform a person of ordinary skill in the art before the effective filing date of the claimed invention on a configuration of pluralities of first gate lines and second gate lines wherein multiple transistors in the same pixel circuit (in the context of Kim FIG. 4, transistors T3 and T4 ¶ [0124]) are separately addressed by separate the gate lines as a matter of obvious design choice, and Kim also teaches that their second gate line structure has relatively low linear resistance (¶ [0114]).
Oh and Kim both pertain to the field of display substrates, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Oh in view of Kim such that at least one of the second gate lines comprises a gate line body portion and a gate line additional portion connected to the gate line body portion, and the at least one of the second gate lines comprises a ring structure surrounded by the gate line body portion and the gate line additional portion, in order to achieve a configuration with a more versatile control mechanism for the first and second transistors as suggested by Oh and illustrated by Kim with relatively low linear resistance to improve the electrical properties of the device.
Regarding claim 7, Oh in view of Kim discloses the limitations of claim 6 as detailed above, and further discloses that the gate line additional portion comprises a first additional portion (Kim FIG. 3, in the portion of gate like GIL_i above the two left pixels PX, a left branch extending lengthwise along the DR2 direction), a second additional portion (Kim FIG. 3, in the portion of gate line GIL_i above the two left pixels PX, a right branch extending lengthwise along the DR2 direction) and a third additional portion (Kim FIG. 3, in the portion of gate line GIL_i above the two left pixels PX, the upper portion relative to the DR2 direction extending lengthwise along the DR1 direction), the first additional portion and the second additional portion extend from the gate line body portion respectively in the second direction (Kim FIG. 3, the first and second additional portions extend from the gate line body along the DR2 direction, which is the second direction ¶ [0067]), the third additional portion extends in the first direction (Kim FIG. 3, the third additional portion as described above extends along the DR1 direction, which is the first direction ¶ [0067]), one end of the first additional portion is connected to the gate line body portion, another end of the first additional portion is connected to one end of the third additional portion (Kim FIG. 3, the first additional portion’s lower end connects to the line body portion of GIL_i, and its upper end connects to the third additional portion), another end of the third additional portion is connected to one end of the second additional portion (Kim FIG. 3, the second additional portion’s upper end connects to the third additional portion), and another end of the second additional portion is connected to the gate line body portion (Kim FIG. 3, the second additional portion’s lower end connects to the line body portion of GIL_i).
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Oh in view of Kim as applied to claim 7 above, and further in view of Chinese patent publication CN 112331714 A (Zhang et al hereinafter Zhang). The Office action mailed 10/29/2025 included a translation of the latter document with may be referenced for page/paragraph citations.
Oh in view of Kim discloses the limitations of claim 7 as detailed above, and Oh further discloses that an orthographic projection of the second gate line on the base substrate (while not explicitly illustrated in FIGS. 3 and 10, the second gate line GL1b extends along the horizontal direction in view of the schematic diagram of FIG. 1) overlaps partially with an orthographic projection of the first voltage line on the base substrate (FIG. 10, first power line EVDD ¶ [0043]), an orthographic projection of the data signal line on the base substrate (FIG. 10, first data line DL1 ¶ [0038]), an orthographic projection of a sensing signal line on the base substrate (FIG. 10, sensing line VREF ¶ [0045]) respectively at a first position, a second position, a third position (while not explicitly illustrated in FIGS. 3 and 10, the second gate line GL1b extends along the horizontal direction with the first gate line and intersects the vertically-extending voltage lines EVDD, data lines DL1-DL4, and sensing line VREF ¶ [0039, 0047]); in a pixel unit, each of the second active region of the second transistor of the first sub-pixel and the second active region of the second transistor of the second sub-pixel (FIGS. 3 and 10, an electrical connection between the source/drains and sensing line VREF is present when current runs through second/sensing transistor ST in both the first and second sub-pixels ¶ [0045]) is electrically connected to the sensing signal line, and each of the second active region of the second transistor of the third sub-pixel and the second active region of the second transistor of the fourth sub-pixel (FIGS. 3 and 10, an electrical connection between the source/drains and sensing line VREF is present when current runs through second/sensing transistor ST in both the third and fourth sub-pixels ¶ [0045]) is electrically connected to the sensing signal line.
Oh in view of Kim does not disclose an orthographic projection of the second gate line on the base substrate overlaps partially with an orthographic projection of an auxiliary cathode line on the base substrate at a fourth position; and the second gate line comprises at least one ring structure located in at least one of the first position, the second position, the third position and the fourth position, wherein the second gate line comprises a plurality of ring structures located at the first position and the fourth position respectively, wherein the display substrate further comprises a second conductive connecting portion and a third conductive connecting portion that are located in the third conductive film layer, and the second conductive connecting portion is connected to the sensing signal line; in a pixel unit, each of the second active region of the second transistor of the first sub-pixel and the second active region of the second transistor of the second sub-pixel is electrically connected to the sensing signal line through the third conductive connecting portion, a second conductive portion and the second conductive connecting portion, and each of the second active region of the second transistor of the third sub-pixel and the second active region of the second transistor of the fourth sub-pixel is electrically connected to the sensing signal line through the second conductive connecting portion; and each of an orthographic projection of the third conductive connecting portion on the base substrate, an orthographic projection of the second conductive portion on the base substrate and an orthographic projection of the second conductive connecting portion on the base substrate is spaced apart from an orthographic projection of the ring structure of the second gate line on the base substrate.
However, Zhang discloses a display device (the device of FIGS. 3A-3B) wherein the second gate line (FIG. 3A, second scan line 160, page 22 paragraph 4) comprises at least one ring structure (FIG. 3A, ring structures formed by portions 161 and 162 are at overlap locations with data lines DL1-DL4, detection line 230, and power supply line 240, page 22 paragraph 7) located in at least one of the first position, the second position, the third position, wherein the second gate line comprises a plurality of ring structures located at the first position (FIG. 3A, data line DL1 has a first position overlap with a ring structure of second scan line 160), wherein the display substrate further comprises a second conductive connecting portion (FIG. 3A, a central portion of detection part 231 directly at and around its connection to detection line 230, page 24 paragraphs 1-4) and a third conductive connecting portion (FIG. 3A, a portion of detection part 231 adjoining the left edge of the central portion, located to the right of the connection via from sub-pixel P4, page 24 paragraphs 1-4) that are located in the third conductive film layer (detection part 231 is located in conductive film layer 501, page 24 paragraph 8), and the second conductive connecting portion is connected to the sensing signal line (FIG. 3A, the central portion of detection part 231 directly at and around detection line 230 connects to it); in a pixel unit (FIG. 3A, upper four sub-pixels P1-P4 form a pixel unit, page 19 paragraphs 3-4), each of the second active region of the second transistor of the first sub-pixel (FIG. 3A, third transistor T3’s active region in sub-pixel P1 page 17 paragraph 3) and the second active region of the second transistor of the second sub-pixel (FIG. 3A, third transistor T3’s active region in sub-pixel P4) is electrically connected to the sensing signal line through the third conductive connecting portion, a second conductive portion (FIG. 3A, a portion of detection part 231 at the connection via from sub-pixel P4, adjoining the third conductive connection portion) and the second conductive connecting portion (FIG. 3A, the claimed third conductive connecting portion, second conductive portion, and second conductive connection portion provide a conductive path from each of the active regions of the third transistors T3 of the sub-pixels P1 and P4), and each of the second active region of the second transistor of the third sub-pixel (FIG. 3A, third transistor T3’s active region in sub-pixel P3) and the second active region of the second transistor of the fourth sub-pixel (FIG. 3A, third transistor T3’s active region in sub-pixel P2) is electrically connected to the sensing signal line through the second conductive connecting portion (FIG. 2B and 3A, each third transistor T3’s active region electrically connects to detection line 230 though the central portion of detection part 231 directly at and around its connection to detection line 230); and each of an orthographic projection of the third conductive connecting portion on the base substrate, an orthographic projection of the second conductive portion on the base substrate and an orthographic projection of the second conductive connecting portion on the base substrate is spaced apart from an orthographic projection of the ring structure of the second gate line on the base substrate (FIG. 3A, the ring structures of scan line 160 do not overlap detection part 231). Zhang also teaches that their configuration of conductive lines manages the overlap of signal lines and can reduce parasitic capacitance and signal delay (page 24 paragraph 4).
Oh, Kim, and Zhang all pertain to the field of display substrates, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Oh in view of Kim further in view of Zhang such that the second gate line comprises at least one ring located in at least one of the first position, the second position, the third position, wherein the second gate line comprises a plurality of ring structures located at the first position, wherein the display substrate further comprises a second conductive connecting portion and a third conductive connecting portion that are located in the third conductive film layer, and the second conductive connecting portion is connected to the sensing signal line; in a pixel unit, each of the second active region of the second transistor of the first sub-pixel and the second active region of the second transistor of the second sub-pixel is electrically connected to the sensing signal line through the third conductive connecting portion, a second conductive portion and the second conductive connecting portion, and each of the second active region of the second transistor of the third sub-pixel and the second active region of the second transistor of the fourth sub-pixel is electrically connected to the sensing signal line through the second conductive connecting portion; and each of an orthographic projection of the third conductive connecting portion on the base substrate, an orthographic projection of the second conductive portion on the base substrate and an orthographic projection of the second conductive connecting portion on the base substrate is spaced apart from an orthographic projection of the ring structure of the second gate line on the base substrate, in order to manage the overlap of signal lines and reduce parasitic capacitance and signal delay.
Oh in view of Kim and Zhang do not explicitly disclose an orthographic projection of the second gate line on the base substrate overlaps partially with an orthographic projection of an auxiliary cathode line on the base substrate at a fourth position, the second gate line comprises at least one ring structure located at the fourth position. Zhang does however contemplate the inclusion of an auxiliary electrode line among the signal lines (page 23 paragraph 4), and further states that places where scanning (gate) lines and signal lines cross may be set in the ring structures of the gate lines to allow for repair by cutting one defective portion of the ring structure while the circuit structure can still work through the other channel (page 23 paragraph 5). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Oh in view of Kim and Zhang to further include an auxiliary cathode line, such that an orthographic projection of the second gate line on the base substrate overlaps partially with an orthographic projection of an auxiliary cathode line on the base substrate at a fourth position, and the second gate line comprises at least one ring structure located at the fourth position, in order to include an auxiliary cathode line which would adjust the electrical properties of the device, since Zhang suggested the inclusion of such an element, and position the auxiliary cathode line as claimed in order to have it cross the gate line at the ring structure to allow for repair in the event of a defect in the ring structure.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Oh) as applied to claim 1 above, and further in view of US 20140313112 A1 (Madhusudan).
Oh discloses the limitations of claim 1 as detailed above, and further discloses that the display substrate further comprises a first electrode layer (FIGS. 3 and 9-10, an electrode layer including the anode electrodes of the OLEDs ¶ [0045-0046, 0071]) and the third conductive film layer (FIG. 12, data line/light shield DL4_LS is a conductive film layer ¶ [0078]), and the display substrate comprises a plurality of anodes (FIG. 3, the OLEDs of the sub-pixels includes anode electrodes ¶ [0045-0046]) located in the first electrode layer; and for at least one pixel unit group (a pixel unit group may be a set of pixel units such as a pair of the one shown in FIG. 10, where a first pixel unit of the pixel unit group is pictured in the figure, and a second pixel unit of the pixel group is located above or below along the second vertical direction, such an arrangement implied by the matrix array of subpixels mentioned in ¶ [0005], further implied by the rows and columns of scan lines GL1-GLm and data lines DL1-DLn in FIG. 1), the pixel driving circuits of the plurality of sub-pixels are arranged side by side in the first direction (FIG. 10, multiple sub-pixels are arranged along the horizontal direction), and the anodes of the light emitting elements of the plurality of sub-pixels are arranged in two rows in the second direction (as illustrated by FIG. 1, rows of gate lines GL1-m along the vertical direction indicate that a second pixel unit with the structure shown in FIG. 10 may be present above or below the pictured first pixel unit of FIG. 10),
wherein for a sub-pixel, a relationship between an orthographic projection of the pixel driving circuit of the sub-pixel on the base substrate and an orthographic projection of the anode of the light emitting element of the sub-pixel on the base substrate comprises: the orthographic projection of the pixel driving circuit of the sub-pixel on the base substrate exceeds the orthographic projection of the anode of the light emitting element of the sub-pixel on the base substrate in the second direction; and/or the orthographic projection of the anode of the light emitting element of the sub-pixel on the base substrate exceeds the orthographic projection of the pixel driving circuit of the sub-pixel on the base substrate in the first direction (FIG. 10, projections of both circuit area DRA and emission area EMA which includes the OLED ¶ [0071] include portions that exceed the other; which is to say that each area has an orthographic projection which includes a portion not included in the other area, that being the interpretation of the term ‘exceed’ being considered currently).
Oh does not explicitly teach that the first electrode layer is on a side of the third conductive film layer away from the base substrate (FIG. 12, DL4_LS is illustrated directly on substrate 150a; however, the anode of the OLED is not illustrated in a cross-sectional figure, the relative positions not emphasized in the disclosure of Oh).
However, Madhusudan discloses a first electrode layer (FIG. 4, first electrode 710 is an anode in a first electrode layer ¶ [0045]) is on a side of a third conductive film layer (FIG. 4, a third conductive film layer including a data wire, which includes driving source electrode 176 ¶ [0055]) away from a base substrate (FIG. 4, substrate member 111 is below 710, with driving source electrode 176 between them ¶ [0052]).
Oh and Madhusudan both pertain to the field of display substrates, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to have the device of Oh informed in view of Madhusudan such that it places the first electrode layer is on a side of the third conductive film layer away from the base substrate as a matter of obvious design choice demonstrated in the prior art, in order to configure the pixel electrodes and data lines of the display device to display images.
Allowable Subject Matter
Claims 12, 14, 17, and 19-21 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims, as well as rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US patent publication US 20210167162 A1.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/E.R.C./Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813