DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/10/2026 has been entered.
Claims 1, 3-7, 9-15, 17-21 are pending and have been examined.
Response to Amendments
Applicant's response of 03/10/2026 has been acknowledged. Claims 1, 3, 4, 9 and 20 have been amended. No new matter has been added.
This office action considers claims 1, 3-7, 9-15, 17-21 pending for prosecution and are examined on their merits.
Response to Arguments
Applicant's arguments of 03/10/2026 with respect to the rejections of claims have
been fully considered, and are persuasive. However, upon further consideration, a new ground(s) of rejection is made in view of Tang et al. (US 20210233985 A1 – hereinafter Tang).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 1, 3-6, 20, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Tang et al. (US 20210233985 A1 – hereinafter Tang) in view of Seong et al. (US 20220199730 A1 – hereinafter Seong), Tomiyasu et al. (US 20130234137 A1 – hereinafter Tomiyasu), Kong et al. (US 20230217796 A1 – hereinafter Kong), Jang et al. (US 20220208878 A1 – hereinafter Jang), and Park et al. (US 10079276 B2 – hereinafter Park).
Regarding independent claim 1, Tang teaches:
(Currently Amended) A display substrate (Fig. 6 shows the display
substrate that is described below – hereinafter ‘100’), comprising:
a base substrate (10 – Fig. 10 – [0090] – “substrate 10”) and a plurality of
pixel units arranged on the base substrate (100), wherein
each pixel unit comprises a plurality of sub-pixels, and each sub-pixel comprises a light emitting element ([0074] – “FIG. 1 to FIG. 10 are schematic structural diagrams of an organic light emitting diode (OLED) display panel” – although the entire light emitting element is not show, Fig. 10 includes the pixel electrode for a light emitting element, hereinafter ‘OLED’) and a pixel driving circuit (fig. 6 shows a pixel driving circuit – hereinafter ‘SPC’) for driving the light emitting element (OLED);
wherein the pixel driving circuit (SPC) comprises:
a functional layer (16 – Fig. 10 – [0079] – “first transparent conductive layer 16” – this is a functional layer) arranged on a side of the base substrate (10);
a light-shielding layer (18 – fig. 10 – [0091] – “light shielding metal layer 18”) arranged on a side of the functional layer (16) away from the base substrate (10), wherein the light-shielding layer (18) is electrically connected to the functional layer (Fig. 10 shows this);
a buffer layer (20 – Fig. 10 – [0091] – “buffer layer 20”) arranged on a
side of the light-shielding layer (18) away from the base substrate (10) and covering the functional layer (16) and the light-shielding layer (18 – Fig. 10 shows this);
an active layer (24 – Fig. 10 – [0101] – “active region 24”) arranged on a
side of the buffer layer (20) away from the base substrate (10 – Fig. 10
shows this);
a gate electrode layer (28 – Fig. 10 annotated, see below – [0102] –
“metal layer 28”) arranged on a side of the active layer (24) away from the
base substrate (10 – Fig. 10 shows this);
a first via hole (Fig. 10 annotated, see below – [0103] – “via hole
exposing the entire metal layer 18” – hereinafter ‘60’) penetrating the buffer layer (20); and
a signal line (32 – Fig. 10 – [0092] – “transparent conductive layer 32” –
this corresponds to a signal line) arranged on a side of the buffer layer (20)
away from the base substrate (10);
wherein the functional layer (16) of the pixel driving circuit (SPC) of each
sub-pixel is electrically connected to the signal line (32) at least through the first via hole (60);
wherein a projection of the light-shielding layer (18) on the base substrate
(10) and a projection of the functional layer (16) on the base substrate (10) form an overlap region (Fig. 10 annotated, see below – [0089] – “projection of the first region on the horizontal plane, and a projection of the first active region on the horizontal plane overlap. Therefore, the first region of the first transparent conductive layer of the active region, the first active region, the second transparent conductive layer, the anode, and insulating layers between them constitute a plurality of capacitor structures connected in series to increase the capacitance of the OLED panel” – this describes the corresponding overlap region, hereinafter ‘A’, ‘B’, or ‘C’) and a projection of the first via hole (60) on the base substrate (10) is located in the overlap region (A, B, C);
wherein a thickness of the light-shielding layer is greater than a thickness of the
functional layer;
wherein the pixel driving circuit comprises a storage capacitance;
wherein a part of the functional layer (16) forms a first electrode of the
storage capacitance (Fig. 10 annotated, see below – [0072] – “The first
transparent conductive layer, the first active region and the second transparent conductive layer are respectively separated by a buffer layer and an interlayer dielectric layer, thereby forming a three-layer parallel capacitor structure” – this corresponds to a storage capacitor, hereinafter ‘CST’), and a part of the active layer forms (Fig. 10 annotated, see below – this corresponds to the active layer, hereinafter ‘21’) a second electrode of the storage capacitance (Fig. 10 annotated, see below – [0089] – “the first region of the first transparent conductive layer of the active region, the first active region, the second transparent conductive layer, the anode, and insulating layers between them constitute a plurality of capacitor structures connected in series to increase the capacitance of the OLED panel” – hereinafter ‘CE2’);
wherein the pixel driving circuit of each sub-pixel at least comprises a driving
transistor and a sensing transistor;
wherein the first electrode of the storage capacitor and the second electrode of the storage capacitor are respectively connected to a gate electrode of the driving transistor and a second electrode of the sensing transistor, so as to store voltage signals;
wherein a part of the functional layer forms a first functional region of the sensing
transistor;
wherein the first functional region comprises a first functional sub-region located
at a first electrode of the sensing transistor and a second functional sub-region located at a second electrode of the sensing transistor, and
wherein a part of the light-shielding layer forms a first conductive connection part,
the first functional sub-region is electrically connected to the first electrode of the storage capacitance, and the first conductive connection part is configured to electrically connect the second functional sub-regions of the sensing transistors of different sub-pixels.
Tang does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Seong teaches
a plurality of pixel units ([0084] – “Four pixels 101 constituting an example unit
pixel among a plurality of pixels 101 are shown in FIG. 4” – hereinafter ‘PX’),
each pixel unit (PX) comprises a plurality of sub-pixels ([0085] – “unit pixel is a reference unit for representing various colors, and may, for example, include a red pixel R, a white pixel W, a blue pixel R and a green pixel G as shown in FIG. 4” – hereinafter ‘SP1-4’), and each sub-pixel (SP1-4),
wherein the pixel driving circuit (PDU – [0063] – “pixel 101 may include a pixel
driving unit PDU and a light emitting unit, wherein the pixel driving unit PDU may include a switching transistor Tsw1, a capacitor Cst, a driving transistor Tdr, and a sensing transistor Tsw2”) comprises a storage capacitance (Cst – [0063] – “pixel 101 may include a pixel driving unit PDU and a light emitting unit, wherein the pixel driving unit PDU may include a switching transistor Tsw1, a capacitor Cst, a driving transistor Tdr, and a sensing transistor Tsw2”);
wherein the pixel driving circuit (PDU) of each sub-pixel (SP1-4) at least
comprises a driving transistor (Tdr – [0063] – “pixel 101 may include a pixel driving unit PDU and a light emitting unit, wherein the pixel driving unit PDU may include a switching transistor Tsw1, a capacitor Cst, a driving transistor Tdr”) and a sensing transistor (Tsw2 – [0063] – “pixel 101 may include a pixel driving unit PDU and a light emitting unit, wherein the pixel driving unit PDU may include a switching transistor Tsw1, a capacitor Cst, a driving transistor Tdr, and a sensing transistor Tsw2”);
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the pixel unit and sub-pixel structure as taught by Seong into Tang.
An ordinary artisan would have been motivated to use the known technique of Seong in the manner set forth above to produce the predictable result of [0003] – “A pixel constituting a light emitting display apparatus includes a light emitting element, and transistors and a capacitor for driving the light emitting element.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Tang and Seong do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Tomiyasu teaches
wherein a thickness of the light-shielding layer (17 – Fig. 11(c) – [0096] –
“light-blocking metal film (third conductive film) 17 (e.g., thickness: about 50-300 nm)”) is greater than a thickness of the functional layer (16 – Fig. 11(c) – [0096] – “a transparent conductive film (second conductive film) 16 (e.g., thickness: about 50-200 nm) of, for example, ITO, IZO, etc”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the light-shielding layer structure as taught by Tomiyasu into Tang and Seong.
An ordinary artisan would have been motivated to use the known technique of Tomiyasu in the manner set forth above to produce the predictable result of [0033] – “In the present invention, the entirety of each of source lines, the entirety of each of source electrodes, and the entirety each of drain electrodes are provided on the corresponding one of oxide semiconductor layers. Therefore, a TFT formed of an oxide semiconductor having satisfactory characteristics can reliably operate normally, and a TFT substrate including the TFTs can be manufactured using a smaller number of photomasks at lower cost. As a result, a TFT substrate, and in addition, a liquid crystal display device can be manufactured at lower cost without a decrease in manufacturing efficiency and yield.”
Tang, Seong, and Tomiyasu do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Kong teaches
wherein the first electrode (151 – Fig. 3 – [0094] – “storage capacitor 150
includes a first capacitor electrode 151”) of the storage capacitor (150 – Fig. 3 – [0086] – “storage capacitor 150”) and the second electrode (152 – Fig. 3 – [0086] – “the second capacitor electrode 152 of the storage capacitor 150”) of the storage capacitor (150) are respectively connected ([0096] – “the first capacitor electrode 151 may be electrically connected to the first gate electrode 121”) to a gate electrode (121 – Fig. 3 – [0071] – “first transistor 120 includes a first gate electrode 121”) of the driving transistor (120 – Fig. 3 – [0071] – “The first transistor 120 is disposed in the non-emission area NEA of each of the red sub-pixel SPR, the white sub-pixel SPW, the blue sub-pixel SPB, and the green sub-pixel SPG” – this corresponds to the drive transistor) and ([0086] – “the second capacitor electrode 152 of the storage capacitor 150 may be a sensing transistor SET”) a second electrode (142 – Fig. 3 – [0088] – “third source electrode 142 may be electrically connected to the second capacitor electrode 152 forming the storage capacitor 150”) of the sensing transistor ([0086] – “sensing transistor SET”), so as to store voltage signals;
wherein a part of the functional layer (RBL2 – Fig. 3 – [0121] – “the reference
branch line RBL may be conductive as it has the stack structure of the semiconductor layer RBL1 and the transparent oxide layer RBL2” – this corresponds to a functional layer) forms a first functional region (Fig. 3 annotated, see below – hereinafter ‘FFR’) of the sensing transistor (140 – Fig. 3 – [0124] – “the reference branch line RBL includes an active layer forming the channel of the sensing transistor SET where it overlaps with the first bridge line GBL1. As a result, the first bridge line GBL1 branching off from the gate line GL and extended to overlap with the reference branch line RBL may work as the third gate electrode 141, the active layer disposed under the first bridge line GBL1 may work as the third active layer 144, and the conductive region including the transparent oxide layer RBL2 under the second bridge line GBL2 may work as the third drain electrode 143” – this describes transistor 140 as the sensing transistor SET);
wherein the first functional region (FFR) comprises a first functional sub-
region (Fig. 3 annotated, see below – hereinafter ‘FFRS1’) located at a first electrode (142 – Fig. 3 – [0124] – “The third transistor 140 includes a third gate electrode 141, a third source electrode 142, a third drain electrode 143 and a third active layer 144”) of the sensing transistor (140) and a second functional sub-region (Fig. 3 annotated, see below – hereinafter ‘FFRS2’) located at a second electrode of the sensing transistor (143 – Fig. 3 – [0124] – “The third transistor 140 includes a third gate electrode 141, a third source electrode 142, a third drain electrode 143 and a third active layer 144”).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate functional region structure as taught by Kong into Tang, Seong, and Tomiyasu.
An ordinary artisan would have been motivated to use the known technique of Kong in the manner set forth above to produce the predictable result [0125] – “so that the aperture ratio can be improved and the repair process of the reference branch line RBL can proceed. As a result, the aperture ratio can be increased without any additional metal layer.”
Tang, Seong, Tomiyasu, and Kong do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Jang teaches
wherein a part of the light-shielding layer (LS – Fig. 3 – [0092] – “reference
bridge lines VREF_B1 and VREF_B2 may be formed by a light shielding layer LS”) forms a first conductive connection part (VREF_B1 – Fig. 8 – [0092] – “reference bridge lines VREF_B1” – this is a connection part).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the light-shielding layer structure as taught by Jang into Tang, Seong, Tomiyasu, and Kong.
An ordinary artisan would have been motivated to use the known technique of Jang in the manner set forth above to produce the predictable result of [0008] “to provide a light emitting display device that may improve an aperture ratio in a limited space of a subpixel and perform a repair process in response to various types of defects.”
Tang, Seong, Tomiyasu, Kong, and Jang do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Park teaches
the first functional sub-region (Fig. 2 – [5:51-53] – “second transistor (SENT) may be a sensing transistor, and may include a second gate electrode 252 and a second source electrode 256b/second drain electrode 256a”}) is electrically connected to the first electrode of the storage capacitance ([5:53-55] – “One end of the second transistor (SENT) is connected to a storage capacitor (Cstg)”), and the first conductive connection part (254 – Fig. 2 – [5:37-40] – “the eighth line 254 may be connected to the third line 260c, which is a reference voltage line, and a contact hole, so as to supply a reference voltage to adjacent sub-pixels”) is configured to electrically connect the second functional sub-regions of the sensing transistors (Fig. 2 – [5:51] – “second transistor (SENT)”) of different sub-pixels (Fig. 2 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the sub-region connection structure as taught by Park into Tang, Seong, Tomiyasu, Kong, and Jang.
An ordinary artisan would have been motivated to use the known technique of Park in the manner set forth above to produce the predictable result of a display device with elements connect through a display substrate.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 3, Tang as modified by Seong, Tomiyasu, Kong, Jang, and Park, teaches claim 1 from which claim 3 depends. Tang further teaches
(Currently Amended) The display substrate according to claim 1,
wherein the light-shielding layer (18) comprises a first light-shielding part
(Fig. 10 annotated, see below – hereinafter ‘31’), an orthographic projection of the first electrode (21) on the base substrate (10) overlaps with an orthographic projection of the first light-shielding part (31) on the base substrate (10) to form a first overlap region (A), and an area of the orthographic projection of the first electrode (21) on the base substrate (10) is greater than an area of the orthographic projection of the first light-shielding part (31) on the base substrate (10 – Fig. 10 annotated, see below, shows this).
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Regarding claim 4, Tang as modified by Seong, Tomiyasu, Kong, Jang, and Park, teaches claim 3 from which claim 4 depends. Tang further teaches
(Currently Amended) The display substrate according to claim [[1]] 3,
wherein an orthographic projection of the first via hole (60) on the base substrate (10) is located in the first overlap region (A – Fig. 10 annotated, see above, shows this).
Regarding claim 5, Tang as modified by Seong, Tomiyasu, Kong, Jang, and Park, teaches claim 3 from which claim 5 depends. Tang further teaches
the first via hole (60); and
wherein an orthographic projection of the light-shielding layer (18) on the
base substrate (10) overlaps with an orthographic projection of the first functional region (Fig. 10 annotated, see above – hereinafter ‘22’) on the base substrate (10) to form a second overlap region (B).
Tang, Tomiyasu, Kong, Jang, and Park do not expressly disclose the other limitations of claim 5.
However, in an analogous art, Seong teaches
(Previously Presented) The display substrate according to claim 3, wherein
the signal line comprises a sensing signal line (SL – Fig. 4 – [0070] – “sensing line SL may be connected to the sensing transistor Tsw2”);
wherein the first electrodes or the second electrodes of all sensing
transistors (Tsw2) of each pixel unit (PX) are electrically connected to the sensing signal line (SL – Fig. 4 – [0070] – “sensing line SL may be connected to the sensing transistor Tsw2”) at least through the first via hole; and
wherein an orthographic projection of the light-shielding layer on the base
substrate overlaps with an orthographic projection of the first functional region on the base substrate to form a second overlap region.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the pixel unit and sub-pixel structure as taught by Seong into Tang, Tomiyasu, Kong, Jang, and Park.
An ordinary artisan would have been motivated to use the known technique of Seong in the manner set forth above to produce the predictable result of as stated above in claim 1.
Regarding claim 6, Tang as modified by Seong, Tomiyasu, Kong, Jang, and Park, teaches claim 5 from which claim 6 depends. Tang further teaches
(Original) The display substrate according to claim 5, wherein the
orthographic projection of the first via hole (60) on the base substrate (10) is located in the second overlap region (B – Fig. 10 annotated shows this).
Regarding claim 9, Tang, as modified by Seong, Tomiyasu, Kong, Jang, and Park, teaches claim 1 from which claim 9 depends. Tang further teaches
wherein a part of the functional layer (16) forms a second functional region (Fig. 10 annotated, see below – hereinafter ‘23’).
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Tang, Tomiyasu, Kong, and Park do not expressly disclose the limitations of claim 9.
However, in an analogous art, Seong teaches
(Currently Amended) The display substrate according to claim 1,
wherein a first electrode or a second electrode of each driving transistor (Tdr) is electrically connected to the first electrode (150 – Fig. 20 – [0135] – “first electrode 150”) through the first via hole (CH1 – Fig. 20 – [0142] – “first contact hole CH1”); wherein the signal line (PLA – [0068] – “first voltage supply line PLA” – this is a signal line) further comprises a driving voltage signal line (EVDD – [0068] – “first voltage EVDD may be supplied to the driving transistor Tdr and the light emitting element ED through a first voltage supply line PLA”); wherein a part of the functional layer forms a second functional region electrically connected to the first electrode or the second electrode of the driving transistor (Tdr – Fig. – [0068] – “driving thin film transistor DT”); and
wherein a part of the light-shielding layer forms a second conductive connection part, and the second conductive connection part is configured to electrically connect the second functional region of at least one sub-pixel (SP1-4) in one and the same pixel unit (101 – [0063] – “pixel 101) with the driving voltage signal line.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the pixel circuit structure as taught by Seong into Tang, Liu, Shim, and Park.
An ordinary artisan would have been motivated to use the known technique of Seong in the manner set forth above to produce the predictable result of [0006] – “a light emitting display apparatus.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Tang, Liu, Shim, Park and Seong do not expressly disclose the other limitations of claim 9.
However, in an analogous art, Jang teaches
wherein a part of the light-shielding layer (LS – Fig. 3 – [0092] – “reference bridge lines VREF_B1 and VREF_B2 may be formed by a light shielding layer LS”) forms a second conductive connection part (VREF_H – Fig. 3 – [00607] – “reference line VREF may include an auxiliary reference line VREF_H (or auxiliary power line) extending in the first direction (or horizontal direction) toward the left and
right sides”), and the second conductive connection part (VREF _H) is configured to electrically connect the second functional region of at least one sub-pixel in one and the same pixel unit with the driving voltage signal line (VREF – Fig. 3 – [0048] – “the reference voltage Vref supplied through a reference line”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the functional region and light shielding structure as taught by Jang into Tang, Liu, Shim, Park and Seong.
An ordinary artisan would have been motivated to use the known technique of Jang in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 10, Tang, as modified by Seong, Tomiyasu, Kong, Jang, and Park, teaches claim 9 from which claim 10 depends. Tang further teaches
(Original) The display substrate according to claim 9, wherein an
orthographic projection of the second functional region (Fig. 10 annotated, see below – hereinafter ‘23’) on the base substrate (10) and an orthographic projection of the second conductive connection part (while Tang doesn’t expressly disclose the second conductive region, the structure shown in Fig. 10 can be applied to any overlap region as it is repetitive to each pixel/sub-pixel and the display device) on the base substrate (10) coincides to form a third overlap region (C – Fig. 10 annotated, see below, shows this).
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Regarding claim 11, Tang, as modified by Seong, Tomiyasu, Kong, Jang, and Park, teaches claim 10 from which claim 11 depends. Tang further teaches
(Original) The display substrate according to claim 10, wherein the
orthographic projection of the first via hole (60) on the base substrate (10) is located in the third overlap region (C – Fig. 10 annotated, see above, shows this).
Regarding claim 12, Tang, as modified by Seong, Tomiyasu, Kong, Jang, and Park, teaches claim 10 from which claim 12 depends. Tang further teaches
the second overlap region (B).
Tang, Seong, Tomiyasu, Kong, and Park do not expressly disclose the other limitations of claim 12.
However, in an analogous art, Jang teaches
(Original) The display substrate according to claim 10, wherein in a direction perpendicular to a length of the first conductive connection part (VREF_B1), a width of the first conductive connection part (VREF_B1) located in the second overlap region is greater than a width of the first conductive connection part (VREF_B1) between adjacent sub-pixels (SP1-4 – Fig. 3 shows VREF-B1 is longer in the perpendicular direction than it Is wider in the between sub-pixels direction).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the conductive connection part width structure as taught by Jang into Tang, Seong, Tomiyasu, Kong, and Park.
An ordinary artisan would have been motivated to use the known technique of Jang in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 13, Tang, as modified by Seong, Tomiyasu, Kong, Jang, and Park, teaches claim 10 from which claim 13 depends. Tang further teaches
(Original) The display substrate according to claim 10, wherein in the
second overlap region (B) and the third overlap region (C), the orthographic projection of the functional layer (16) on the base substrate (10) is located within the orthographic projection of the light-shielding layer (18) on the base substrate (10 – Fig. 10 annotated shows this).
Regarding claim 21, Tang as modified by Seong, Tomiyasu, Kong, Jang, and Park, teaches claim 1 from which claim 21 depends. Tang further teaches
(Previously Presented) A display device, wherein the display device
([0005] – “The application provides an organic light emitting diode (OLED) display panel – this is a display device) comprises the display substrate (100) according to claim 1.
Regarding independent claim 20, Tang teaches:
(Currently Amended) A method of manufacturing a display substrate
(Fig. 6 shows the display substrate that is described below – hereinafter ‘100’), comprising:
forming a base substrate (10 – Fig. 10 – [0090] – “substrate 10”);
forming a plurality of pixel units on the base substrate (100), wherein each pixel
unit comprises a plurality of sub-pixels, and the forming a plurality of pixel units comprises forming, at each sub-pixel, a light emitting element ([0074] – “FIG. 1 to FIG. 10 are schematic structural diagrams of an organic light emitting diode (OLED) display panel” – although the entire light emitting element is not show, Fig. 10 includes the pixel electrode for a light emitting element, hereinafter ‘OLED’) and a pixel driving circuit (fig. 6 shows a pixel driving circuit – hereinafter ‘SPC’) for driving the light emitting element (OLED);
wherein the pixel driving circuit (SPC) comprises:
forming a functional layer (16 – Fig. 10 – [0079] – “first transparent conductive layer 16” – this is a functional layer) arranged on a side of the base substrate (10);
forming a light-shielding layer (18 – fig. 10 – [0091] – “light shielding metal layer 18”) on a side of the functional layer (16) away
from the base substrate (10), wherein the light-shielding layer (18) is
electrically connected to the functional layer (Fig. 10 shows this);
forming a buffer layer (20 – Fig. 10 – [0091] – “buffer layer 20”) on a side of the light-shielding layer (18) away from
the base substrate (10), wherein the buffer layer (20) covers the functional layer (16) and the light-shielding layer (18 – Fig. 10 shows this);
forming an active layer (24 – Fig. 10 – [0101] – “active region 24”) on a side of the buffer layer (20) away from the
base substrate (10 – Fig. 10 shows this);
forming a gate electrode layer (28 – Fig. 10 annotated, see below – [0102] – “metal layer 28”) on a side of the active layer (24) away
from the base substrate (10 – Fig. 10 shows this);
forming a first via hole (Fig. 10 annotated, see below – [0103] – “via hole exposing the entire metal layer 18” – hereinafter ‘60’) penetrating the buffer layer (20); and
forming a signal line (32 – Fig. 10 – [0092] – “transparent conductive layer 32” – this corresponds to a signal line) on a side of the buffer layer (20) away from the base substrate (10);
wherein the functional layer (16) of the pixel driving circuit (SPC) of each
sub-pixel is electrically connected to the signal line (32) at least through the first via hole (60);
wherein a projection of the light-shielding layer (18) on the base substrate
(10) and a projection of the functional layer (16) on the base substrate (10) form an overlap region (Fig. 10 annotated, see below – [0089] – “projection of the first region on the horizontal plane, and a projection of the first active region on the horizontal plane overlap. Therefore, the first region of the first transparent conductive layer of the active region, the first active region, the second transparent conductive layer, the anode, and insulating layers between them constitute a plurality of capacitor structures connected in series to increase the capacitance of the OLED panel” – this describes the corresponding overlap region, hereinafter ‘A’, ‘B’, or ‘C’) and a projection of the first via hole (60) on the base substrate (10) is located in the overlap region (A, B, C);
wherein a thickness of the light-shielding layer is greater than a thickness of the
functional layer;
wherein the pixel driving circuit comprises a storage capacitance;
wherein a part of the functional layer (16) forms a first electrode of the
storage capacitance (Fig. 10 annotated, see below – [0072] – “The first
transparent conductive layer, the first active region and the second transparent conductive layer are respectively separated by a buffer layer and an interlayer dielectric layer, thereby forming a three-layer parallel capacitor structure” – this corresponds to a storage capacitor, hereinafter ‘CST’), and a part of the active layer forms (Fig. 10 annotated, see below – this corresponds to the active layer, hereinafter ‘21’) a second electrode of the storage capacitance (Fig. 10 annotated, see below – [0089] – “the first region of the first transparent conductive layer of the active region, the first active region, the second transparent conductive layer, the anode, and insulating layers between them constitute a plurality of capacitor structures connected in series to increase the capacitance of the OLED panel” – hereinafter ‘CE2’);
wherein the pixel driving circuit of each sub-pixel at least comprises a driving
transistor and a sensing transistor;
wherein the first electrode of the storage capacitor and the second electrode of the storage capacitor are respectively connected to a gate electrode of the driving transistor and a second electrode of the sensing transistor, so as to store voltage signals;
wherein a part of the functional layer forms a first functional region of the sensing
transistor;
wherein the first functional region comprises a first functional sub-region located
at a first electrode of the sensing transistor and a second functional sub-region located at a second electrode of the sensing transistor, and
wherein a part of the light-shielding layer forms a first conductive connection part,
the first functional sub-region is electrically connected to the first electrode of the storage capacitance, and the first conductive connection part is configured to electrically connect the second functional sub-regions of the sensing transistors of different sub-pixels.
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Tang does not expressly disclose the other limitations of claim 20.
However, in an analogous art, Seong teaches
forming a plurality of pixel units ([0084] – “Four pixels 101 constituting an example unit pixel among a plurality of pixels 101 are shown in FIG. 4” – hereinafter ‘PX’) on the base substrate, wherein each pixel
unit ([0084] – “Four pixels 101 constituting an example unit pixel among a plurality of pixels 101 are shown in FIG. 4” – hereinafter ‘PX’) comprises a plurality of sub-pixels ([0085] – “unit pixel is a reference unit for representing various colors, and may, for example, include a red pixel R, a white pixel W, a blue pixel R and a green pixel G as shown in FIG. 4” – hereinafter ‘SP1-4’), and the forming a plurality of pixel units (PX) comprises forming, at each sub-pixel (SP1-4).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the pixel unit and sub-pixel structure as taught by Seong into Tang.
An ordinary artisan would have been motivated to use the known technique of Seong in the manner set forth above to produce the predictable result of [0003] – “A pixel constituting a light emitting display apparatus includes a light emitting element, and transistors and a capacitor for driving the light emitting element.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Tang and Seong do not expressly disclose the other limitations of claim 20.
However, in an analogous art, Tomiyasu teaches
wherein a thickness of the light-shielding layer (17 – Fig. 11(c) – [0096] –
“light-blocking metal film (third conductive film) 17 (e.g., thickness: about 50-300 nm)”) is greater than a thickness of the functional layer (16 – Fig. 11(c) – [0096] – “a transparent conductive film (second conductive film) 16 (e.g., thickness: about 50-200 nm) of, for example, ITO, IZO, etc”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the light-shielding layer structure as taught by Tomiyasu into Tang and Seong.
An ordinary artisan would have been motivated to use the known technique of Tomiyasu in the manner set forth above to produce the predictable result of [0033] – “In the present invention, the entirety of each of source lines, the entirety of each of source electrodes, and the entirety each of drain electrodes are provided on the corresponding one of oxide semiconductor layers. Therefore, a TFT formed of an oxide semiconductor having satisfactory characteristics can reliably operate normally, and a TFT substrate including the TFTs can be manufactured using a smaller number of photomasks at lower cost. As a result, a TFT substrate, and in addition, a liquid crystal display device can be manufactured at lower cost without a decrease in manufacturing efficiency and yield.”
Tang, Seong, and Tomiyasu do not expressly disclose the other limitations of claim 20.
However, in an analogous art, Kong teaches
wherein the first electrode (151 – Fig. 3 – [0094] – “storage capacitor 150
includes a first capacitor electrode 151”) of the storage capacitor (150 – Fig. 3 – [0086] – “storage capacitor 150”) and the second electrode (152 – Fig. 3 – [0086] – “the second capacitor electrode 152 of the storage capacitor 150”) of the storage capacitor (150) are respectively connected ([0096] – “the first capacitor electrode 151 may be electrically connected to the first gate electrode 121”) to a gate electrode (121 – Fig. 3 – [0071] – “first transistor 120 includes a first gate electrode 121”) of the driving transistor (120 – Fig. 3 – [0071] – “The first transistor 120 is disposed in the non-emission area NEA of each of the red sub-pixel SPR, the white sub-pixel SPW, the blue sub-pixel SPB, and the green sub-pixel SPG” – this corresponds to the drive transistor) and ([0086] – “the second capacitor electrode 152 of the storage capacitor 150 may be a sensing transistor SET”) a second electrode (142 – Fig. 3 – [0088] – “third source electrode 142 may be electrically connected to the second capacitor electrode 152 forming the storage capacitor 150”) of the sensing transistor ([0086] – “sensing transistor SET”), so as to store voltage signals;
wherein a part of the functional layer (RBL2 – Fig. 3 – [0121] – “the reference
branch line RBL may be conductive as it has the stack structure of the semiconductor layer RBL1 and the transparent oxide layer RBL2” – this corresponds to a functional layer) forms a first functional region (Fig. 3 annotated, see below – hereinafter ‘FFR’) of the sensing transistor (140 – Fig. 3 – [0124] – “the reference branch line RBL includes an active layer forming the channel of the sensing transistor SET where it overlaps with the first bridge line GBL1. As a result, the first bridge line GBL1 branching off from the gate line GL and extended to overlap with the reference branch line RBL may work as the third gate electrode 141, the active layer disposed under the first bridge line GBL1 may work as the third active layer 144, and the conductive region including the transparent oxide layer RBL2 under the second bridge line GBL2 may work as the third drain electrode 143” – this describes transistor 140 as the sensing transistor SET);
wherein the first functional region (FFR) comprises a first functional sub-
region (Fig. 3 annotated, see below – hereinafter ‘FFRS1’) located at a first electrode (142 – Fig. 3 – [0124] – “The third transistor 140 includes a third gate electrode 141, a third source electrode 142, a third drain electrode 143 and a third active layer 144”) of the sensing transistor (140) and a second functional sub-region (Fig. 3 annotated, see below – hereinafter ‘FFRS2’) located at a second electrode of the sensing transistor (143 – Fig. 3 – [0124] – “The third transistor 140 includes a third gate electrode 141, a third source electrode 142, a third drain electrode 143 and a third active layer 144”).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate functional region structure as taught by Kong into Tang, Seong, and Tomiyasu.
An ordinary artisan would have been motivated to use the known technique of Kong in the manner set forth above to produce the predictable result [0125] – “so that the aperture ratio can be improved and the repair process of the reference branch line RBL can proceed. As a result, the aperture ratio can be increased without any additional metal layer.”
Tang, Seong, Tomiyasu, and Kong do not expressly disclose the other limitations of claim 20.
However, in an analogous art, Jang teaches
wherein a part of the light-shielding layer (LS – Fig. 3 – [0092] – “reference
bridge lines VREF_B1 and VREF_B2 may be formed by a light shielding layer LS”) forms a first conductive connection part (VREF_B1 – Fig. 8 – [0092] – “reference bridge lines VREF_B1” – this is a connection part).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the light-shielding layer structure as taught by Jang into Tang, Seong, Tomiyasu, and Kong.
An ordinary artisan would have been motivated to use the known technique of Jang in the manner set forth above to produce the predictable result of [0008] “to provide a light emitting display device that may improve an aperture ratio in a limited space of a subpixel and perform a repair process in response to various types of defects.”
Tang, Seong, Tomiyasu, Kong, and Jang do not expressly disclose the other limitations of claim 20.
However, in an analogous art, Park teaches
the first functional sub-region (Fig. 2 – [5:51-53] – “second transistor (SENT) may be a sensing transistor, and may include a second gate electrode 252 and a second source electrode 256b/second drain electrode 256a”}) is electrically connected to the first electrode of the storage capacitance ([5:53-55] – “One end of the second transistor (SENT) is connected to a storage capacitor (Cstg)”), and the first conductive connection part (254 – Fig. 2 – [5:37-40] – “the eighth line 254 may be connected to the third line 260c, which is a reference voltage line, and a contact hole, so as to supply a reference voltage to adjacent sub-pixels”) is configured to electrically connect the second functional sub-regions of the sensing transistors (Fig. 2 – [5:51] – “second transistor (SENT)”) of different sub-pixels (Fig. 2 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the sub-region connection structure as taught by Park into Tang, Seong, Tomiyasu, Kong, and Jang.
An ordinary artisan would have been motivated to use the known technique of Park in the manner set forth above to produce the predictable result of a display device with elements connect through a display substrate.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Tang in view of Seong, Tomiyasu, Kong, Jang, Park, and Long (US 20200294446 A1 – hereinafter Long).
Regarding claim 7, Tang, as modified by Seong, Tomiyasu, Kong, Jang, and Park, teaches claim 5 from which claim 7 depends. Tang further teaches
the first via hole (60).
Tang, Seong, Tomiyasu, Kong, Jang and Park do not expressly disclose the other limitations of claim 7.
However, in an analogous art, Long teaches
(Original) The display substrate according to claim 5, wherein the first
electrode or the second electrode (EMn – Fig. 3 – [0051] – “T6 is electrically coupled to the light-emitting control signal line EMn” – this corresponds to a second electrode) of the sensing transistor (T6 – Fig3 – [0051] – “second light-emitting control transistor T6” – this the sensing transistor) is electrically connected to the first functional region (500 – Fig. 3 – [0044] – “active layer 500” – this corresponds to the first functional region) through the first via hole.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the sensing transistor electrical connections as taught by Long into Tang, Seong, Tomiyasu, Kong, Jang and Park.
An ordinary artisan would have been motivated to use the known technique of Long in the manner set forth above to produce the predictable result of [0003] – “A display substrate generally includes a plurality of pixel units, each of which has a pixel circuit therein. By supplying a signal to the pixel circuit in each pixel unit, the pixel unit can be driven to emit light.”
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Tang in view of Seong, Tomiyasu, Kong, Jang, Park, and Shim et al. (US 20180061908 A1 – hereinafter Shim).
Regarding claim 14, Tang, as modified by Seong, Tomiyasu, Kong, Jang, and Park, teaches claim 10 from which claim 14 depends. Tang, Tomiyasu, Kong, Jang, and Park do not expressly disclose the limitations of claim 14.
However, in an analogous art, Shim teaches
(Original) The display substrate according to claim 10, wherein a part of the
functional layer (ACT1 – Fig. 6 – [0070] – “The first semiconductor layer ACT1 and the third semiconductor layer ACT3 are positioned on the buffer layer BUF and may be formed of a silicon semiconductor or an oxide semiconductor” – it is interpreted that these are the same layer) forms a third conductive connection part (ACT3 – Fig. 6 – [0075] – “The third semiconductor layer ACT3 of the driving transistor DR”), and the third conductive connection part (ACT3) is configured to electrically connect the first electrode with the first functional sub-region (FFSR) of the sensing transistor (ST – Fig. 6 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the electrical connection structure as taught by Shim into Tang, Tomiyasu, Kong, Jang, and Park.
An ordinary artisan would have been motivated to use the known technique of Shim in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 15, Tang, as modified by Seong, Tomiyasu, Kong, Jang, Park, and Shim, teaches claim 14 from which claim 15 depends. Tang, Seong, Tomiyasu, Kong, Park, and Shim do not expressly disclose the other limitations of claim 15.
However, in an analogous art, Jang teaches
(Previously Presented) The display substrate according to claim 14,
wherein a width of the third conductive connection part (24) in a length direction of the third conductive connection part (24) is greater than a width of the first conductive connection part (VREF_B1) in a length direction of the first conductive connection part (VREF_B1 – Fig. 3 shows this); and
wherein a width of the third conductive connection part (24) in the length direction of the third conductive connection part (24) is greater than a width of the second conductive connection part (VREF_H) in a length direction of the second conductive connection part (VREF_H – Fig. 3 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the conductive connection part width structure as taught by Jang into Tang, Seong, Tomiyasu, Kong, Park, and Shim.
An ordinary artisan would have been motivated to use the known technique of Jang in the manner set forth above to produce the predictable result as stated above in claim 1.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Tang in view of Seong, Tomiyasu, Kong, Jang, Park, and Ou (US 20240155888 A1 – hereinafter Ou).
Regarding claim 17, Tang, as modified by Seong, Tomiyasu, Kong, Jang, and Park, teaches claim 10 from which claim 17 depends. Tang further teaches
the first via hole (60) on the base substrate (10) is located in
the first overlap sub-region (Fig. 10 annotated, see below – hereinafter ‘B1’).
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Tang, Seong, Tomiyasu, Kong, Jang, and Park do not expressly disclose the other limitations of claim 17.
However, in an analogous art, Ou teaches
(Original) The display substrate according to claim 10, wherein the
second overlap region (200 – Fig. 2 – [0054] – “overlapping area 200”) comprises a first overlap sub-region (202 – Fig. 2 – [0054] – “overlapping areas 202”) and a second overlap sub-region (201 – Fig. 2 – [0054] – “overlapping areas 201”), an area of the first overlap sub-region (202) is greater than an area of the second overlap sub-region (201 – Fig. 2 shows this), and the orthographic projection of the first via hole on the base substrate is located in the first overlap sub-region.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the overlap sub-region area as taught by Ou into Tang, Seong, Tomiyasu, Kong, Jang, and Park.
An ordinary artisan would have been motivated to use the known technique of Ou in the manner set forth above to produce the predictable result to [0018] – “provides a display substrate, a method for fabricating the same, and a vapor deposition apparatus. A light-emitting functional layer and a cathode layer of the display substrate can be fabricated by the vapor deposition apparatus using one same mask, and an electrode layer in a display area normally overlaps signal wires in first overlapping areas, which greatly reduces a fabricating cost of the display substrate.”
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Tang in view of Seong, Tomiyasu, Kong, Jang, Park, Ou, Feng et al. (US 20230033702 A1 – hereinafter Feng), and Kim (US 20210202645 A1 – hereinafter Kim).
Regarding claim 18, Tang, as modified by Seong, Tomiyasu, Kong, Jang, Park, and Ou, teaches claim 17 from which claim 18 depends. Tang, Seong, Tomiyasu, Kong, Jang, Park, and Ou do not expressly disclose the limitations of claim 18.
However, in an analogous art, Feng teaches
(Original) The display substrate according to claim 17, wherein the second
overlap region comprises a first electrode overlap region located at the first electrode of the sensing transistor (T3 – [0465] – “sensing transistor T3”), and a second electrode overlap region located at the second electrode of the sensing transistor ([0465] – “Light-shielding layers 23 may be electrically connected to respective source-drain conductive layers of the switching transistor T1, the driving transistor T2, and the sensing transistor T3 to form structures similar to upper-lower double channels, so as to improve electrical performances of the transistors” – this describes overlap regions where the light shield is placed in a pattern overlapping the source/drain electrodes of the sensing transistor that corresponds to the described elements ‘Bx’ and ‘By’ of the instant application) ; and
wherein the first electrode overlap region and the second electrode overlap
region have a proportionally same shape.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the overlap region area as taught by Feng into Tang, Seong, Tomiyasu, Kong, Jang, Park, and Ou.
An ordinary artisan would have been motivated to use the known technique of Feng in the manner set forth above to produce the predictable result to [0465] – “to improve electrical performances of the transistors.”
Tang, Seong, Tomiyasu, Kong, Jang, Park, Ou, and Feng do not expressly disclose the other limitations of claim 18.
However, in an analogous art, Kim teaches
wherein the first electrode overlap region and the second electrode overlap
region have a proportionally same shape ([0054] – “the lower-surface light shield layer BLS has a square shape is illustrated, this may be changed depending on a shape of the semiconductor layer ACT of the driving transistor DT, or the like” – this is interpreted that the overlap regions would be the same shape for the source and drain of the same transistor).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the shape of region area as taught by Kim into Tang, Seong, Tomiyasu, Kong, Jang, Park, Ou, and Feng.
An ordinary artisan would have been motivated to use the known technique of Kim in the manner set forth above to produce the predictable result to ease manufacturing and reduce cost by making the pattern the same shape and size.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Tang in view of Seong, Tomiyasu, Kong, Jang, Park, and Liu et al. (US 20200273923 A1 – hereinafter Liu).
Regarding claim 19, Tang, as modified by Seong, Tomiyasu, Kong, Jang, and Park, teaches claim 1 from which claim 19 depends. Tang, Seong, Tomiyasu, Kong, Jang, and Park do not expressly disclose the limitations of claim 19.
However, in an analogous art, Liu teaches
(Previously Presented) The display substrate according to claim 1, wherein the light-shielding layer ([0068] – “metal layer on the base substrate to serve as a light shielding layer, a material of which may be selected from conductive metal materials capable of shielding light, such as AlNd/Mo”) comprises an opaque metal conductive material; and
wherein the functional layer (110 – [0048] – “the active layer 310 may be formed using an IGZO (Indium Gallium Zinc Oxide) material, and accordingly, the auxiliary connection member 110 may be formed using a conductorized IGZO material” – this corresponds to a functional layer) comprises a light-transmitting metal oxide material.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the materials of the light shielding and functional layer structure as taught by Liu into Tang and Seong.
An ordinary artisan would have been motivated to use the known technique of Liu in the manner set forth above to produce the predictable result of [0004] – “As the size of the display panel increases, the IR drop of the plate electrode during display may cause the brightness of the display panel to be uneven” thus requiring a thicker light-shielding layer.
Pertinent Art
For the benefits of the Applicant, US 20230230533 A1 and US 20210359211 A1
are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the combination of limitations including the conductive layer structure.
Conclusion
Any inquiry concerning this communication or earlier communications from the
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/GRA/
Examiner, Art Unit
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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