Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness
rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed
invention is not identically disclosed as set forth in section 102, if the differences between
the claimed invention and the prior art are such that the claimed invention as a whole would have been
obvious before the effective filing date of the claimed invention to a person having ordinary skill in the
art to which the claimed invention pertains. Patentability shall not be negated by the manner in which
the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35
U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claims 1-11 are rejected under 35 U.S.C. § 103 as being unpatentable over Huang et al (US 2010/0094440) in view of Liu et al (US 2020/0358907).
Huang discloses an audio acquisition and reproduction module, referred to as the “externally-connected audio apparatus 30,” comprising an electronic component integrating multiple functional blocks (Fig. 3; ¶[0030]).
Huang further discloses a universal serial bus digital (USB) audio interface for audio signals, wherein “the interface control unit 301 is realized as a controller of the universal serial bus (USB)” which connects the apparatus to a computer system 32 (¶[0031]).
The apparatus includes a programmable computing unit (audio interface module 307 as shown in fig. 3 or the microprocessor (MCU) 505/Audio interface unit 507 as shown in fig. 5 of Huang) configured by a control link accessible via the USB audio interface, comprising at least one processor implementing a plurality of audio signal processing operations. For example, the “digital audio interface unit 371” processes digital audio signals and communicates with the host computer via the USB interface (¶[0031]–[0032]). Configuration via the control link is inherent because that is how such USB audio devices operate. It is also inherent that the control link is bidirectional which enables control and parameterization of the signal processing operations because that is how such USB audio devices operate (e.g., Huang shows the data communication between the audio interface module 307 and the USB audio interface 301 is bidirectional (see the bidirectional link shown between the USB Interface 301 and audio interface module 307 and memory control unit 309 in fig. 3 & see paragraphs [0031]-[0035]; the bidirectional link shown between the USB Interface 401 and audio interface module 405 and memory control unit 309 in fig. 4 & see paragraphs [0037]-[0042]; the bidirectional link shown between the USB Interface 501 and microprocessor (MCU 505) and audio interface module 507 and memory control unit 509 in fig. 5 & see paragraphs [0043]-[0044] and [0050-0053].
Huang discloses at least one analog/digital conversion unit for acquisition and reproduction of analog audio signals in the “analog audio interface unit 373,” which “performs conversion between digital and analog signals, including the conversion of digital signals received from the computer system 32 into analog signals” and “receives external analog signals and converts them into digital signals” (¶[0032]).
Additionally, Huang discloses at least one reconfigurable analog interface, as the audio interface module 307 includes analog ports connected to earphones, speakers, and microphones, enabling connection with various analog audio devices (¶[0031]–[0032]). Similarly, the digital audio interface unit 371 connects to external digital audio sources or devices, serving as a reconfigurable digital interface (¶[0032]).
Huang does not disclose that the audio apparatus is implemented using System-on-a-Module (SoM) or System-on-a-Chip (SoC) technology, However, integrating an electronic component apparatus using SoM/SoC technology and placing electronic components on a single printed circuit board was a known design choice to reduce size, cost, and power consumption as evidenced by Liu (see SoM 202 and SoC 204 as shown in fig. 2, paragraph 0019 and 0021 of Liu). Thus it would have been obvious to a person of ordinary skill in the art to implement Huang’s apparatus using SoM/SoC technology as suggested by Liu, with a reasonable expectation of success, because such modifications involve the predictable use of prior art elements according to their established functions so that known benefits such as reducing size, cost and power consumption can be achieved.
Regarding claim 2, Huang as modified meets the limitations for the following reason: Huang teaches “The circuit for processing digital audio signals is specified by some digital audio transmission interfaces, such as I2S (Inter-IC Sound), SPDIF (Sony/Philips Digital Interconnect Format), and DSD (Direct Stream Digital)” (see paragraph 0025 of Huang) (note: the micro-control unit of Huang inherently will have to have the ability to do audio data compression/decompression so that audio data in compression or decompression format can be processed effectively) , “In one preferred embodiment, the externally-connected audio apparatus 40 includes a micro-control unit (MCU) which may provide more functions for signal processing in addition to original process. For example, the MCU may performs volume control, audio analog-digital conversion, and power management. In another preferred embodiment, the circuit forming the audio interface module shown in FIG. 3 and FIG. 4, or forming the analog-digital converter of the audio interface module may be included in the MCU, and use the buffer memory inside” (see paragraph 0041 of Huang).
Regarding claim 3, since the MCU taught by Huang (see paragraphs 0041-0043) is a micro-controller which incorporates a programmable CPU (central processing unit), and some circuitry that implements peripheral functionalities, thus each processing operation carried out by the MCU of Huang is inherently carried out as executable program code that is modifiable.
Regarding claim 4, note the discussion of the rejection of claim 1, the USB audio interface and the programmable computing unit of Huang as modified would have met the claim limitation for the same reason as set forth in the rejection of claim 1.
Regarding claim 5, Huang as modified meets the limitations for the following reason: Huang teaches “The circuit for processing digital audio signals is specified by some digital audio transmission interfaces, such as I2S (Inter-IC Sound), SPDIF (Sony/Philips Digital Interconnect Format), and DSD (Direct Stream Digital)” (see paragraph 0025 of Huang) (note: the micro-control unit of Huang inherently will have to have an encoder/decoder component in order to have the ability to encode/decode audio signals into different data formats effectively).
Regarding claim 6, the device of Huang as modified includes at least one analog input interface and at least one analog output interface (see figs. 3-5 of Huang).
Regarding claim 7, note the discussion of the rejection of claim 1, the device of Huang as modified by Liu would have met the claim limitation since the apparatus of Huang as modified by Liu would have had implemented the audio acquisition and reproduction module with SoM and SoC technology and SoM technology inherently comprises power supply control stages.
Regarding claim 8, the arrangement of components arranged on a board in a compact manner to minimize unoccupied surfaces on the board would have been an obvious design choice. Optimizing board size impacts manufacturing costs, product dimensions, and even performance factors like signal integrity. Design factors such as component size and spacing; layer stackup; routing complexity; enclosure constraints; thermal considerations; and other factors like electromagnetic interference (EMI) shielding, panelization requirements, and serviceability influence the amount of unoccupied space on a board. Hence the arrangement as claimed would have been a design choice based on the above enumerated design choices to yield a compact layout of components on a board.
Regarding claim 9, note the discussion of the rejection of claim 1, the device of Huang as modified would have met the claim limitation since the apparatus of Huang as modified by Liu would have had implemented the audio acquisition and reproduction module with SoM and SoC technology.
Regarding claim 10, Huang teaches a device with audio acquisition and reproduction capabilities, comprising: a host processor (e.g., the computer system 32 as shown in fig. 3 inherently contains a host processor); and at least one audio acquisition and reproduction module (audio module 30 as shown in fig. 3) according to claim 1, connected via a universal serial communication bus, called a USB communication bus (see fig. 3 and paragraph 0030-0031).
Regarding claim 11, Huang teaches a device with audio acquisition and reproduction capabilities, comprising: a host processor (e.g., the computer system 32 as shown in fig. 3 inherently contains a host processor); at least one such audio acquisition and reproduction modules (audio module 30 as shown in fig. 3) according to claim 1; and an interconnection module as per the USB standard, said audio acquisition and reproduction modules being connected to said host processor via the interconnection module (note: it is inherent that there is a USB hub (i.e., a USB standard interconnection module) in the computer system of Huang in order to provide interconnection between the host processor of computer system 32 and other USB devices such as the audio module 30 as shown in fig. 3). Although Huang does not show the device contains more than one audio acquisition and reproduction modules, official notice is taken that it is well known in the art that a host computer system can have multiple USB ports so that multiple USB devices such as multiple audio modules as taught by Huang can be connected to the host processor of the host computer system based on designer’s preference and needs. Thus it would have been obvious that the device of Huang as modified by Liu could have been further modified to include more than one USB ports so that one additional audio acquisition and reproduction module could have been connected to the device based on designer’s preference and needs which produces no unexpected results.
Response to applicant’s arguments
Applicant’s arguments with respect to the newly added limitations “the control link being bidirectional and enabling control and parameterization of the signal processing operations” will make claim(s) 1-11 patentably distinct have been fully considered but are found not persuasive because a new ground(s) of rejection has been made as set forth above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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should be directed to Supervisory Patent Examiner VIVIAN CHIN whose telephone number is (571)272-
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/VIVIAN C CHIN/
Supervisory Patent Examiner, Art Unit 2695