DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 02/27/26 have been fully considered but they are not persuasive. The applicant argues that prior art of Ito does not read on the applicant claimed invention since Figure 1 of Ito discloses a coil component having a second wiring layer 21, a first wiring layer 24, a first intermediate wiring layer 22 and a second intermediate wiring layer 23. By having this configuration, it cannot be said that the number of turns of the first wiring layer 24 is greater than the number of turns of the second wiring layer 21 because the wiring layer 24 has four turns whereas the second wiring layer has 8 turns and it cannot be said that Ito discloses that "at least a portion of the second wiring layer is wider than at least a portion of the first wiring layer" as seen in Ito Figure 1. The examiner respectfully disagrees with the interpretation of Ito.
As previously mentioned in the office action sent out on 01/13/26 and shown in the rejection below, Furui et al. (figures 1-4 and para 0024-0070) discloses wherein the coil portion includes a plurality of wiring layers (see figures 3-4 and para 0046-0049) laminated on the substrate (3), the plurality of wiring layers includes a first wiring layer (4c), a second wiring layer (4a) having a plurality of tuns and a first intermediate wiring layer (4b) having a plurality of turns which is shown in (see figure 4) of Furui et al.
As clearly pointed in the previous rejection and the rejection below, Ito figure 1 discloses at least a portion of the second wiring layer (24) (note: the coil 34 is on layer 24) in which is layer 24 has a coil 34 that is wider than at least a portion of the first wiring layer 21 (note: the coil 31 is on layer 21). The examiner did not suggest that second wiring layer is 21, and a first wiring layer 24. The rejection shows that the second wiring layer is 24/34, and a first wiring layer 21/31. Which clearly meets the claimed limitations wherein the number of turns of the first wiring layer 21 is greater than the number of turns of the second wiring layer 24 and at least a portion of the second wiring layer 24 is wider than at least a portion of the first wiring layer 21 and the first intermediate wiring layer 22/32 is greater than the winding number of the second wiring layer. Accordingly, the rejection will remain in the office action.
The applicant also argues that the specification describes the following relationship: W1<W2<W3<W4<W5, which indicates that the width of the wire layers narrow at each turn. Ito does not disclose such a feature, nor do Furui and Schmelzer. The examiner respectfully disagrees.
Claim 1 in its current form does point out nor suggest structural features of W1<W2<W3<W4<W5, which indicates that the width of the wire layers narrow at each turn. The claim only mentions that the number of turns of the first wiring layer is greater than the number of turns of the second wiring layer, the first intermediate wiring layer is greater than the winding number of the second wiring layer and the first wiring layer and the intermediate wiring layers are provided in parallel to each other. The combinations of Furui, Ito and Schmelzer have these teaching. Accordingly, the rejection will remain in the office action.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
1 Claims 1-2, 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Furui et al. (US 20160035478) in view of Ito et al. (WO 2017104309) and Schmelzer et al. (US 20140347154)
Regarding claim 1, Furui et al. (figures 1-4 and para 0024-0070) discloses wherein the coil portion includes a plurality of wiring layers (see figures 3-4 and para 0046-0049) laminated on the substrate (3), the plurality of wiring layers include a first wiring layer (4c) having a plurality of turns to define a wound configuration on a first surface side of the substrate (see figure 4), a second wiring layer (4a) having a plurality of tuns to define a wound configuration on a second surface side of the substrate relative to the first wiring layer (see figure 4), and a first intermediate wiring layer (4b) having a plurality of turns to define a wound configuration and disposed on the first surface side of the substrate relative to the second wiring layer (see figure 4), the first surface of the substrate is in contact with a heat dissipation portion (10) (see para 0041) and supported by the heat dissipation portion (see figure 4).
Furui et al. (figure 4) discloses an intermediate wiring layer and the first wiring layer and the intermediate wiring layer are provided in parallel to each other, but does not disclose at least a portion of the second wiring layer is wider than at least a portion of the first wiring layer, a number of turns of the first wiring layer is greater than a number of turns of the second wiring layer, a number of the first intermediate wiring layer is greater than the number of turns of the second wiring layer and the first wiring layer and the intermediate wiring layer is provided in parallel to each other.
Furui et al. (para 0041-0042) also discloses a heat dissipation material of the heat dissipation portion in contact with the first surface but does not expressly disclose wherein a heat dissipation material of the heat dissipation portion in contact with the first surface has a higher thermal conductivity than an insulating layer forming the substrate.
Ito et al. (figures 1-4 and pages 2-5) at least a portion of the second wiring layer (34) is wider than at least a portion of the first wiring layer (21/31), the winding number of the first wiring layer is greater than the winding number of the second wiring layer (see figure 1), the winding number of each of the first intermediate wiring layer (22/32) is greater than the winding number of the second wiring layer (24/34) and the first wiring layer and the intermediate wiring layers are provided in parallel to each other.(see figure 1)
Schmelzer et al. (figures 1-8a and para 0030/0043) discloses a teaching a heat dissipation material of the heat dissipation portion in contact with the first surface has a higher thermal conductivity than an insulating layer forming the substrate. (see para 0043).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the applicant claimed invention to design a plurality of intermediate wiring layers; at least a portion of the second wiring layer is wider than at least a portion of the first wiring layer, the winding number of the first wiring layer is greater than the winding number of the second wiring layer, the winding number of each of the first intermediate wiring layer is greater than the winding number of the second wiring layer and the first wiring layer and the intermediate wiring layers are provided in parallel to each other as taught by Ito et al. to the inductive device of Furui et al. so as to allow for a higher inductance to be obtained while also allowing for improved characteristic of increasing the magnetic flux density generated on the specific surface side of the multilayer body without increasing the conductor loss while suppressing an increase in the conductor loss.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the applicant claimed invention to design wherein a heat dissipation material of the heat dissipation portion in contact with the first surface has a higher thermal conductivity than an insulating layer forming the substrate as taught by Schmelzer et al. to the inductive device of Furui et al. so as to move heat quickly away from hot spots in the inductive device, thereby preventing damage and ensure stable operation.
Regarding claim 2, Ito et al. (figure 3) discloses wherein the first wiring layer (31a) includes one or more first conductor patterns that are continuous with a constant width the second wiring layer (34a) includes one or more second conductor patterns that are continuous with a constant width, and the constant width of all of the second conductor patterns of the second wiring layer is larger than the constant width of the all of the first conductor patterns of the first wiring layer.(see figure 3)
Regarding claim 5, Ito et al. (figures 2/4) discloses wherein at least one of the first wiring layer (31 or 31a) and the second wiring layer (34/34a) includes a first annular pattern provided in an annular shape, and a second annular pattern provided in an annular shape on the outer side relative to the first annular pattern (see figures 2/4), and at least a portion of the second annular pattern is wider than at least a portion of the first annular pattern. (see figures 1-4).
Regarding claim 7, Ito et al. (figures 2/4) discloses wherein at least one of the first wiring layer (31 or 31a) and the second wiring layer (34/34a) includes a first annular pattern provided in an annular shape, and a second annular pattern provided in an annular shape on the outer side relative to the first annular pattern (see figures 2/4), and at least a portion of the second annular pattern is wider than at least a portion of the first annular pattern. (see figures 1-4).
2 Claims 6 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Furui et al. (US 20160035478) in view of Ito et al. (WO 2017104309) and Schmelzer et al. (US 20140347154) in further view of Gamou et al. (US 6,847,284)
Regarding claim 6, Furui et al. (figures 1-4 and para 0024-0070) discloses all the limitations as noted above but does not expressly disclose wherein a second intermediate wiring layer having a plurality of turns to define a wound configuration, and the second intermediate wiring layer is connected in parallel to at least one of the first wiring layer and the second wiring layer.
Gamou et al. (figures 7-11 and Col 14, lines 44-50) discloses a teaching wherein the plurality of wiring layers include a second intermediate wiring layer (23) with a wound configuration, and the other wiring layer is connected in parallel to at least one of the first wiring layer (21) and the second wiring layer.(see also figures 41-47 and Col 26, lines 15-25 disclosing a teaching of additional windings added to the inductive device)
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the applicant claimed invention to design wherein the plurality of wiring layers include a second intermediate wiring layer with a wound configuration, and the a second intermediate wiring layer is connected in parallel to at least one of the first wiring layer and the second wiring layer as taught by Gamou et al. to the modified inductive device of Furui et al. so as to allow for increased power/output, improved longevity of consistent voltage and help reduce heat stress.
Regarding claim 8, Furui et al. (figures 1-4 and para 0024-0070) discloses all the limitations as noted above but does not expressly disclose wherein a second intermediate wiring layer having a plurality of turns to define a wound configuration, and a second intermediate wiring layer is connected in parallel to at least one of the first wiring layer and the second wiring layer.
Gamou et al. (figures 7-11 and Col 14, lines 44-50) a teaching wherein the plurality of wiring layers include a second intermediate wiring layer (23) with a wound configuration, and the other wiring layer is connected in parallel to at least one of the first wiring layer (21) and the second wiring layer.(see also figures 41-47 and Col 26, lines 15-25 disclosing a teaching of additional windings added to the inductive device)
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the applicant claimed invention to design a teaching wherein the plurality of wiring layers include a second intermediate wiring layer with a wound configuration, and the other wiring layer is connected in parallel to at least one of the first wiring layer and the second wiring layer as taught by Gamou et al. to the modified inductive device of Furui et al. so as to allow for increased power/output, improved longevity of consistent voltage and help reduce heat stress.
Regarding claim 9, Furui et al. (figures 1-4 and para 0024-0070) discloses all the limitations as noted above but does not expressly disclose wherein a second intermediate wiring layer having a plurality of turns to define a wound configuration, and a second intermediate wiring layer is connected in parallel to at least one of the first wiring layer and the second wiring layer.
Gamou et al. (figures 7-11 and Col 14, lines 44-50) a teaching wherein the plurality of wiring layers include a second intermediate wiring layer (23) with a wound configuration, and the other wiring layer is connected in parallel to at least one of the first wiring layer (21) and the second wiring layer.(see also figures 41-47 and Col 26, lines 15-25 disclosing a teaching of additional windings added to the inductive device)
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the applicant claimed invention to design a teaching wherein the plurality of wiring layers include a second intermediate wiring layer with a wound configuration, and the other wiring layer is connected in parallel to at least one of the first wiring layer and the second wiring layer as taught by Gamou et al. to the modified inductive device of Furui et al. so as to allow for increased power/output, improved longevity of consistent voltage and help reduce heat stress.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RONALD HINSON whose telephone number is (571)270-7915. The examiner can normally be reached M to F; 8 -5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Shawki Ismail can be reached at 571-272-3985. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/RONALD HINSON/Primary Examiner, Art Unit 2837
Prosecution Insights