DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for domestic priority under 35 U.S.C. 120. The PCT Application Number PCT/CN2022/077130, being filed on February 21, 2022.
Information Disclosure Statement
The information disclosure statements filed August 24, 2023 have been submitted for consideration by the Office. It has been placed in the application file and the information referred to therein has been considered.
Applicants must continue to submit prior art references throughout the patent application process. A supplemental IDS must be submitted if prior art is discovered through a foreign patent application or an International Patent Search, or a related application before a prosecution closes.
Election/Restrictions
Applicant's election of Group I, Species A2 and B1 encomssing claims 1-14 and 16-17 based on original claims with traverse of in the reply filed on June 13, 2025 is acknowledged. The traversal is on the ground(s) that all it would not be an undue burden for the Examiner to search all four claim groups and species. This is not found persuasive because
Applicant’s arguments based on search burden as mention would not be considered proper because restriction is based on PCT unity of invention, thefore, incorrect or inappropriate arguments are presented.
And under PCT rule 13.1, restriction requirement clearly mentions why restriction is proper based on lacking special technical features (see explanation in the context of prior art in the restriction requirement) in view of prior art mentioned (see further MPEP PCT Rule). The expression “special technical features” shall mean those technical features that define a contribution which each of the claimed inventions, considered as a whole, makes over the prior art. a "special technical feature" in the context of prior art refers to a specific technical aspect of an invention that represents a unique contribution over existing technology, meaning it is not found in the prior art and defines what makes the invention novel and potentially patentable; It appears that applicant defining all features as common features, if all features as common features, then no novelty exists, and the claim or invention is unpatentable. Claims 18-20 are withdrawn from further consideration as being drawn to a nonelected subject matter or species. Additionally claims 2-6, 12-13, 16 are further withdrawn as being drawn to a nonelected subject matter or species because Claims 5-6 are further withdrawn because third connection pad K3 which connect to first connection pad K1 is part of non-elected figure 3A; additionally claim 6 depends on claim 5 and moreover having forth connection pad K4 as mentioned in figure 3B not because third connection pad K3 which connects to first connection pad K1 not first connection pad K2; therefore Claims 5-6 are withdrawn. Also, claims 2-4,6 and 12-13, 16 has at least one limitation mentioned by “in a case” or “Or” that independently read on non-elected species., Therefore, these claims are further withdrawn. Note that rejection is given below under USC 103 to advance prosecution. Examiner strongly suggests when any changes made to claims from prior submitted claims, claims should be submitted again in the reply for consistency throughout the prosecution.
Claim Objections
Claim 1 is objected to because of the following informalities:
Objection of claim 1, claim 1’s preamble mentions that “a wiring board” includes a mother board and a daughter board which appears to be two different wiring boards. Therefore, preamble “a wiring board” is inappropriate. Proper preamble would be such as “ wiring board assembly” or similar.
Appropriate correction is required.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 or 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AlA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Note: The rejection under USC 103 below some of the withdrawn claims are given to advance prosecution; however, proper clarification or amendment is required to consider the rejection under USC 103.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7-9, 14, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Adachi et al. (US6025901, herin referred to as Adachi).
Rejection of claim 1, Adachi discloses a wiring board (see figures 13A-14 of Adachi) comprising:
a mother board (1 ) and a daughter board (135) that are stacked; and at least one side wiring (226); wherein the mother board includes a first substrate and a first wiring layer disposed on the first substrate, and the first wiring layer includes at least one first connection pad (see a first wiring layer on surface of substrate 135 has connection pad 136 on a substrate 1 in figure 13A)); the daughter board is disposed on a side of the first substrate away from the first wiring layer (see board 135 is disposed on a side of the substrate 1 away from the first wiring layer in figure 14); the daughter board includes a second substrate and a second wiring layer disposed on the second substrate, and the second wiring layer includes at least one second connection pad (see terminal 134 as connection pad included on substrate 1) ; wherein the at least one side wiring is connected, via a respective end thereof, to the at least one first connection pad in one-to-one correspondence, and the at least one side wiring is connected, via respective another end thereof, to the at least one second connection pad in one-to-one correspondence (see figure 14);
Adachi discloses the mother board and the daughter board attached to each other (see figure of 14) but fails to discloses via a bonding layer.
Examine makes official notice that it is old and know that use of adhesive layer between two boards to keep them secure together. Therefore, it would have been obvious to ordinary skill in the art to before the effective filing date of the claimed invention to modify the wiring board to have adhesive layer between two boards as reason mentioned above. since it has been held that forming in one piece an article, which has formerly been formed in two pieces and put together, involves only routine skill in the art. Howard v. Detroit Stove Works, 150 U.S. 164 (1893).
Rejection of claim 7, Adachi discloses the wiring board according to claim 1, wherein the mother board has an active area and a passive area located on a side of the active area; wherein the at least one first connection pad is disposed in the passive area, the daughter board is arranged close to the passive area, and an orthographic projection of the daughter board on the first substrate does not exceed edges of the first substrate (see figure 13b in view of figure 13A wherein daughter board under passive area of connection board; also, see active area at 2 next to passive area where the connection pads are on the first substrate, see edge of substrates of daughter board and mother board are aligned) .
Rejection of claim 8, Adachi discloses the wiring board according to claim 1, wherein the mother board has a shape of a rectangle; and the active area and the passive area are arranged in sequence in a first direction, and the first direction is a direction represented by a long side or a short side of the rectangle (see figure 13b in view of figure 13A); wherein in a case where the first direction is the direction represented by the long side of the rectangle, the at least one side wiring is disposed on a side of the wiring board corresponding to the short side of the rectangle (see figure 13b in view of figure 13A and rejection of claim 7 ); in a case where the first direction is the direction represented by the short side of the rectangle, the at least one side wiring is disposed on a side of the wiring board corresponding to the long side of the rectangle.
Rejection of claim 9, Adachi discloses the wiring board according to claim 1, wherein the at least one second connection pad is arranged close to the passive area; and the at least one first connection pad includes a plurality of first connection pads, and the at least one second connection pad includes a plurality of second connection pads; wherein the plurality of first connection pads are arranged in sequence in a second direction, and the plurality of second connection pads are arranged in sequence in the second direction; each first connection pad is in correspondence with a second connection pad in the plurality of second connection pads connected to this first connection pad in a thickness direction of the second substrate; wherein the second direction is perpendicular to the first direction (Specification mentions that connector electrodes 132 extend on inner surfaces of the cover 131. However, the connector electrodes 132 may be provided at any other positions so long as the connector electrodes 132 can electrically connect the external input terminals 134 and the output terminals 136 to each other, and see 132, 134, and 136 in figures 13A,14, in view of figures 16 wherein direction of arrangement of pads perpendicular to direction of arrangement of active and passive area).
Rejection of claim 14, Adachi discloses the wiring board according to claim 1, wherein a chamfer structure or a rounded corner structure is disposed at a position of the first substrate corresponding to a side of the wiring board where the at least one side wiring is located (see corner of the first substrate in figure 14 of Adachi); and/or a thickness of the bonding layer is in a range of 8 microns to 15 microns, inclusive, and a thickness of the second substrate is in a range of 5 microns to 20 microns, inclusive (note that this part is optional or not required).
Rejection of claim 17, Adachi discloses a functional backplane, comprising: the wiring board according to claim 1; and the at least one electronic element; wherein the at least one electronic element is disposed on the wiring board, and is electrically connected to the first wiring layer in the wiring board (see rejection of claim 1, also specification discloses “A chip-on-glass (COG) method in which an LSI chip for drivers is directly connected to the gate bus terminal or the source bus terminal”; moreover, specification discloses other electronic component electrically connected wiring layer mentioned in 13B such as diver chip, controller..etc.) .
Claims 2-4, 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Adachi and Uchida et al. (US20140332258, hereinafter Uchida).
Rejections of claims 2-4, Adachi discloses the wiring board according to claim 1, but fails to disclose the second wiring layer includes a first sub-layer and a second sub-layer that are respectively disposed on two opposite sides of the second substrate in a thickness direction of the second substrate, and the first sub-layer is closer to the mother board than the second sub- layer; the second sub-layer includes the at least one second connection pad; at least one second via is disposed in the second substrate, and a second connection pad in the at least one second connection pad is electrically connected to the first sub-layer through a second via in the at least one second via (claim 2); an orthographic projection of edges of each second connection pad on the second substrate exceeds an orthographic projection, on the second substrate, of an edge of a corresponding second via proximate to this second connection pad; Anda distance between the orthographic projection of the edges of each second connection pad on the second substrate and the orthographic projection of the edge of the corresponding second via on the second substrate is in a range of 10 microns to 30 microns, inclusive (claims 3- 4).
Uchida discloses the second wiring layer includes a first sub-layer and a second sub-layer that are respectively disposed on two opposite sides of the second substrate in a thickness direction of the second substrate, and the first sub-layer is closer to the mother board than the second sub- layer; the second sub-layer includes the at least one second connection pad; at least one second via is disposed in the second substrate, and a second connection pad in the at least one second connection pad is electrically connected to the first sub-layer through a second via in the at least one second via (claim 2) (see figure 1-3 wherein sub-layers 3 and 4 are opposite side of substrate 2 connected to via portion at 7 passing through substrate 2); an orthographic projection of edges of each second connection pad on the second substrate exceeds an orthographic projection, on the second substrate, of an edge of a corresponding second via proximate to this second connection pad (see orthographic projection of edges pad 4 exceed an orthographic projection, on the second substrate, of an edge of a corresponding second via); and a distance between the orthographic projection of the edges of each second connection pad on the second substrate and the orthographic projection of the edge of the corresponding second via on the second substrate is in a range of 10 microns to 30 microns, inclusive (see paragraph 0060which has w1 40 μm or more and 100 μm or more less and paragraph 0065 which would have the outer diameter W3 of the second land portion 6 is preferably 1.2 times or more, and more preferably 1.5 times or more the outer diameter W1 of the blind via hole 7; therefore, ranges of gap between edges would be satisfy; also note that it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.)
It would have been obvious to ordinary skill in the art before the effective filing date of the claimed invention to modify the wiring board of Adachi to have via hole with land pads as taught by Uchida so that by having via, easily connect or transfer current, signal. or ground between opposite sides of substrate and electrically connect both sides of devices; and by having larger pad than via will increase contact area or surface of the pad to reliably connect other devices to the board; Uchida further mentions that the present invention has been made in view of the disadvantages described above. an object of the present invention is to provide a double-sided printed wiring board in which a blind via hole is easily and reliably formed, which can be accurately applied to lands of a surface-mounted component that are arranged at a narrow pitch, and in which an impedance mismatch can be effectively suppressed, and a method for producing the double-sided printed wiring board.
Rejection of claims 10-11, Adachi discloses the wiring board according to claim 7, wherein the wiring board further comprises a protective layer disposed on the at least one side wiring (see cover 131 in figure 14 of Adachi), and
Adachi fails to disclose an orthographic projection of edges of the protective layer on the first substrate exceeds an orthographic projection of edges of the at least one side wiring on the first substrate; and a distance between an edge of the protective layer and a corresponding edge of an entirety of the at least one side wiring is greater than or equal to 20 microns.
Adachi in view of Uchida as explained in the rejection of claims 2-4 above disclose the an orthographic projection of edges of the protective layer on the first substrate exceeds an orthographic projection of edges of the at least one side wiring on the first substrate; and a distance between an edge of the protective layer and a corresponding edge of an entirety of the at least one side wiring is greater than or equal to 20 microns (see rejection of claims 2-4 above).
Pertinent Prior Arts
The prior arts made of record and not relied upon is considered pertinent to applicant's disclosure. Please refer to the enclosed PTO-892 form for the citation of pertinent arts in the present case, all of which disclose various wiring board assemblies.
Communication
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PARESH PAGHADAL whose telephone number is (571)272-5251. The examiner can normally be reached 7:00AM-4:00PM, Monday - Thursday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached on (571)272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PARESH PAGHADAL/ Primary Examiner, Art Unit 2847