DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to Amendment filed on September 21, 2026.
Drawings
The drawings were received on April 7, 2026. These drawings are accepted.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over by Cao et al. (US 9,287,516 hereinafter Cao) in view of Sharma et al. (US 2022/0328697, hereinafter Sharma), and further in view of Makita et al. (US 5,936,291; hereinafter Makita).
Regarding claim 11, Cao discloses for a method for fabricating a transistor (Figs. 8-9) comprising that
forming a low-dimensional material layer (carbon nanotubes 206, Fig. 8), because carbon nanotubes (CNTs) are classified as one-dimensional (1-D) material, which corresponds to the low-dimensional material layer in the claimed invention, a gate dielectric layer (first gate dielectric material 214, Fig. 9), a source (source electrode 208, Fig. 9), a drain (drain electrode 210, Fig. 8) and a gate (gate electrode material 212, Fig. 8) above a substrate (a composite substrate of substrate 202 and dielectric layer 204, Fig. 8), because Applicants do not specifically claim what a substrate is made of and/or what material’s composition a substrate has, i.e., whether it is a single layer substrate or multilayers such as semiconductor-on-insulator (SOI) wafer, and the Merriam-Webster dictionary defines a word “substratum” as “an underlying support or foundation”, and the substrate 202 and the dielectric layer 204 by Cao is the underlying support of several layers and components, therefore, the composite substrate of layers 202 and 204 can correspond to the substrate in the claimed invention,
wherein the gate dielectric layer (214, Fig. 8) is located between the low-dimensional material layer (206, Fig. 8) and the gate (212, Fig. 8); and
forming spacers (dielectric 216 and 218, Fig. 9) between the source (208, Fig. 9) and the gate (212, Fig. 9) and between the drain (210, Fig. 9) and the gate (212, Fig. 9), respectively,
wherein each spacer (216/218, Fig. 9) is a distinct structural element disposed at a sidewall of the source (sidewall of 208, Fig. 9) and at a sidewall of the drain (sidewall of 210, Fig. 9), respectively, because Cao further discloses that “…the gate structure 224 is separated from the source electrode 208 by a first gap 220 and is separated from the drain electrode 210 by a second gap 222” (Col. 3, lines 18-20) and “dielectric 216 is formed in the first gap 220 and dielectric 218 is formed in the second gap 222” (Col. 3, lines 25-27), therefore, each of the dielectric 216 and 218 would be a distinct structural element disposed in different gaps.
Cao does not explicitly disclose that each spacer has a rectangular shape in a top view.
However, Sharma discloses a thin film transistor structure including spacer materials 114B and 116B having a rectangular shape in a top view (Fig. 1A-1B), therefore, Sharma demonstrates that a rectangular shape in a plan view is a known configuration for transistor spacers and further supports the evidence of Cao’s dielectrics 216 and 218 as having the claimed rectangular shape.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a rectangular shape of Cao’s dielectric spacers in a top view, as evidenced by Sharma, as a known configuration of conventional thin film transistor spacers.
Cao in view of Sharma does not explicitly disclose that the substrate has fixed charges, or interface dipoles are formed by the substrate and an insulating dielectric layer comprising at least one of the gate dielectric layer and the spacers, and the interface dipoles are formed at an interface of the substrate and each of the spacers.
However, Cao further discloses that “the first dielectric 214 may be an n-type or a p-type dielectric” (Col. 3, lines 36-37), “the second dielectric 216 and 218 may be an n-type or p-type dielectric” (Col. 3, lines 42-43), and “the first and second dielectric 214 and 216 may dope their respective segments of the carbon nanotube by electrostatic doping” (emphasis added, Col. 3, lines 48-50). The first dielectric 214 and second dielectric 216/218 by Cao corresponds to the claimed gate dielectric layer and spacers, respectively, therefore, Cao expressly teaches that the dielectric layers may have n-type or p-type characteristics and may electrostatically dope adjacent segments of the carbon nanotube channel. Such electrostatic doping would involve an electrostatic charge distribution across the dielectric and carbon nanotube interfaces, resulting in an interfacial electric field and corresponding dipole behavior. Therefore, one of ordinary skill in the art would have understood that Cao’s n-type or p-type dielectric layers provide the claimed interface charge or dipole configuration at the relevant dielectric interfaces.
Furthermore, Makita discloses a thin film transistor structure including a first insulating film 2 disposed on a substrate 1 (Fig. 1A), and therefore, a composite layer of the first insulating film 2 and substrate 1 can correspond to the claimed substrate. Makita further discloses an active layer 9, a gate electrode 11, and a second insulating film 10 disposed in the transistor structure (Fig. 1A). Makita expressly teaches that “the first insulating film 2 has positive fixed charges E1 as shown in FIG. 1A, the second insulating film 10 is made to have negative fixed charges E2” (Fig. 1A, Col. 5, line 36-38) and “the amount of the fixed charges E2 influences the active layer 9, and consequently the threshold voltage of the TFT can be controlled. This method allows both the film formation and the threshold voltage to be controlled together at one time without performing an extra step such as an ion doping step for controlling the threshold voltage of the TFT” (Col. 8, lines 48-54). Accordingly, Makita demonstrates that fixed charges can be intentionally provided in insulating films of a transistor structure and that the amount and polarity of such fixed charges can be selected to control the electrical characteristics of an adjacent semiconductor channel. Therefore, in view of Makita, one of ordinary skill in the art would have recognized that Makita’s fixed charge of insulating layers can be incorporated into Cao’s insulating layer 204 and gate dielectric/spacer structures 214/216/218. Such modification would provide a known mechanism for controlling the electrical characteristics of Cao’s transistor without requiring a separate ion-doping operation.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cao’s insulating layer, gate dielectric material, and spaces in view of Makita to include fixed charges, in order to control the electrical characteristics including the doping or carrier concentration of the channel and the threshold voltage of the transistor, while facilitating transistor fabrication by formation of fixed charges in the insulating films, as taught by Makita.
Regarding claim 12, Cao further discloses for the method according to claim 11 that forming the substrate (202/204, Fig. 9) by thermal oxidation, chemical vapor deposition, physical vapor deposition or atomic layer deposition, because “dielectric layer 204 may be deposited on substrate 202 by chemical vapor deposition method or atomic layer deposition method or other suitable techniques” (Col. 4, line 11-14).
Cao in view of Sharma does not explicitly disclose that subjecting a surface of the substrate to a pretreatment before the low-dimensional material layer is formed, wherein the pretreatment comprises at least one of plasma treatment, annealing treatment, wet chemical cleaning, and surface molecule modification.
However, it is obvious to one of ordinary skill in the semiconductor industry that the substrate would be subjected to some form of treatments such as wet/dry cleaning and/or annealing prior to CNT (i.e., low-dimensional material layer in the claimed invention) formation and it is generally considered as a routine optimization to adjust surface energy or remove adsorbates/contaminants from the substrate ensuring good adhesion and good electrical contact.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over by Cao et al. (US 9,299,939, hereinafter Cao) in view of Sharma et al. (US 2022/0328697, hereinafter Sharma), and further in view of Makita et al. (US 5,936,291; hereinafter Makita) as applied to claim 1, and further in view of Xu et al. (US 2020/0259009, hereinafter Xu). The teachings of Cao in view of Sharma, further in view of Makita are discussed above.
Regarding claim 13, Cao further discloses that sequentially forming the low-dimensional material layer (206, Fig. 4), a gate dielectric material layer (214, Fig. 6) and a gate material layer (212, Fig. 7) on the substrate (202/204, Figs. 4-9);
patterning the gate material layer to form the gate (212, Fig. 7) and expose a part of the gate dielectric material layer where the gate is not located (sidewall of the first gate dielectric material 214 shown in Fig. 8);
forming a spacer material layer (216/218, Fig. 9) on a top and a sidewall of the gate (top surface and sidewall of the gate electrode material 212, Fig. 9) and the exposed part of the gate dielectric material layer (sidewall of the first gate dielectric material 214, Fig. 9) by atomic layer deposition or chemical vapor deposition, because Cao further discloses that “In one embodiment, dielectric 214 may include AlON/HfO2 and dielectric 216 and 218 may include AlON/Al2O3. In another embodiment, dielectric 214 may include AlON/Al2O3 and dielectric 216 and 218 may include AlON/HfO2” (Col. 3, lines 31-35) and it is well-known in the semiconductor industry that chemical vapor deposition and atomic layer deposition are widely used for deposition of AlON or HfO2;
removing a part of the spacer material layer (216/218, Fig. 9) by dry etching and retaining the spacer material layer at the sidewall of the gate (sidewall of 212, Fig. 9) to form the spacers (216/218, Fig. 9), because “the second dielectric may be deposited to cover the source electrode 208, drain electrode 210, gate 224 and the first gap 220 and second gap 222 and an etching process may be used to remove the second dielectric from the source electrode 208, drain electrode 210 and gate electrode 212, thereby leaving second dielectric 216 and 218 in their respective gaps 220 and 222” (emphasis added, Col. 4, lines 55-61), therefore, the etching process by Cao removes a part of the second dielectric layer 216 and 218 (Fig. 9);
Cao in view of Sharma, further in view of Makita does not explicitly disclose that removing the gate dielectric material layer at a side of the spacers away from the gate by etching to form the gate dielectric layer; and depositing a metal to form the source and the drain, respectively.
However, Xu discloses for a double gate two-dimensional (2D) material transistor that the top gate dielectric 140 is deposited on the layer of 2D material 130 (Fig. 3, [0030]), the first/second/third sets of spacers 170/180/190 are deposited on the top gate dielectric 140 (Figs. 4-6), and the top gate dielectric 140 at a side of the spacers 170/180/190 is removed by a directional etch (Fig. 7, [0035]); and then the source and drain contact metal 210 is deposited (Fig. 12, [0037]), as described in claim 13 of the current application.
Moreover, it is well-known in the semiconductor industry that numerous methods are available for fabricating field-effect transistors based on 2D materials and that various combinations of conventional techniques such as gate dielectric deposition, insulator deposition, gate/source/drain formation, photolithography, and plasma etching can be employed.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a gate electrode and spacers can be formed on a gate dielectric layer prior to forming source/drain electrodes, as disclosed by Xu, in order to implement one of the well-known fabrication sequences for 1D/2D materials-based field-effect transistors.
Response to Arguments
Applicant’s arguments with respect to claim(s) 11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/WOO K LEE/Examiner, Art Unit 2815
