Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Applicant's preliminary amendments filed on 3/6/23 have been entered.
Drawings
The drawings are objected to because two figures (an upper figure and a lower figure in which both figures are shown beneath FIG. 6B) share the same label of “FIG. 6C” and it appears that the lower figure should be labeled “FIG. 6D” to improve clarity.
The drawings are objected to because it is unclear if FIG 6C should have the “Rd” value of “0” or “1”. Currently, the figure shows “Rd=0”, but it appears that it may conflict with specification [0095] that states “is asserted (Rd = 1)”.
The drawings are objected to because it is unclear if FIG 6D should have the “Wr” value of “0” or “1”. Currently, the figure shows “Wr=0”, but it appears that it may conflict with specification [0096] that states “is asserted (Wr = 1)”.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 11, 13, and 31 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hennecke et al. US20200370955.
Regarding independent claim 1, Hennecke discloses, in Figures 1-7,
A Light Detection and Ranging (LIDAR) detector circuit (Hennecke; Fig. 1-7; LIDAR scanning system 200), comprising: one or more photodetector elements (Hennecke; receiver unit 22 that comprises an optical receiver photodetector array 15) configured to output respective detection signals indicating respective detection events responsive to light incident thereon (Hennecke; [0057] “point cloud data”); and at least one control circuit configured to receive the respective detection signals from the one or more photodetector elements (Hennecke; receiver circuit 24 of receiver unit 22; [0061] “receive the digital electrical signals from the photodetectors”), and to reset the one or more photodetector elements responsive to a transition of a clock signal (Hennecke; clock signal generator 7) after (Hennecke; [0082] “Thus, the clock signal actively recharges the internal capacitor CD of the SPAD 3 after the internal capacitor CD has been discharged by a received photon.”) the respective detection events (Hennecke; [0077] “transistor SR is representative of an active quenching-recharging circuit that is triggered by a clock.”; [0079] “The clock signal CLK actively turns the transistor SR on and off based on whether or not the SPAD 3 is in its operating mode (i.e., its off condition).”; [0081] “a clock pulse ( e.g., a high clock value) turns on the transistor SR to charge the internal capacitor CD in order to place the SPAD 3 back into its operating mode”).
Regarding claim 2, Hennecke discloses The LIDAR detector circuit of claim 1, wherein the clock signal comprises a global clock signal (Hennecke; clock signal generator 7) that is configured to control output of pulses of an emitter signal from a LIDAR emitter element or emitter array (Hennecke; [0048] it is inferred that the clock signal is used to synchronize photodiode activation with light pulses from illumination unit 10).
Regarding claim 3, Hennecke discloses The LIDAR detector circuit of claim 2, wherein the at least one control circuit comprises: a sampling circuit that is configured to sample the respective detection signals responsive to the global clock signal to generate a sampled detection signal (Hennecke; Fig. 6; summing circuit 8; [0060] “digital sample” with corresponding “sample time” from the photodetector array); and a reset circuit that is configured to reset the one or more of the photodetector elements responsive to the sampled detection signal (Hennecke; quenching circuit 4).
Regarding claim 4, Hennecke discloses The LIDAR detector circuit of claim 3 wherein the sampling circuit comprises a logic circuit that is free of delay logic (Hennecke; Fig. 6; summing circuit 8 is free of delay logic).
Regarding claim 11, Hennecke discloses The LIDAR detector circuit of claim 3, wherein the one or more photodetector elements are configured to operate at a different voltage level than the reset circuit, and wherein the at least one control circuit further comprises: a bias circuit that is coupled between an output of the one or more photodetector elements and the reset circuit, wherein the reset circuit and the bias circuit are free of voltage level shift electronics (Hennecke; [0026] “biasing circuitry”; [0082] “recharged by the bias voltage”).
Regarding claim 13, Hennecke discloses The LIDAR detector circuit of claim 2, wherein the one or more photodetector elements are detectors of a same detector pixel of a LIDAR detector array (Hennecke; Fig. 3B; each digital SiPM pixel 1 comprises an array of microcells 2 which each comprises multiple SPAD 3), and wherein the at least one control circuit is configured to reset the one or more photodetector elements responsive to the transition of the global clock signal after a first one of the respective detection events (Hennecke; [0077] “transistor SR is representative of an active quenching-recharging circuit that is triggered by a clock.”; [0079] “The clock signal CLK actively turns the transistor SR on and off based on whether or not the SPAD 3 is in its operating mode (i.e., its off condition).”; [0081] “a clock pulse ( e.g., a high clock value) turns on the transistor SR to charge the internal capacitor CD in order to place the SPAD 3 back into its operating mode”).
Regarding claim 31, Hennecke discloses The LIDAR detector circuit of claim 1, wherein the one or more photodetector elements comprise one or more single photon avalanche diodes (SPADs) (Hennecke; [0048] photodetector array 15 comprises SPADs).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hennecke et al. US20200370955 in view of Sugawara et al. US20230048446.
Regarding claim 5, Hennecke teaches the invention substantially the same as described above, and The LIDAR detector circuit of claim 1, wherein the at least one control circuit is configured to reset the one or more photodetector elements responsive to the transition of the clock signal and the one or more photodetector elements (Hennecke; [0077] “transistor SR is representative of an active quenching-recharging circuit that is triggered by a clock.”; [0079] “The clock signal CLK actively turns the transistor SR on and off based on whether or not the SPAD 3 is in its operating mode (i.e., its off condition).”; [0081] “a clock pulse ( e.g., a high clock value) turns on the transistor SR to charge the internal capacitor CD in order to place the SPAD 3 back into its operating mode”).
Hennecke does not disclose after respective delay times that are associated with the one or more photodetector elements.
Sugawara teaches, in Figure 2, a “variable delay element (electrical signal delay section) 1b is arranged to delay an electrical signal output from the photodetector 1a by a predetermined delay time” (Sugawara; Fig. 2; [0066] “variable delay element (electrical signal delay section) 1b is arranged to delay an electrical signal output from the photodetector 1a by a predetermined delay time”; [0069] “It is noted that the delay time is variable in the variable delay element (electrical signal delay section) 1b. This allows for scaling with a change in the distance D1 in the case of actually using the optical measuring instrument 2.”).
It would have been obvious to one having ordinary skill at the effective filing date of the invention to modify the detector circuit and each of the photodetector elements as taught by Hennecke to include the variable photodetector delay element as taught by Sugawara for the purpose of providing a variable/adjustable delay of the electrical signal output of the photodetector (Sugawara; [0066] “to delay an electrical signal output from the photodetector 1a by a predetermined delay time”) and to allow for scaling relative to the measuring distance (Sugawara; [0069] “It is noted that the delay time is variable in the variable delay element (electrical signal delay section) 1b. This allows for scaling with a change in the distance D1 in the case of actually using the optical measuring instrument 2.”).
Regarding claim 6, Hennecke teaches the invention substantially the same as described above, and The LIDAR detector circuit of claim 5, wherein the one or more photodetector elements are detectors of a same detector pixel of a LIDAR detector array (Hennecke; Fig. 3B; each digital SiPM pixel 1 comprises an array of microcells 2 which each comprises multiple SPAD 3), and wherein the respective delay times of the detectors of the same detector pixel differ from one another (Hennecke; [0002] “to measure ranges (variable distances)”) (Sugawara; [0069] “It is noted that the delay time is variable in the variable delay element (electrical signal delay section) 1b. This allows for scaling with a change in the distance D1 in the case of actually using the optical measuring instrument 2.”).
Regarding claim 7, Hennecke teaches the invention substantially the same as described above, and The LIDAR detector circuit of claim 5, wherein the one or more photodetector elements are detectors of different detector pixels of a LIDAR detector array, and wherein the respective delay times of the detectors of the different detector pixels differ from one another (Hennecke; [0002] “to measure ranges (variable distances)”) (Sugawara; [0069] “It is noted that the delay time is variable in the variable delay element (electrical signal delay section) 1b. This allows for scaling with a change in the distance D1 in the case of actually using the optical measuring instrument 2.”).
Regarding claim 8, Hennecke teaches the invention substantially the same as described above, and The LIDAR detector circuit of claim 5, wherein the one or more photodetector elements are detectors of different groups of detector pixels of a LIDAR detector array, and wherein the respective delay times of the detectors of the different groups of the detector pixels differ from one another (Hennecke; [0002] “to measure ranges (variable distances)”) (Sugawara; [0069] “It is noted that the delay time is variable in the variable delay element (electrical signal delay section) 1b. This allows for scaling with a change in the distance D1 in the case of actually using the optical measuring instrument 2.”).
Regarding claim 9, Hennecke teaches the invention substantially the same as described above, and The LIDAR detector circuit of claim 5, wherein the at least one control circuit comprises: a sampling and delay circuit that is configured to sample the respective detection signals responsive to the clock signal to generate sampled detection signals (Hennecke; Fig. 6; summing circuit 8; [0060] “digital sample” with corresponding “sample time” from the photodetector array), and is configured to offset the sampled detection signals by the respective delay times (Sugawara; Fig. 2; [0066] “variable delay element (electrical signal delay section) 1b is arranged to delay an electrical signal output from the photodetector 1a by a predetermined delay time”; [0069] “It is noted that the delay time is variable in the variable delay element (electrical signal delay section) 1b. This allows for scaling with a change in the distance D1 in the case of actually using the optical measuring instrument 2.”); and a reset circuit that is configured to reset the one or more of the photodetector elements responsive to the sampled detection signals that are offset by the delay circuit (Hennecke; [0077] “transistor SR is representative of an active quenching-recharging circuit that is triggered by a clock.”; [0079] “The clock signal CLK actively turns the transistor SR on and off based on whether or not the SPAD 3 is in its operating mode (i.e., its off condition).”; [0081] “a clock pulse ( e.g., a high clock value) turns on the transistor SR to charge the internal capacitor CD in order to place the SPAD 3 back into its operating mode”).
Regarding claim 10, Hennecke teaches the invention substantially the same as described above, and The LIDAR detector circuit of claim 9, wherein the sampling and delay circuit comprises one or more delay elements having respective timing offsets associated therewith, wherein the one or more delay elements are selectable responsive to a delay select signal (Sugawara; Fig. 2; [0066] “variable delay element (electrical signal delay section) 1b is arranged to delay an electrical signal output from the photodetector 1a by a predetermined delay time”; [0069] “It is noted that the delay time is variable in the variable delay element (electrical signal delay section) 1b. This allows for scaling with a change in the distance D1 in the case of actually using the optical measuring instrument 2.”).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hennecke et al. US20200370955 in view of Wan et al. US20160245788.
Regarding claim 12, Hennecke teaches the invention substantially the same as described above, and The LIDAR detector circuit of claim 11.
Hennecke does not disclose wherein the reset circuit comprises a reset transistor that is coupled to the output of the one or more photodetector elements, and wherein the bias circuit comprises a bias transistor that is coupled in a cascode arrangement between the output of the one or more photodetector elements and the reset transistor.
Wan teaches a reset transistor (Wan; Fig. 3B; reset transistor 341) that is coupled to the output of the one or more photodetector elements (Wan; Fig. 3B; photodiode 330), and wherein the bias circuit comprises a bias transistor (Wan; Fig. 3B; bias transistor 343) that is coupled in a cascode arrangement between the output of the one or more photodetector elements and the reset transistor (Wan; Fig. 3B; [0042] “providing a PMOS cascode load”).
It would have been obvious to one having ordinary skill at the effective filing date of the invention to modify the detector circuit as taught by Hennecke to include a reset transistor and a bias transistor in a cascode arrangement as taught by Wan for the purpose of improving speed/bandwidth, improving sensitivity, minimizing noise, and improving stability.
Claim(s) 14-23, 25, and 27-28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hennecke et al. US20200370955 in view of Yuh et al. US9881676 and Abts et al. US20090177932.
Regarding claim 14, Hennecke teaches the invention substantially the same as described above, and The LIDAR detector circuit of claim 2, further comprising: a memory device comprising a storage medium including a plurality of memory cells and configured to store data in respective memory bins comprising one or more of the memory cells (Hennecke; Fig. 8; clocked memory device 87 with six 1-bit flip flops), wherein the at least one control circuit further comprises a memory control circuit configured to update the data in the respective memory bins responsive to the respective detection events (Hennecke; Fig. 8; hierarchical adder tree 800).
Hennecke does not disclose a non-transitory storage medium, a memory control circuit configured to execute an increment operation to update the data in the respective memory bins responsive to the respective detection events.
Yuh teaches a non-volatile memory system 102, a bit line 302 in Figure 4A, a bias circuit, a sense circuit, transistor 456, and bit line capacitance being greater than storage capacitance (Yuh; Fig. 4A; non-volatile memory system 102; a bit line 302; col. 5:47-49 “a bias circuit and a sense circuit, and the capacitance of the bias circuit may be greater than the capacitance of the sense circuit”; col. 6:6-13 “A higher-capacitance bias circuit coupled to the bit line to apply the bias voltage may stabilize the bias voltage over the course of multiple program voltage pulses. Thus, in certain embodiments, a sense/bias component 150 including a sense circuit and a bias circuit, where the capacitance of the bias circuit is greater than the capacitance of the sense circuit, may provide fast read operations and stable program operations.”; col. 17:24-26 “a capacitance of a bias circuit 404 may be greater than a capacitance for a sense circuit 402”; col. 17:35-36 “low sense circuit 402 capacitances may facilitate fast sensing for read or program verify operations”; col. 17:52-55 “low capacitance sense circuit 402 may facilitate fast sensing, and a high capacitance bias circuit 404 may facilitate stable programming”.
It would have been obvious to one having ordinary skill at the effective filing date of the invention to modify the storage medium memory of Hennecke to be non-transitory/non-volatile as taught by Yuh for the purpose of providing longer-term data storage that is retained without the need for continuous power.
Furthermore, it would have been obvious to one having ordinary skill at the effective filing date of the invention to modify the detector circuit of Hennecke to include the configuration of the bit line, bias circuit, sense circuit, transistor 456, and bit line capacitance being greater than storage capacitance as taught by Yuh for the purpose of providing stable programming and fast sensing/detection (Yuh; col. 17:52-55 “low capacitance sense circuit 402 may facilitate fast sensing, and a high capacitance bias circuit 404 may facilitate stable programming).
Modified Hennecke does not teach, a memory control circuit configured to execute an increment operation to update the data in the respective memory bins responsive to the respective detection events.
Abts teaches an increment operation to update the data in the respective memory bins (Abt; [0088] “LFSR associated with the given bit location is incremented. Therefore, the value in the LFSRs of data structure 400 function as counters”; [0092] LFSR 510 operates as an incremental counter).
It would have been obvious to one having ordinary skill at the effective filing date of the invention to modify the detector circuit of Modified Hennecke to include LFSR Linear Feedback Shift Register as taught by Abts for the purpose of providing improved time delay, improved chip area usage, improved energy efficiency, and/or lower hardware overhead.
Regarding claim 15, Modified Hennecke teaches the invention substantially the same as described above, and The LIDAR detector circuit of claim 14, wherein the memory control circuit (Hennecke; Fig. 8; hierarchical adder tree 800) comprises a logic-based counter circuit that is configured to perform the increment operation by connecting a storage element of a respective one of the memory cells to a bit line (Yuh; bit line 302) of a preceding one of the memory cells in a same row or column of the memory device (Abt; LFSR 510), wherein a capacitance of the bit line is greater than a capacitance of the storage element (Yuh; col. 17:24-26 “a capacitance of a bias circuit 404 may be greater than a capacitance for a sense circuit 402”).
Regarding claim 16, Modified Hennecke teaches the invention substantially the same as described above, and The LIDAR detector circuit of claim 15, wherein the logic-based counter circuit comprises a linear feedback shift register that is configured to execute the increment operation by sequentially shifting the data stored in the storage element of the respective one of the memory cells to a bit line of a succeeding one of the memory cells in the row using a linear feedback loop (Abt; LFSR 510).
Regarding independent claim 17, Modified Hennecke teaches the invention substantially the same as described above in reference to independent claim 1, corresponding dependent claims 14-15, and their intervening claims above, and A Light Detection and Ranging (LIDAR) detector circuit (Hennecke; Fig. 1-7; LIDAR scanning system 200), comprising: a memory device comprising a non-transitory (Yuh; non-volatile memory system 102) storage medium including a plurality of memory cells configured to store data in respective memory bins comprising one or more of the memory cells (Hennecke; Fig. 8; clocked memory device 87 with six 1-bit flip flops); and at least one control circuit configured to execute an increment operation to update the data in the respective memory bins by connecting a storage element of a respective memory cell of the memory cells to a bit line (Yuh; bit line 302) of a preceding memory cell of the memory cells in a same row or column of the memory device (Abt; LFSR 510).
Regarding claim 18, Modified Hennecke teaches the invention substantially the same as described above, and The LIDAR detector circuit of claim 17, wherein the respective memory cell comprises a transistor (Yuh; Fig. 4B; transistor 456) that is configured to be switched to connect the storage element thereof with the bit line (Yuh; bit line 302) of the preceding memory cell, wherein a capacitance of the bit line is greater than a capacitance of the storage element (Yuh; col. 17:24-26 “a capacitance of a bias circuit 404 may be greater than a capacitance for a sense circuit 402”).
Regarding claim 19, Modified Hennecke teaches the invention substantially the same as described above, and The LIDAR detector circuit of claim 17, wherein the at least one control circuit further comprises: a photodetector interface circuit (Hennecke; receiver circuit 24) that is configured to receive respective detection signals from one or more photodetector elements (Hennecke; receiver unit 22 that comprises an optical receiver photodetector array 15), wherein the at least one control circuit is configured to execute the increment operation to update the data in the respective memory bins responsive to respective detection events indicated by the respective detection signals (Abt; [0088] “LFSR associated with the given bit location is incremented. Therefore, the value in the LFSRs of data structure 400 function as counters”; [0092] LFSR 510 operates as an incremental counter), and to reset the one or more photodetector elements responsive to transition of a clock signal (Hennecke; clock signal generator 7) after the respective detection events (Hennecke; [0077] “transistor SR is representative of an active quenching-recharging circuit that is triggered by a clock.”; [0079] “The clock signal CLK actively turns the transistor SR on and off based on whether or not the SPAD 3 is in its operating mode (i.e., its off condition).”; [0081] “a clock pulse ( e.g., a high clock value) turns on the transistor SR to charge the internal capacitor CD in order to place the SPAD 3 back into its operating mode”), optionally wherein the clock signal (Hennecke; clock signal generator 7) is configured to control output of pulses of an emitter signal from a LIDAR emitter element (Hennecke; illumination unit 10 necessarily operates in conjunction with a clock signal in order to provide light pulses; [0030] “emitting successive light pulses”) (it is noted that this limitation is not necessarily required because the limitation recites “optionally”).
Regarding claim 20, Modified Hennecke teaches the invention substantially the same as described above, and The LIDAR detector circuit of claim 19, wherein the at least one control circuit comprises a logic-based counter circuit that is configured to execute the increment operation responsive to the respective detection events (Abt; LFSR 510).
Regarding claim 21, Modified Hennecke teaches the invention substantially the same as described above, and The LIDAR detector circuit of claim 20, wherein the logic-based counter circuit comprises a linear feedback shift register that is configured to execute the increment operation by sequentially shifting the data stored in the storage element of the respective memory cell to a bit line of a succeeding memory cell in the same row or column of the memory device using a linear feedback loop (Abt; LFSR 510).
Regarding independent claim 22, Modified Hennecke teaches the invention substantially the same as described above in reference to independent claim 1, corresponding dependent claims 14-15, and their intervening claims above, and A Light Detection and Ranging (LIDAR) detector circuit (Hennecke; Fig. 1-7; LIDAR scanning system 200), comprising: a detector array comprising a plurality of photodetector elements configured to output respective detection signals indicating respective detection events responsive to light incident thereon (Hennecke; receiver unit 22 that comprises an optical receiver photodetector array 15); a memory device (Hennecke; Fig. 8; clocked memory device 87 with six 1-bit flip flops) comprising a non-transitory storage medium (Yuh; non-volatile memory system 102) including a plurality of memory cells configured to store data in respective memory bins comprising one or more of the memory cells; and at least one control circuit configured to receive the respective detection signals from the photodetector elements (Abt; LFSR 510), and to execute an increment operation to update the data in the respective memory bins responsive to the respective detection events (Abt; LFSR 510), wherein the at least one control circuit comprises: a photodetector control circuit configured to reset the photodetector elements responsive to a transition of a clock signal after the respective detection events (Hennecke; [0077] “transistor SR is representative of an active quenching-recharging circuit that is triggered by a clock.”; [0079] “The clock signal CLK actively turns the transistor SR on and off based on whether or not the SPAD 3 is in its operating mode (i.e., its off condition).”; [0081] “a clock pulse ( e.g., a high clock value) turns on the transistor SR to charge the internal capacitor CD in order to place the SPAD 3 back into its operating mode”); and/or a memory control circuit configured to execute the increment operation by connecting a storage element of a respective memory cell of the memory cells to a bit line (Yuh; bit line 302) of a preceding memory cell of the memory cells in a same row or column of the memory device (Abt; LFSR 510).
Regarding claim 23, Modified Hennecke teaches the invention substantially the same as described above, and The LIDAR detector circuit of claim 22, wherein the clock signal comprises a global clock signal (Hennecke; clock signal generator 7) that is configured to control output of pulses of an emitter signal from a LIDAR emitter element or emitter array (Hennecke; illumination unit 10 necessarily operates in conjunction with a clock signal in order to provide light pulses; [0030] “emitting successive light pulses”).
Regarding claim 25, Modified Hennecke teaches the invention substantially the same as described above in reference to claim 3.
Regarding claim 27, Modified Hennecke teaches the invention substantially the same as described above, and The LIDAR detector circuit of claim 22, wherein the memory device is a memory array comprising respective rows or columns of memory cells that define the respective memory bins (Hennecke; Fig. 8; clocked memory device 87 with six 1-bit flip flops), and wherein the at least one control circuit is further configured to output a readout signal responsive to a read signal that is sequentially applied to the respective rows or columns (Abt; LFSR 510).
Modified Hennecke does not teach wherein the memory device is a memory array comprising respective rows or columns of dynamic random access memory (DRAM) cells.
Abts teaches dynamic random access memory (DRAM) (Abts; [0043] memory device 130 include DRAM memory; [0004] DRAM is configured to “store data such that it can be read or written much more quickly than the same data could be accessed using nonvolatile memory”).
It would have been obvious to one having ordinary skill at the effective filing date of the invention to modify the memory cells as taught by Modified Hennecke to be DRAM cells as taught by Abts for the purpose of providing quicker access for scenarios that do not require long-term memory storage or for scenarios where continuous power is assumed to be provided under normal operating conditions (Abts; [0004] DRAM is configured to “store data such that it can be read or written much more quickly than the same data could be accessed using nonvolatile memory”).
Regarding claim 28, Modified Hennecke teaches the invention substantially the same as described above, and The LIDAR detector circuit of claim 27, wherein the readout signal comprises a count signal and/or a time integration signal, and wherein the at least one control circuit is configured to calculate an estimated time of arrival of photons incident on the photodetector elements based on the readout signal (Hennecke; [0002] “time-of-flight computations”).
Claim(s) 24 and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hennecke et al. US20200370955 in view of Yuh et al. US9881676 and Abts et al. US20090177932 as applied to claims 23 and 25 above, and further in view of Sugawara et al. US20230048446.
Regarding claim 24, Modified Hennecke teaches the invention substantially the same as described above in reference to claim 5.
Regarding claim 26, Modified Hennecke teaches the invention substantially the same as described above, and The LIDAR detector circuit of claim 25, wherein the sampling circuit (Hennecke; Fig. 6; summing circuit 8; [0060] “digital sample” with corresponding “sample time” from the photodetector array) further comprises a delay circuit (Sugawara; Fig. 2; [0066] “variable delay element (electrical signal delay section) 1b is arranged to delay an electrical signal output from the photodetector 1a by a predetermined delay time”; [0069] “It is noted that the delay time is variable in the variable delay element (electrical signal delay section) 1b. This allows for scaling with a change in the distance D1 in the case of actually using the optical measuring instrument 2.”) that is configured to offset the sampled detection signals by the respective delay times, and the reset circuit (Hennecke; quenching circuit 4) is configured to reset the photodetector elements responsive to the sampled detection signals that are offset by the delay circuit (Sugawara; Fig. 2; [0066] “variable delay element (electrical signal delay section) 1b is arranged to delay an electrical signal output from the photodetector 1a by a predetermined delay time”; [0069] “It is noted that the delay time is variable in the variable delay element (electrical signal delay section) 1b. This allows for scaling with a change in the distance D1 in the case of actually using the optical measuring instrument 2.”).
Claim(s) 29-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hennecke et al. US20200370955 in view of Yatskan et al. US20230213627.
Regarding claim 29, Hennecke discloses The LIDAR detector circuit of claim 1, wherein the at least one control circuit is configured to transmit respective strobe signals that activate the photodetector elements (Hennecke; receiver unit 22 that comprises an optical receiver photodetector array 15) for respective detection windows that are pulses of an emitter signal that are generated responsive to the clock signal (Hennecke; clock signal generator 7).
Hennecke does not disclose wherein the at least one control circuit is configured to transmit respective strobe signals that activate the photodetector elements for respective detection windows that are differently delayed between pulses of an emitter signal that are generated responsive to the clock signal.
Yatskan teaches wherein the at least one control circuit is configured to transmit respective strobe signals that activate the photodetector elements for respective detection windows that are differently delayed between pulses of an emitter signal that are generated responsive to the clock signal (Yatskan; [0034] “Thus, while the X photodiodes (hereinafter first photodiodes 32x) can be configured to detect light at a first timeslot, the Y photodiodes (hereinafter second photodiodes 32y) can be configured to detect light at a second timeslot, the W photodiodes (hereinafter third photodiodes 32w) can be configured to detect light at a third timeslot, and the Z photodiodes (hereinafter fourth photodiodes 32z) can be configured to detect light at a fourth timeslot. As explained above the length of the first, second, third and fourth timeslots can be the same, however the timestamp in which each timeslot begins, and ends is unique for each of the timeslots. Thus, the timing of the exposure of each group of X, Y and Z photodiodes can be controlled.”; [0052] “each group 36 in the photodiode array 30 acquires enough information to accurately determine the time of flight of any range, i.e., for objects located at either short or long distances. Thus, the photodiode array 30 can provide a depth image of an object wherein each depth pixel in the image is determined by the information obtained by one of the groups 36.”).
It would have been obvious to one having ordinary skill at the effective filing date of the invention to modify the photodetector element activation as taught by Hennecke to be differently delayed for different photodetector elements as taught by Yatskan for the purpose of providing accurate depth images that are optimized for different depth ranges/subranges (Yatskan; [0052] “each group 36 in the photodiode array 30 acquires enough information to accurately determine the time of flight of any range, i.e., for objects located at either short or long distances. Thus, the photodiode array 30 can provide a depth image of an object wherein each depth pixel in the image is determined by the information obtained by one of the groups 36.”).
Regarding claim 30, Modified Hennecke teaches the invention substantially the same as described above, and The LIDAR detector circuit of claim 29, wherein the respective detection windows correspond to respective distance subranges, and wherein the at least one control circuit is configured to transmit the respective strobe signals to activate the photodetector elements to sequentially cycle through the respective distance subranges (Yatskan; [0034] “Thus, while the X photodiodes (hereinafter first photodiodes 32x) can be configured to detect light at a first timeslot, the Y photodiodes (hereinafter second photodiodes 32y) can be configured to detect light at a second timeslot, the W photodiodes (hereinafter third photodiodes 32w) can be configured to detect light at a third timeslot, and the Z photodiodes (hereinafter fourth photodiodes 32z) can be configured to detect light at a fourth timeslot. As explained above the length of the first, second, third and fourth timeslots can be the same, however the timestamp in which each timeslot begins, and ends is unique for each of the timeslots. Thus, the timing of the exposure of each group of X, Y and Z photodiodes can be controlled.”).
Claim(s) 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hennecke et al. US20200370955 in view of Makimoto US20210165084.
Regarding claim 32, Hennecke discloses A LIDAR system comprising the LIDAR detector circuit of claim 1, wherein the LIDAR system is configured such that one or more emitter elements and the one or more photodetector elements are oriented relative to (Hennecke; receiver unit 22 that comprises an optical receiver photodetector array 15).
Hennecke is silent regarding wherein the LIDAR system is configured to be coupled to an autonomous vehicle such that one or more emitter elements and the one or more photodetector elements are oriented relative to an intended direction of travel of the autonomous vehicle.
Makimoto teaches wherein the LIDAR system is configured to be coupled to an autonomous vehicle such that one or more emitter elements and the one or more photodetector elements are oriented relative to an intended direction of travel of the autonomous vehicle (Makimoto; Fig. 16; [0123] LIDAR 7920 is directed towards the front of the vehicle “to detect a preceding vehicle”).
It would have been obvious to one having ordinary skill at the effective filing date of the invention to modify the location of the LIDAR system as taught by Hennecke to be at the front of a vehicle as taught by Makimoto for the purpose of detecting a preceding vehicle in the travel path (Makimoto; [0123] LIDAR 7920 is directed towards the front of the vehicle “to detect a preceding vehicle”).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nikitin et al. US11614542 teaches clock transitions (col. 14:14-20).
Henderson et al. US12442902 teaches a strobe signal.
Storrar US20230273304 teaches photodetectors.
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/JONATHAN MALIKASIM/ Primary Examiner, Art Unit 3612 1/30/26