Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statements
The Information Disclosure Statements filed on 8/12/2025 and 2/4/2026 have been considered.
Preliminary Amendment
In the preliminary amendment filed on 3/9/2023, Applicant amended claims 1-22, 24-27, 29-33.
Response to the Election/Restriction Requirement
In the 7/23/2026 response to the Election/Restriction requirement of 5/26/2026, Applicant elected Group 1, claims 1-22, without traverse. Claims 23-33 are withdrawn from consideration.
DETAILED ACTION
The instant application having Application No. 18/044,699 filed on 3/9/2023 is presented for examination by the Examiner.
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the Applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second
paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 1, 5, 7, 11-12, 16, 18, 22, said claims recite “and/or”. The phrase "and/or” renders the claims indefinite because it is unclear whether the alternative or the joint option is claimed. For examination purposes, the alternative option, “or”, will be taken.
Claim 4 recites the limitation "optical signal" in line 3. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, the quoted term will be taken as “reference optical signal”.
Claim 8 recites the limitation "said analogue circuit" in line 2. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, claim 8 will be taken as depending on claim 5.
Claim 9 recites the limitation "the difference" in line 2. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, said limitation will be taken as “a difference”.
Claim 19 recites the limitation "said analogue circuit" in line 1. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, claim 19 will be taken as depending on claim 16.
Claim 20 recites the limitation "said analogue circuit" in line 2. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, claim 20 will be taken as depending on claim 16.
Claim 20 recites the limitation "the difference" in line 3. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, said limitation will be taken as “a difference”.
Claims 2-3, 6, 10, 13-15, 17, 21 depend from claim 1 and are indefinite for the reason given above.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5-13, 16-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by New et al. (US 2006/0050986, hereinafter, “New”).
Regarding claim 1, New discloses an optical processing system 100 comprising an optical input 103;
an optical Fourier transform stage 120;
at least one modulator 102 provided between said optical input 103 and said optical Fourier transform stage 120; and
said optical Fourier transform stage providing an optical output to at least one photodetector 130 for receiving a reference optical signal 104 to provide currents and/or voltages relating to the intensities and/or phases of said reference optical signal 104;
said system further comprising an electronics feedback loop 131, 140, 141 which feeds back said currents and/or voltages and causes said modulator 102 to modulate the intensities and/or phases of a subsequent optical signal (Fig. 7, [0052]-[0054]. In the optical processing system of New, an optical input 103 is fed to the SLM 102 and a reference optical signal 104
is fed to the SLM 101, and then the outputs are fed to the lens 120 (which acts as a Fourier transform stage at the plane 121 at the lens’s focal plane). The Fourier transformed signal is then detected by detector 130 and its output is fed back to both the SLM 102 and SLM 101 via processor 140 for a subsequent optical signal).
Regarding claim 2, New discloses the optical processing system according to claim 1, wherein said Optical Fourier transform stage is a single Optical Fourier transform stage (Fig. 7, a single lens 120).
Regarding claim 5 New discloses the optical processing system according to claim 1, further comprising providing, as part of said electronics feedback loop, an analogue circuit configured to carry out a mathematical function on currents from said photodetector to provide an output of currents and/or voltages which is proportional to the phase of said reference optical signal ([0054] in New, The modulator 101 receiving the feedback changes the phase of the reference signal).
Regarding claim 6, New discloses the optical processing system according to claim 5, wherein said analogue circuit comprises at least one pair of photodetectors ([0053] in New, the CCD receives a pair of optical signals, signal and reference).
Regarding claim 7, New discloses the optical processing system according to claim 1, wherein said electronics feedback loop comprises at least one driver for intensity and/or phase modulation (Fig. 7, [0053-[0054], the processor 140 comprises at least one driver that produces the output 141).
Regarding claim 8, New discloses the optical processing system according to claim 5, wherein said analogue circuit comprises a rectifier circuit which drives intensity modulation (Fig. 7, [0053-[0054], the processor 140 comprises a rectifier circuit that produces a dc value for the intensity modulation of the SLMs 101, 102).
Regarding claim 9, New discloses the optical processing system according to claim 7, wherein said analogue circuit comprises a comparator to compare a difference signal with a predetermined voltage reference (Fig. 7, [0054], the processor 140 applies information to the SLMs 101, 102 related to brightness value of 1 or 0 (aka predetermined voltage reference), the difference signal corresponding to the signal and reference optical signals).
Regarding claim 10, New discloses the optical processing system according to claim 9, wherein said comparator has an output and said analogue circuit takes said comparator output and adds another predetermined voltage; whereby a phase shift is generated for phase shifting modulation (Fig. 7, [0054], the processor 140 applies information to the SLMs 101, 102 related to brightness value of 1 or 0 (aka predetermined voltage), a phase shift also being applied for phase modulation of the SLMs, claim 29).
Regarding claim 11, New discloses the optical processing system according to claim 1, comprising at least one pair of photodetectors, at least one analogue to digital converter, a microprocessor with either a pre-calibrated look-up-table to retrieve digital values or a digital signal processor (DSP), and at least one digital to analogue converter which generate the voltages and/or currents for driving intensity and/or phase modulators which modulate the intensities and/or phases of said optical signal (Fig. 7, [0053]-[0054] in New, the CCD receives a pair of optical signals, signal and reference. Moreover, the CCD receives an analog signal at 121, requiring a sequence of ADC/DSP/DAC components to feed the feedback signal 131 to the processing device 140).
Regarding claim 12, New discloses method of optical processing comprising the steps of providing an optical input 103,
providing an optical Fourier transform stage 120;
providing at least one modulator 102 between said optical input 103 and said optical Fourier transform stage 120; and
said optical Fourier transform stage providing an optical output to at least one photodetector 130 for receiving a reference optical signal 104 to provide currents and/or voltages relating to the intensities and/or phases of said reference optical signal 104;
providing an electronics feedback loop 131, 140, 141;
feeding back said currents and/or voltages; and
modulating the intensities and/or phases of a subsequent optical signal (Fig. 7, [0052]-[0054]. In the optical processing system of New, an optical input 103 is fed to the SLM 102 and a reference optical signal 104 is fed to the SLM 101, and then the outputs are fed to the lens 120 (which acts as a Fourier transform stage at the plane 121 at the lens’s focal plane). The Fourier transformed signal is then detected by detector 130 and its output is fed back to both the SLM 102 and SLM 101 via processor 140 for a subsequent optical signal).
Regarding claim 13, New discloses the method according to claim 12, wherein said Optical Fourier transform stage is a single Optical Fourier transform stage (Fig. 7, a single lens 120).
Regarding claim 16, New discloses the method according to claim 12, further comprising providing, as part of said electronics feedback loop, an analogue circuit and carrying out a mathematical function on currents from said photodetector to provide an output of currents and/or voltages which is proportional to the phase of said reference optical signal ([0054] in New, The modulator 101 receiving the feedback changes the phase of the reference signal).
Regarding claim 17, New discloses the method according to claim 16, wherein said analogue circuit comprises at least one pair of photodetectors ([0053] in New, the CCD receives a pair of optical signals, signal and reference).
Regarding claim 18, New discloses the method according to claim 12, wherein said electronics feedback loop comprises at least one driver for intensity and/or phase modulation (Fig. 7, [0053-[0054], the processor 140 comprises at least one driver that produces the output 141).
Regarding claim 19, New discloses the method according to claim 16, wherein said analogue circuit comprises a rectifier circuit which drives intensity modulation (Fig. 7, [0053-[0054], the processor 140 comprises a rectifier circuit that produces a dc value for the intensity modulation of the SLMs 101, 102).
Regarding claim 20, New discloses the method according to claim 7, wherein said analogue circuit comprises a comparator and said method comprise the further step of comparing a difference signal with a predetermined voltage reference (Fig. 7, [0054], the processor 140 applies information to the SLMs 101, 102 related to brightness value of 1 or 0 (aka predetermined voltage reference), the difference signal corresponding to the signal and reference optical signals).
Regarding claim 21, New discloses the method according to claim 20, wherein
said comparator has an output and said method comprises the steps of taking said comparator output and adding another predetermined voltage; whereby a phase shift is generated for phase shifting modulation (Fig. 7, [0054], the processor 140 applies information to the SLMs 101, 102 related to brightness value of 1 or 0 (aka predetermined voltage), a phase shift also being applied for phase modulation of the SLMs, claim 29).
Regarding claim 22, New discloses the method according to claim 12, comprising at least the steps of providing at least one pair of photodetectors, providing a microprocessor, providing at least one analogue to digital converter, providing either a pre-calibrated look-up table or a digital signal processor (DSP) to retrieve digital values, and providing at least one digital to analogue converter which generate the voltages and/or currents for driving intensity and/or phase modulators which modulate the intensities and/or phases of said optical signal (Fig. 7, [0053]-[0054] in New, the CCD receives a pair of optical signals, signal and reference. Moreover, the CCD receives an analog signal at 121, requiring a sequence of ADC/DSP/DAC components to feed the feedback signal 131 to the processing device 140).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4, 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over New in view of Hosseinzadeh et al. (US 2020/0110992, hereinafter, “Hosseinzadeh”).
Regarding claim 3, New discloses the optical processing system according to claim 1.
New does not disclose wherein at least one modulator comprises an interferometer with a first branch for optically encoding a signed Real value and with a second branch for optically encoding a signed Imaginary value.
Hosseinzadeh discloses an optoelectronic computing system (Abstract). In one embodiment, Hosseinzadeh’s system includes optical modulators, such as, Mach-Zehnder Interferometers (MZIs) that have two branches for optically encoding a signed real value and a signed imaginary value (Fig. 39A, [0412], [0460]. One branch encodes the phase).
Both New and Hosseinzadeh disclose optical processing systems.
It would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the present application to modify New so that the SLMs 101, 102 are MZIs, as taught by Hosseinzadeh, for better performance (for example, preventing losses due to backward reflection (by separating the optical paths to separate arms)).
Regarding claim 4, New/ Hosseinzadeh discloses the optical processing system according to claim 3.
New/Hosseinzadeh does not disclose wherein said interferometer encodes a signed magnitude and a signed orthogonal or quadrature phases on said optical signal.
Hosseinzadeh does not specify the encoded phases.
The parameter of the encoded phase is a result-effective variable, i.e., it is recognized to achieve a recognized result, for example, effecting the correlation between the inputs for the successive inputs.
New/Hosseinzadeh discloses the claimed invention except for the types of the encoded phases.
It would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the present application to modify New/Hosseinzadeh so that the encoded phases are orthogonal or quadrature, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art, In re Aller, 105 USPQ 233 (C.C.P.A. 1955). In the current instance, the encoded phase is an art recognized result-effective variable in that it affects the processing of the successive inputs.
Thus, one would have been motivated to optimize the encoded phase because it is an art-recognized result-effective variable and it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977). See MPEP §2144.05(II)(B) “after KSR, the presence of a known result-effective variable would be one, but not the only, motivation for a personal of ordinary skill in the art to experiment to reach another workable product or process”.
Regarding claim 14, New discloses the method according to claim 12.
New does not disclose optically encoding a signed Real value and with a second branch for optically encoding a signed Imaginary value.
Hosseinzadeh discloses an optoelectronic computing system (Abstract). In one embodiment, Hosseinzadeh’s system includes optical modulators, such as, Mach-Zehnder Interferometers (MZIs) that have two branches for optically encoding a signed real value and a signed imaginary value (Fig. 39A, [0412], [0460]. One branch encodes the phase).
It would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the present application to modify New so that the SLMs 101, 102 are MZIs, as taught by Hosseinzadeh, for better performance (for example, preventing losses due to backward reflection (by separating the optical paths to separate arms)).
Regarding claim 15, New/ Hosseinzadeh discloses the method according to claim 12.
New/Hosseinzadeh does not disclose encoding a signed magnitude and a signed orthogonal or quadrature phases on said optical signal.
Hosseinzadeh does not specify the encoded phases.
The parameter of the encoded phase is a result-effective variable, i.e., it is recognized to achieve a recognized result, for example, effecting the correlation between the inputs for the successive inputs.
New/Hosseinzadeh discloses the claimed invention except for the types of the encoded phases.
It would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the present application to modify New/Hosseinzadeh so that the encoded phases are orthogonal or quadrature, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art, In re Aller, 105 USPQ 233 (C.C.P.A. 1955).
In the current instance, the encoded phases is an art recognized result-effective variable in that it affects the processing of the successive inputs.
Thus, one would have been motivated to optimize the encoded phase because it is an art-recognized result-effective variable and it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977). See MPEP §2144.05(II)(B) “after KSR, the presence of a known result-effective variable would be one, but not the only, motivation for a personal of ordinary skill in the art to experiment to reach another workable product or process”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEONIDAS BOUTSIKARIS whose telephone number is (703)756-4529. The Examiner can normally be reached Mon. - Fr. 9.00-5.00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Stephone Allen, can be reached on 571-272-2334. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/L.B./
Patent Examiner, AU 2872
/STEPHONE B ALLEN/Supervisory Patent Examiner, Art Unit 2872
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