DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The following addresses Applicant’s remarks/amendments dated 24 June 2026.
Claims 11 and 17 were amended; Claim 22 was added; Claim 18 was cancelled; therefore, Claims 1-6, 8-17, and 19-22 are pending in the current application and will be addressed below.
Response to Arguments
Applicant’s arguments with respect to Claims 1 and 15 directed to the pulse shape circuitry have been considered but are not persuasive. Under the broadest reasonable interpretation consistent with the specification and how a person of ordinary skill in the art understands digital circuitry, “pulse shaping circuitry” reasonably encompasses circuitry that modifies, conditions, or restores the characteristics of a pulse, including its rise time, fall time, amplitude, slew rate, and edge integrity. Hynecek’s inverters perform these functions. As digital logic elements, inverters regenerate degraded pulses, restore logic levels, modify edge slopes and introduce propagation delay, all of which constitute pulse shaping under the broadest reasonable interpretation. Even when described as “buffering,” such buffering necessarily involves reshaping the incoming pulse to maintain signal integrity and drive subsequent circuitry. Accordingly, Hynecek’s inverters meet the claimed “pulse shape circuitry coupled to the avalanche photodiode,” and Applicant’s argument does not overcome the rejection.
Applicant’s arguments with respect to Claims 1 and 15 directed to the quench circuitry disposed in the second layer have been considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made and addressed below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-9, 11, 14-17, and 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over Hynecek (US 2018/0308881 A1).
Regarding Claim 1, Hynecek teaches a light detecting device ([Abstract] A back side illuminated image sensor may operate… for single photon detection) comprising;
an avalanche photodiode disposed in a first layer ([0025]-[0026] image sensor 14 includes a SOI substrate 101… In order to form the single-photon avalanche diode (SPAD));
readout circuitry disposed in a second layer and a third layer ([0025]-[0033] image sensor 14 includes a SOI substrate 101, a SOI circuit section 201 [second layer], and an application-specific integrated circuit (ASIC) chip section 301 [third layer]… analog pulse counting circuit 310 may include circuitry in the top chip (formed from SOI substrate 101 and SOI circuit portion 201) and circuitry in ASIC circuit 301), the readout circuitry including
quench circuitry coupled to the avalanche photodiode ([0033] The resulting pulse output may be fed to the gate of avalanche quenching transistor 403 and to the buffer circuit formed by transistors 408 and 409. Avalanche quenching transistor 403 may be a p-type transistor Examiner Note: Fig. 3 shows the quenching transistor 403 directly coupled to the SPAD node),
pulse shape circuitry coupled to the avalanche photodiode ([0033] The SPAD diode 402 may generate a pulse in response to an incident photon that is buffered by two inverters formed by transistors 404, 405, 406, and 407 Examiner Note: The inverters act as the pulse shaping mechanism), and
logic circuitry coupled to the pulse shape circuitry ([0034] Output from this buffer (formed by transistors 408 and 409) may drive the bump pad 410 that connects the top chip to the ASIC chip… The corresponding circuits of the ASIC chip may include a current source formed by the transistors 411 and 412 and the capacitor 414 Examiner Note: This processing logic in the ASIC is coupled to the pulse output from the SOI layer),
wherein the first layer, the second layer, and the third layer are stacked on each other ([0025] As shown in FIG. 2, image sensor 14 may include stacked chips… image sensor 14 includes a SOI substrate 101, a SOI circuit section 201, and an application-specific integrated circuit (ASIC) chip section 301),
wherein a portion of the quench circuitry is disposed in the second layer ([0030]-[0033] SOI circuit section 201 of the image sensor may include a fully depleted silicon layer 203… The resulting pulse output may be fed to the gate of avalanche quenching transistor 403), and
wherein the logic circuitry is disposed in the third layer ([0031]-[0032] The ASIC section 301 of the image sensor may include pulse counting pixel circuits 310 and the time-of-flight (ToF) to voltage converter pixel circuits 311… Details of the illustrative signal processing circuits (i.e., analog or digital pulse counting circuit 310 and ToF to voltage converter circuit 311) are shown in FIGS. 3 and 4).
It would have been obvious to a person of ordinary skill in the art to dispose the quench circuitry in the second layer as claimed. Hynecek already teaches the avalanche photodiode and quench transistor within the top=chip structure (block 401), which comprises both the first layer (SOI substrate 101) and the second layer (SOI circuitry portion 201). The specific placement of the quench circuitry within either of these layers represents a routine layout decision made to achieve predictable results such as simplified routing. Under KSR, rearranging known components within a multilayer chip in a manner that yields predictable performance is considered obvious design choice, absent any showing of criticality or unexpected results. Applicant has not demonstrated that locating the quench circuitry in the second layer provides any unexpected technical advantage over placement in the first layer. Accordingly, the claimed disposition of the quench circuitry in the second layer would have been an obvious design choice to a person of ordinary skill in the art, and does not render the claim patentable over Hynecek.
Regarding Claim 2, Hynecek teaches that the avalanche photodiode operates in a Geiger mode ([Abstract] using the single-photon avalanche diode (SPAD) concept in a Geiger mode of operation).
Regarding Claim 3, Hynecek teaches that the avalanche photodiode is a single-photon avalanche diode ([Abstract] using the single-photon avalanche diode (SPAD)).
Regarding Claim 4, Hynecek teaches that the readout circuitry includes multiple transistor circuit sections ([0025] , image sensor 14 includes a SOI substrate 101, a SOI circuit section 201, and an application-specific integrated circuit (ASIC) chip section 301… The SOI circuit section 201 of the image sensor may include a fully depleted silicon layer 203… The transistor gates are the regions 204… The ASIC section 301 of the image sensor may include pulse counting pixel circuits 310 and the time-of-flight (ToF) to voltage converter pixel circuits 311 built in the p-type doped region… For simplicity, certain details of the circuit cross section are omitted from FIG. 2), and
the multiple transistor circuit sections are stacked on each other in a stacking direction ([0025], [0030]-[0031] As shown in FIG. 2, image sensor 14 may include stacked chips… image sensor 14 includes a SOI substrate 101, a SOI circuit section 201, and an application-specific integrated circuit (ASIC) chip section 301).
Regarding Claim 5, Hynecek teaches that the multiple transistor circuit sections include the pulse shape circuitry ([0033] The SPAD diode 402 may generate a pulse in response to an incident photon that is buffered by two inverters formed by transistors 404, 405, 406, and 407) and the logic circuitry ([0034] Output from this buffer (formed by transistors 408 and 409) may drive the bump pad 410 that connects the top chip to the ASIC chip… The corresponding circuits of the ASIC chip may include a current source formed by the transistors 411 and 412 and the capacitor 414), the pulse shape circuitry configured to shape a pulse signal output from the avalanche photodiode ([0033] The SPAD diode 402 may generate a pulse in response to an incident photon that is buffered by two inverters formed by transistors 404, 405, 406, and 407 Examiner Note: The inverters act as the pulse shaping mechanism to buffer/condition the raw avalanche signal into a usable pulse), the logic circuitry configured to process the pulse signal output that is shaped by the pulse shaping circuitry ([0031] The ASIC section 301 of the image sensor may include pulse counting pixel circuits 310… built in the p-type doped region… [0035] When the SPAD pulses are detected, the resulting current pulses gradually charge the capacitor 414 and its bias voltage change is detected at the node 418 Examiner Note: This counting/integration function is the processing logic that acts on the output provided by the inverters/shaping circuitry).
Regarding Claim 6, Hynecek teaches that the quench circuitry is configured to suppress avalanche multiplication of the avalanche photodiode ([0014] The light sensing diode is biased slightly above its breakdown point and when an incident photon generates an electron or hole, this carrier initiates an avalanche breakdown with additional carriers being generated. The process needs to be stopped (quenched) by lowering the diode bias below its breakdown point. This is called the Geiger mode of SPAD operation).
Regarding Claim 8, Hynecek teaches that the avalanche photodiode, the quench circuitry, and the pulse shape circuitry are stacked in a stacking direction ([0025] As shown in FIG. 2, image sensor 14 may include stacked chips… image sensor 14 includes a SOI substrate 101, a SOI circuit section 201, and an application-specific integrated circuit (ASIC) chip section 301… [0033] The SPAD diode 402 may generate a pulse in response to an incident photon that is buffered by two inverters formed by transistors 404, 405, 406, and 407… The resulting pulse output may be fed to the gate of avalanche quenching transistor 403 and to the buffer circuit formed by transistors 408 and 409 Examiner Note: Fig. 2 illustrates that the diode in layer 101 is vertically stacked with the quenching and shaping transistors located in layer 201), and wherein the avalanche photodiode, the quench circuitry, and the pulse shape circuitry are electrically coupled to each other by an electrical conductor that extends in the stacking direction ([0030] The transistor gates are the regions 204 and the contact vias are the regions 205 [0033] he SPAD diode 402 may generate a pulse in response to an incident photon that is buffered by two inverters formed by transistors 404, 405, 406, and 407… The resulting pulse output may be fed to the gate of avalanche quenching transistor 403 and to the buffer circuit formed by transistors 408 and 409 Examiner Note: Fig. 2 shows that the vertical contact via 205 is the electrical conductor that extends in the stacking direction to couple the output of the first diode in layer 101 to the shared circuit node of the quench and shaping transistors in the second layer 201).
Regarding Claim 9, Hynecek teaches that the electrical conductor is electrically coupled to the quench circuitry and the pulse shape circuitry by a contact section ([0030] The transistor gates are the regions 204 and the contact vias are the regions 205… The metal wirings in this section of the pixel are the regions 206… [0033] The resulting pulse output may be fed to the gate of avalanche quenching transistor 403 and to the buffer circuit formed by transistors 408 and 409 Examiner Note: The vertical via 205 (conductor) is physically connected to the horizontal metal wiring 206, which then distributes the signal to the gates of the quenching and shaping transistors).
Regarding Claim 11, Hynecek teaches that a first semiconductor chip includes the first layer and the second layer, and a second semiconductor chip includes the third layer ([0025] As shown in FIG. 2, image sensor 14 may include stacked chips… image sensor 14 includes a SOI substrate 101, a SOI circuit section 201, and an application-specific integrated circuit (ASIC) chip section 301).
Regarding Claim 14, Hynecek teaches that the avalanche photodiode has a back-illuminated pixel structure that takes in light applied from a substrate back surface side ([0011] specifically to photon counting CMOS image sensor arrays with pixels that use single-photon avalanche diodes (SPADs) for single photon detection and that are illuminated from the back side of the substrate… [0025] The SOI substrate section 101 may include a silicon epitaxial layer 102 that has a P+ doped region 103 deposited at the back side surface interface (facing the light illumination flow)) in a case where a side on which a wiring layer is provided, is regarded as a substrate front surface side ([0030] The metal wirings in this section of the pixel are the regions 206 with bump pad 207 Examiner Note: Fig. 2 Shows light 113 incident on the back side surface interface of substrate 101 while the wiring 206 is provided on the opposite substrate front side of the circuit section 201).
Regarding Claim 15, Hynecek teaches a distance measuring apparatus ([0039] One advantage of using the ToF to voltage conversion circuit of FIG. 4 is that the global ramp slope can be changed, which corresponds to a range change of the distance measurement) comprising:
a light source unit that applies light to a distance measurement target ([0037] The global ramp start may be coincidental with the scene illumination pulse (e.g., from an infrared light source). When the SPAD pulse is later detected, the detection corresponds to the reflected photon from the scene); and
a light receiving device that receives reflected light from the distance measurement target, the reflected light being based on the light applied from the light source unit ([0037] When the SPAD pulse is later detected, the detection corresponds to the reflected photon from the scene), wherein
the light receiving device includes
an avalanche photodiode disposed in a first layer ([0025]-[0026] image sensor 14 includes a SOI substrate 101… In order to form the single-photon avalanche diode (SPAD));
readout circuitry disposed in a second layer and a third layer ([0025]-[0033] image sensor 14 includes a SOI substrate 101, a SOI circuit section 201 [second layer], and an application-specific integrated circuit (ASIC) chip section 301 [third layer]… analog pulse counting circuit 310 may include circuitry in the top chip (formed from SOI substrate 101 and SOI circuit portion 201) and circuitry in ASIC circuit 301), the readout circuitry including
quench circuitry coupled to the avalanche photodiode ([0033] The resulting pulse output may be fed to the gate of avalanche quenching transistor 403 and to the buffer circuit formed by transistors 408 and 409. Avalanche quenching transistor 403 may be a p-type transistor Examiner Note: Fig. 3 shows the quenching transistor 403 directly coupled to the SPAD node),
pulse shape circuitry coupled to the avalanche photodiode ([0033] The SPAD diode 402 may generate a pulse in response to an incident photon that is buffered by two inverters formed by transistors 404, 405, 406, and 407 Examiner Note: The inverters act as the pulse shaping mechanism), and
logic circuitry coupled to the pulse shape circuitry ([0034] Output from this buffer (formed by transistors 408 and 409) may drive the bump pad 410 that connects the top chip to the ASIC chip… The corresponding circuits of the ASIC chip may include a current source formed by the transistors 411 and 412 and the capacitor 414 Examiner Note: This processing logic in the ASIC is coupled to the pulse output from the SOI layer),
wherein the first layer, the second layer, and the third layer are stacked on each other ([0025] As shown in FIG. 2, image sensor 14 may include stacked chips… image sensor 14 includes a SOI substrate 101, a SOI circuit section 201, and an application-specific integrated circuit (ASIC) chip section 301),
wherein a portion of the quench circuitry is disposed in the second layer ([0030]-[0033] SOI circuit section 201 of the image sensor may include a fully depleted silicon layer 203… The resulting pulse output may be fed to the gate of avalanche quenching transistor 403), and
wherein the logic circuitry is disposed in the third layer ([0031]-[0032] The ASIC section 301 of the image sensor may include pulse counting pixel circuits 310 and the time-of-flight (ToF) to voltage converter pixel circuits 311… Details of the illustrative signal processing circuits (i.e., analog or digital pulse counting circuit 310 and ToF to voltage converter circuit 311) are shown in FIGS. 3 and 4).
It would have been obvious to a person of ordinary skill in the art to dispose the quench circuitry in the second layer as claimed. Hynecek already teaches the avalanche photodiode and quench transistor within the top=chip structure (block 401), which comprises both the first layer (SOI substrate 101) and the second layer (SOI circuitry portion 201). The specific placement of the quench circuitry within either of these layers represents a routine layout decision made to achieve predictable results such as simplified routing. Under KSR, rearranging known components within a multilayer chip in a manner that yields predictable performance is considered obvious design choice, absent any showing of criticality or unexpected results. Applicant has not demonstrated that locating the quench circuitry in the second layer provides any unexpected technical advantage over placement in the first layer. Accordingly, the claimed disposition of the quench circuitry in the second layer would have been an obvious design choice to a person of ordinary skill in the art, and does not render the claim patentable over Hynecek.
Regarding Claim 16, Hynecek teaches that the avalanche photodiode, the quench circuitry, and the pulse shape circuitry are stacked in a stacking direction ([0025] As shown in FIG. 2, image sensor 14 may include stacked chips… image sensor 14 includes a SOI substrate 101, a SOI circuit section 201, and an application-specific integrated circuit (ASIC) chip section 301… [0033] The SPAD diode 402 may generate a pulse in response to an incident photon that is buffered by two inverters formed by transistors 404, 405, 406, and 407… The resulting pulse output may be fed to the gate of avalanche quenching transistor 403 and to the buffer circuit formed by transistors 408 and 409 Examiner Note: Fig. 2 illustrates that the diode in layer 101 is vertically stacked with the quenching and shaping transistors located in layer 201), and wherein the avalanche photodiode, the quench circuitry, and the pulse shape circuitry are electrically coupled to each other by an electrical conductor that extends in the stacking direction ([0030] The transistor gates are the regions 204 and the contact vias are the regions 205 [0033] he SPAD diode 402 may generate a pulse in response to an incident photon that is buffered by two inverters formed by transistors 404, 405, 406, and 407… The resulting pulse output may be fed to the gate of avalanche quenching transistor 403 and to the buffer circuit formed by transistors 408 and 409 Examiner Note: Fig. 2 shows that the vertical contact via 205 is the electrical conductor that extends in the stacking direction to couple the output of the first diode in layer 101 to the shared circuit node of the quench and shaping transistors in the second layer 201).
Regarding Claim 17, Hynecek teaches that the logic circuitry includes one of a counter or a time-to-digital converter (TDC) ([0031] The ASIC section 301 of the image sensor may include pulse counting pixel circuits 310).
Regarding Claim 19, Hynecek teaches that the second layer includes one or more transistors with a light receiving side facing the avalanche photodiode and a second side opposite to the light receiving side and facing away from the avalanche photodiode ([0030] The SOI circuit section 201 of the image sensor may include a fully depleted silicon layer 203 deposited over the oxide layers 202… The transistor gates are the regions 204 and the contact vias are the regions 205 Examiner Note: Fig. 2 Shows the silicon layer 203 facing the photodiode 101/102, while the gates 204 face away from the photodiode 101/102 toward the ASIC 301), and wherein the one or more transistors are electrically connected to the avalanche photodiode on the second side ([0030] The metal wirings in this section of the pixel are the regions 206 with bump pad 207 (sometimes referred to as an interconnect layer) that is connected to underlying ASIC chip 301 Examiner Note: Fig. 2 Shows the electrical path through the circuit section 201 to the metal wirings 206 and bump pads 207 located on the side facing away from the photodiode 101/102).
Regarding Claim 20, Hynecek teaches that the second layer includes a wiring layer disposed adjacent to the second side ([0030] The metal wirings in this section of the pixel are the regions 206 with bump pad 207 (sometimes referred to as an interconnect layer) that is connected to underlying ASIC chip 301 Examiner Note: Fig. 2 Shows metal wirings 206 and bump pads 207 located on the side of the SOI circuit section 201 that faces the ASIC chip section 301, which is the side opposite the light-receiving silicon layer 203).
Regarding Claim 21, Hynecek teaches that the second layer includes a PMOS transistor and an NMOS transistor ([0011] The following relates to solid-state image sensor arrays, specifically to photon counting CMOS image sensor arrays with pixels that use single-photon avalanche diodes (SPADs)… [0030] The SOI circuit section 201 of the image sensor may include a fully depleted silicon layer 203 deposited over the oxide layers 202 (OX) with the P+ [PMOS] or N+ [NMOS] doped regions 208 under the contacts depending on the type of SOI transistor used. The transistor gates are the regions 204 and the contact vias are the regions 205. Examiner Note: CMOS architecture requires both NMOS and PMOS).
Claims 10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Hynecek (US 2018/0308881 A1) in view of Wang et al. (US 20220149098 A1).
Regarding Claim 10, Hynecek is not relied upon as teaching that an interface between the second layer and the third layer includes a junction using a stacked copper-to-copper (Cu-Cu) connection.
However, Wang teaches that an interface between the second layer and the third layer includes a junction using a stacked copper-to-copper (Cu-Cu) connection ([0388] the sensor wafer 5800 is fabricated separately from the logic ASICs wafer 5802 and then bonded together… where metal electrodes 5822 and 5824 such as copper or copper alloy are bonded at the interface.).
Hynecek and Wang are considered to be analogous to the claimed invention because they are both used in the same field of stacked CMOS image sensors utilizing single-photon avalanche diodes (SPADs). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the stacked chip connection of Hynecek to include the copper-to-copper connection of Wang with a reasonable expectation of success. This modification would have been motivated by the desire to increase pixel density and reduce the overall footprint of the sensor array. While Hynecek teaches a general stacked structure using bump pads, Wang explicitly teaches that in high performance stacked sensors “metal electrodes 5822 and 5824 such as copper… are bonded at the interface” [0388]. A person of ordinary skill in the art would be motivated to replace the solder bumps of Hynecek with the Cu-Cu hybrid bonding of Wang because it allows for a significantly finer interconnect pitch compared to traditional micro-bumps. This yields the predictable result of an image sensor with improved resolution and higher integration density without increasing the physical size of the chip.
Regarding Claim 12, Hynecek is not relied upon as teaching that the first semiconductor chip and the second semiconductor chip are electrically coupled to each other via a junction using a copper electrode.
However, Wang teaches that the first semiconductor chip and the second semiconductor chip are electrically coupled to each other via a junction using a copper electrode ([0338] the sensor wafer 5800 is fabricated separately from the logic ASICs wafer 5802 and then bonded together… where metal electrodes 5822 and 5824 such as copper or copper alloy are bonded at the interface. Also shown are the connecting electrodes 5820).
Hynecek and Wang are considered to be analogous to the claimed invention because they are both in the same field of stacked SPAD image sensors. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the interconnect structure of Hynecek to include the copper electrode of Wang with a reasonable expectation of success. This modification would have been motivated by the desire to improve electrical conductivity and thermal stability at the chip-to-chip interface. Why Hynecek teaches that the top chip and ASIC are connected via “bump pads 207” [0030], Wang teaches the use of “metal electrodes 5822 and 5824 such as copper” [0388] for the coupling of stacked wafers. A person of ordinary skill in the art would be motivated to utilize copper electrodes specifically because copper offers lower resistivity and higher electromigration resistance than traditional solder-based materials. Implementing the copper electrodes of wang into the stacked architecture of Hynecek would yield the predictable result of a more robust electrical coupling with reduced parasitic resistance, thereby enhancing the performance of the photon-counting circuitry.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Hynecek (US 2018/0308881 A1) in view of Chhabria et al. (US 11601607 B2).
Regarding Claim 13, Hynecek teaches that an analogue circuit section is provided in pixel units together with the avalanche photodiode ([0011] photon counting CMOS image sensor arrays with pixels that use single-photon avalanche diodes (SPADs) for single photon detection… [0030] The SOI circuit section 201 of the image sensor may include a fully depleted silicon layer 203… The fully depleted transistors used in these pixels help achieve high speeds of operation and low parasitic capacitances… The metal wirings in this section of the pixel are the regions 206… [0033] In FIG. 3, the circuitry in the top chip is shown in block 401. Analog SPAD pulse counting circuit 310 may include a single-photon avalanche diode (SPAD) 402), the analogue circuit section including the quench circuitry ([0033] The resulting pulse output may be fed to the gate of avalanche quenching transistor 403 and to the buffer circuit formed by transistors 408 and 409),
a digital circuit section includes the logic circuitry ([0031] The ASIC section 301 of the image sensor may include pulse counting pixel circuits 310 and the time-of-flight (ToF) to voltage converter pixel circuits 311 built in the p-type doped region… [0035] the resulting current pulses gradually charge the capacitor 414 and its bias voltage change is detected at the node 418).
Hynecek is not relied upon as teaching that the digital circuit section is shared by the analogue circuit section including multiple pixels.
However, Chhabria teaches that the digital circuit section is shared by the analogue circuit section including multiple pixels ([Col. 7 ll. 60-66] a single memory bank is shared by multiple photodiodes, and the quantization of the output of one photodiode needs to be put on hold until the quantization result stored in the memory bank is read out and can be erased, the arrangements above can reduce the delay introduced to the quantization operations and can improve the operational speed of the image sensor).
Hynecek and Chhabria are considered to be analogous to the claimed invention because they are both in the same field of CMOS image sensors utilizing single-photon avalanche diodes (SPADs). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the ASIC section 301 of Hynecek to include shared digital circuits (such as the memory banks) of Chhabria with a reasonable expectation of success. This modification would have been motivated by the desire to optimize the balance between sensor resolution and silicon area efficiency. By integrating Chhabria’s teaching of sharing a single memory bank among multiple photodiodes into Hynecek’s stacked chip architecture, the system can reduce the overall power consumption and physical size of the image sensor array. A person of ordinary skill in the art would recognize that reducing the footprint of the digital logic through sharing would yield the predictable result of allowing for a higher density of SPAD pixels within the sensing layer while simultaneously improving the operational speed of the quantization process.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Hynecek (US 2018/0308881 A1) in view of Snow et al. (US 2011/0205522 A1).
Regarding Claim 22, Hynecek teaches that the pulse shaping circuitry includes a[n] inverter configured to detect a reaction edge ([0033] The SPAD diode 402 may generate a pulse in response to an incident photon that is buffered by two inverters formed by transistors 404, 405, 406, and 407 Examiner Note: The inverters act as the pulse shaping mechanism to buffer/condition the raw avalanche signal into a usable pulse).
Hynecek is not relied upon as teaching that the pulse shaping circuitry includes a single CMOS inverter, wherein the single CMOS inverter includes a single P-type and N-type transistor pair.
However, Snow teaches that the pulse shaping circuitry includes a single CMOS inverter, wherein the single CMOS inverter includes a single P-type and N-type transistor pair ([0023] In one embodiment an enhanced inverter is implemented with a PMOS-NMOS transistor pair coupled between first and second sources of operating potential. The CMOS inverter further includes an input logic circuit cross-coupled between the CMOS inverter input and gates of the PMOS and the NMOS transistors to prevent simultaneous ON condition of both transistors).
Hynecek and Snow are considered to be analogous to the claimed invention because they are both in the same field of SPAD front-end circuitry and pulse conditioning logic. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the pulse shaping circuitry of Hynecek to include the single CMOS inverter comprising a complementary P-type/N-type transistor pair as taught by Snow with a reasonable expectation of success. This modification would have been motivated by the desire to reduce circuitry area, minimize propagation delay, and simplify routing while still providing reliable edge detection and pulse conditioning. By integrating Snow’s teaching of a single CMOS inverter used for edge detection and pulse restoration into Hynecek, the system can generate a clean, conditioned pulse suitable for subsequent digital processing using fewer transistors and lower power. A person of ordinary skill in the art would recognize that substituting a single CMOS inverter for the multi-stage inverter configuration of Hynecek would yield the predictable result of achieving equivalent pulse-shaping functionality with reduced complexity and improved efficiency.
Conclusion
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/E.H.H./Patent Examiner, Art Unit 3645
/HELAL A ALGAHAIM/SPE , Art Unit 3645
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