DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Remarks Claim 1 recites “each of the second floating-point binary value and the second logarithmic binary value being in an FPLNS data format, the second floating-point binary value in the FPLNS format” in lines 11-13. Perhaps Applicant may want to amend the claim to recite “each of the second floating-point binary value and the second logarithmic binary value being in the FPLNS data format, the second floating-point binary value in the FPLNS format ” instead to avoid for better clarity. Priority The present application, 18045804, filed 10/11/2022 claims Priority from Provisional Application 63254053, filed 10/08/2021. Information Disclosure Statement The information disclosure statement (IDS) submitted on 11/22/2022, 03/29/2023, and 11/07/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following must be shown or the feature(s) canceled from the claim(s) : A. access registers containing a first floating-point binary value as specified in claims 1 and 10. B. access registers containing a second floating-point binary value as specified in claims 1 and 10. No new matter should be entered. The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: 410, 420 and 430 mentioned in paragraphs [0049-0050] The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: 1106 and 1128 . Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification The specification is objected to under 37 C.F.R. 1.74, which requires the detailed description to refer to the different parts of the figures by use of reference letters or reference numerals. Implicit in this rule is that the detailed description correctly reference the figures. In this application the figures and detailed description are inconsistent as explained below. In paragraph [0045] line 1, “FPLNS system 300” should read “FPLNS system 200” instead. In paragraph [0049] line 2, “sign bit 410” should read “sign bit 310” instead. In paragraph [0040] line 2 “exponent bits 420” should read “exponent bits 320” instead. In paragraph [0040] line 3 “mantissa bits 430” should read “mantissa bits 330” instead. Claim Objections Claims 1- 18 are objected to under 37 C.F.R. 1.71(a) which requires “full, clear, concise, and exact terms” as to enable any person skilled in the art or science to which the invention or discovery appertains, or with which it is most nearly connected, to make and use the same. The following should be corrected. A. In claim 1 lines 12-13, “an FPLNS data format” should read “the FPLNS data format” instead because an FPLNS data format is already introduced in line 7. Claim 10 recites a similar limitation in lines 11-12 and is objected to for the same reason. Claims 2-9 inherit the same deficiency as claim 1 by reason of dependence. Claims 11-18 inherit the same deficiency as claim 9 by reason of dependence. B. In claim 11 lines 3-4, “converting the first floating-point binary value including to the first logarithmic binary value:” should read “converting the first floating-point binary value to the first logarithmic binary value including:” instead for better clarity. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim s 2, 9, 11 and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 2 recites “subtract the bias constant from the second total to form the first logarithmic binary value” in lines 20-21. Lines 10-11 recites “subtract the bias constant from the first total to form the first logarithmic binary value”. Therefore, it is unclear whether the limitation recited in lines 20-21 is replacing how the first logarithmic binary value is calculated or whether this is meant to define how the second logarithmic binary value is formed. For purposes of examination, lines 20-21 is interpreted as “subtract the bias constant from the second total to form the second logarithmic binary value” instead. Claim 11 recites a similar limitation and is rejected for the same reason. Claim 9 recites “the fourth logarithmic binary value” in line 7; and “the second shifted bias value” in line 10. There is insufficient antecedent basis for these limitations in the claim. For purposes of examination, these are interpreted as a fourth logarithmic binary value and a second shifted bias value respectively. Claim 18 recites a similar limitation and is rejected for the same reason. Further, claim 9 recites “adding the second corrected bias value from the first logarithmic sum to form a second result” in lines 13-14. This limitation is unclear because this limitation is part of the sub-steps for dividing the third floating-point binary value and the fourth floating-point binary value, however, it is using operands or values used in multiplying the first floating-point binary value and the second floating-point binary value. . For purposes of examination, this is interpreted as “adding the second corrected bias value from the first logarithmic difference to form a second result”. Claim 18 recites a similar limitation and is rejected for the same reason. Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-18 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. Under Step 1, claims 1-9 recite a system and, therefore, is a machine. Claims 10-18 recite a series of steps and, therefore, is a process. Under Step 2A prong 1, claim 1 recites A system comprising: an integrated circuit including a hardware inexact floating-point logarithmic number system (FPLNS) multiplier configured to perform FPLNS functions , the integrated circuit configured to: access registers containing a first floating-point binary value and a first logarithmic binary value of the first floating-point binary value, each of the first floating-point binary value and the first logarithmic binary value being in an FPLNS data format, the first floating-point binary value in the FPLNS format including a sign bit followed by exponent bits, the exponent bits followed by mantissa bits ; access registers containing a second floating-point binary value and a second logarithmic binary value of the second floating-point binary value, each of the second floating-point binary value and the second logarithmic binary value being in an FPLNS data format, the second floating-point binary value in the FPLNS format ; multiplying , by the FPLNS multiplier, the first floating-point binary value and the second floating-point binary value , the FPLNS multiplier configured to: add , by the FPLNS multiplier, the first logarithmic binary value to the second logarithmic binary value to form a first logarithmic sum , shift a bias constant by a number of bits of the mantissa of the first floating-point binary value to form a first shifted bias value , subtract a correction factor from the first shifted bias value to form a first corrected bias value , and subtract the first corrected bias value from the first logarithmic sum to form a first result ; and the integrated circuit being further configured to perform an antilogarithm on the first result to generate a multiplication result of the multiplication of the first floating-point binary value and the second floating-point binary value . The above underlined limitations of calculating a product of a first floating-point value and a second floating-point value using their respective logarithmic value to perform the multiplication using add, shift, subtract and antilogarithm operations amounts to processing mathematical relationships/calculations and falls within the “Mathematical Concepts” and “Mental Processes” grouping of abstract ideas. The step of “multiplying” including the sub-steps of “add”, “shift”, “subtract”, “subtract” and “perform an antilogarithm” is a process that under its broadest reasonable interpretation, covers performance of the limitation in the mind. That is, other than reciting “by the FPLNS multiplier” and “the integrated circuit”, nothing in the claim element precludes the step from practically being performed in the human mind. For example, but for the reciting “by the FPLNS multiplier” and “the integrated circuit” language, the claim encompasses manually multiplying a first and second binary floating-point numbers by converting the first and second binary floating-point numbers into first and second binary logarithmic numbers; adding the first and second binary logarithmic numbers to generate a sum; shifting a bias constant by the number of bits of the mantissa of the first binary floating-point number to generate a shifted bias constant, subtracting a correction factor from the shifted bias constant to generate a corrected bias value; subtracting the corrected bias value to the sum to generate a corrected sum; and taking an antilogarithm of the corrected sum to generate the product of the first and second binary floating-point numbers as described in at least Figs. 7A-7B and paragraphs [0078 and 0084-0085] using pen and paper. Accordingly, the claim is directed to recite an abstract idea. Under step 2A prong 2, the claim recites the following additional elements: an integrated circuit including a hardware inexact floating-point logarithmic number system (FPLNS) multiplier , the integrated circuit configured to: access registers containing a first floating-point binary value and a first logarithmic binary value of the first floating-point binary value; access registers containing a second floating-point binary value and a second logarithmic binary value of the second floating-point binary value. However, the additional elements of “an integrated circuit”, “a hardware inexact floating-point logarithmic number system ( FPLNS) multiplier ” and “registers” are recited at a high-level of generality (i.e., as an integrated circuit comprising a generic FPLNS multiplier without reciting any particular configuration with specific circuit structure of the FLPNS multiplier; and as generic registers for storing data) such that they amount to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or merely as tools to implement the abstract idea. The additional elements of “access registers containing a first floating-point binary value and a first logarithmic binary value of the first floating-point binary value” and “access registers containing a second floating-point binary value and a second logarithmic binary value of the second floating-point binary value” are merely adding insignificant extra-solution activities, i.e. mere data gathering. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application. Under step 2B, claim 1 does not include additional elements that, individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “an integrated circuit”, “a hardware inexact floating-point logarithmic number system (FPLNS) multiplier” and “registers” are recited at a high-level of generality (i.e., as an integrated circuit comprising a generic FPLNS multiplier without reciting any particular configuration with specific circuit structure of the FLPNS multiplier; and as generic registers for storing data) such that they amount to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or merely as tools to implement the abstract idea. The additional elements of “access registers containing a first floating- point binary value and a first logarithmic binary value of the first floating-point binary value” and “access registers containing a second floating-point binary value and a second logarithmic binary value of the second floating-point binary value” are merely adding insignificant extra-solution activities, i.e. mere data gathering. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Receiving or transmitting data over a network” and “Storing and retrieving information in memory” as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea. Under step 2A prong 1, claims 2-9 recite the same abstract idea as claim 1 by reason of dependence. Further, claim 2 recites further abstract idea of “convert the first floating-point binary value to the first logarithmic binary value comprising: determine a base-2 logarithm of a quantity of one plus a mantissa of the first floating-point binary value to form a first log quantity, add the first log quantity to the exponent of the first floating-point binary value to form a first total, and subtract the bias constant from the first total to form the first logarithmic binary value, and convert the second floating-point binary value to the second logarithmic binary value, the first floating-point binary value being in the FPLNS format, convert the second floating-point binary value to the second logarithmic binary value comprising: determine a base-2 logarithm of a quantity of one plus a mantissa of the second floating-point binary value to form a second log quantity, add the second log quantity to the exponent of the second floating-point binary value to form a second total, and subtract the bias constant from the second total to form the first logarithmic binary value”; claim 3 recites further details of the abstract idea of “the multiplication result being in the FPLNS format”; claim 4 recites further details of the abstract idea of “the bias constant being 2 (E-1) -1, where E is the number of bits in the exponent of the first floating-point binary value in the FPLNS format”; claim 6 recites further details of the abstract idea of “wherein the correction factor is within a range of 0.04 to 0.06”; claim 7 recites further details of the abstract idea of “wherein the exponent bits of the first floating-point binary value in the FPLNS format are positioned such that a highest exponent bit of the exponent bits is closest to the sign bit and a lowest exponent bit is closest to the mantissa bits, the mantissa bits of the first floating-point binary value of the FPLNS format being positioned such that the highest mantissa bit of the mantissa bits is closest to the exponent bits and the lowest mantissa bit is farthest from the exponent bits”; claim 8 recites further details of the abstract idea of “wherein the exponent bits of the first logarithmic binary value in the FPLNS format are positioned such that the highest exponent bit of the exponent bits is closest to the sign bit and the lowest exponent bit is closest to the mantissa bits, the mantissa bits of the first logarithmic binary value of the FPLNS format being positioned such that the highest mantissa bit of the mantissa bits is closest to the exponent bits and the lowest mantissa bit is farthest from the exponent bits” ; claim 9 recites further abstract idea of “divide a third floating-point binary value and a fourth floating-point binary value, the third floating-point binary value and the fourth floating-point binary value being in the FPLNS data format, divide the third floating-point binary value and the fourth floating-point binary value by: subtracting a third logarithmic binary value of the third floating-point binary value from the fourth logarithmic binary value of the fourth floating-point binary value to form a first logarithmic difference, shifting the bias constant by a number of bits of the mantissa of the third floating-point binary value to form the second shifted bias value, subtracting the correction factor from the second shifted bias value to form a second corrected bias value, and adding the second corrected bias value from the first logarithmic sum to form a second result; and perform an antilogarithm on the second result to generate a division result of the division of the third floating-point binary value and the fourth floating-point binary value ” which falls within the “Mathematical Concepts” and/or “Mental Processes” grouping of abstract ideas. In particular claims 3-4 and 6-9 do not include additional elements that would require further analysis under step 2A prong 2 and step 2B. Accordingly, the claims are directed to recite an abstract idea. Under step 2A prong 2, claim 2 recites the following additional elements: a processor. Claim 5 recites the following additional elements “retrieves the correction factor from one or more registers that do not contain the first floating-point binary value, the first logarithmic binary value, the second floating-point binary value, and the second logarithmic binary value”. However, the additional elements of “a processor” in claim 2 ; and “one or more registers “ in claim 5 are recited at a high-level of generality (i.e., as a generic processor for converting a data format for the first and second floating-point values to the first and second logarithmic values; and as generic registers for storing data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “retrieves the correction factor from one or more registers that do not contain the first floating-point binary value, the first logarithmic binary value, the second floating-point binary value, and the second logarithmic binary value” in claim 5 is merely adding insignificant extra-solution activity, i.e. mere data gathering . The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application. Under step 2B, claims 2 and 5 does not include additional elements that, individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a processor” in claim 2 ; and “one or more registers “ in claim 5 are recited at a high-level of generality (i.e., as a generic processor for converting a data format for the first and second floating-point values to the first and second logarithmic values; and as generic registers for storing data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “retrieves the correction factor from one or more registers that do not contain the first floating-point binary value, the first logarithmic binary value, the second floating-point binary value, and the second logarithmic binary value” in claim 5 is merely adding insignificant extra-solution activity, i.e. mere data gathering. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Receiving or transmitting data over a network” and “Storing and retrieving information in memory” as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claims do not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claims do not amount to significantly more than the abstract idea. Regarding claims 10-18, they are directed to a method practiced by the system of claims 1-9 respectively. All steps performed by the method of claims 10-18 would be practiced by the system of claims 1-9 respectively. Claims 1-9 analysis applies equally to claims 10-18 respectively. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-18 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-18 of copending Application No. 19091282 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-18 under examination are anticipated, respectively, by claims 1-18 of the reference application. Every limitation in the application under examination claims is recited in the conflicting reference application claims as shown in the Table below. 18045804 19091282 Claim 1. A system comprising: Claim 1. A system comprising: an integrated circuit including a hardware inexact floating-point logarithmic number system (FPLNS) multiplier configured to perform FPLNS functions, the integrated circuit configured to: A hardware inexact floating-point logarithmic number system (FPLNS) configured to perform FPLNS functions comprising two inputs, an operation input, a correction input, and an output, the FPLNS including an FPLNS multiplier, the hardware configured to: access registers containing a first floating-point binary value and a first logarithmic binary value of the first floating-point binary value, each of the first floating-point binary value and the first logarithmic binary value being in an FPLNS data format, the first floating-point binary value in the FPLNS format including a sign bit followed by exponent bits, the exponent bits followed by mantissa bits; access registers, over one of two inputs, containing a first floating-point binary value and a first logarithmic binary value of the first floating-point binary value, each of the first floating-point binary value and the first logarithmic binary value being in an FPLNS data format, the first floating-point binary value in the FPLNS format including a sign bit followed by exponent bits, the exponent bits followed by mantissa bits; access registers containing a second floating-point binary value and a second logarithmic binary value of the second floating-point binary value, each of the second floating-point binary value and the second logarithmic binary value being in an FPLNS data format, the second floating-point binary value in the FPLNS format; access registers, over an other of the two inputs, containing a second floating- point binary value and a second logarithmic binary value of the second floating-point binary value, each of the second floating-point binary value and the second logarithmic binary value being in an FPLNS data format, the second floating-point binary value in the FPLNS format; multiplying, by the FPLNS multiplier, the first floating-point binary value and the second floating-point binary value, the FPLNS multiplier configured to: multiplying, by the FPLNS multiplier, the first floating-point binary value and the second floating-point binary value, the FPLNS multiplier configured to: add, by the FPLNS multiplier, the first logarithmic binary value to the second logarithmic binary value to form a first logarithmic sum, add, by the FPLNS multiplier, the first logarithmic binary value to the second logarithmic binary value to form a first logarithmic sum, shift a bias constant by a number of bits of the mantissa of the first floating-point binary value to form a first shifted bias value, shift a bias constant by a number of bits of the mantissa of the first floating-point binary value to form a first shifted bias value, subtract a correction factor from the first shifted bias value to form a first corrected bias value, and subtract a correction factor from the first shifted bias value to form a first corrected bias value, and subtract the first corrected bias value from the first logarithmic sum to form a first result; and subtract the first corrected bias value from the first logarithmic sum to form a first result; and the integrated circuit being further configured to perform an antilogarithm on the first result to generate a multiplication result of the multiplication of the first floating-point binary value and the second floating-point binary value. the hardware FPLNS being further configured to perform an antilogarithm on the first result to generate a multiplication result of the multiplication of the first floating-point binary value and the second floating-point binary value. Mapping for the other claims is not being shown for purpose of brevity. This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented. Claim s 1-2, 4-5, 7-11, 13-14 and 16-18 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1-20 of copending Application No. 19091302 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-2, 4-5, 7-11, 13-14 and 16-18 under examination are anticipated, respectively, by claims 1 -2, 4-5, 9-13, 15-16, 20 and 10- 11 of the reference application. Every limitation in the application under examination claims is recited in the conflicting reference application claims as shown in the Table below. 18045804 19091302 Claim 1. A system comprising: Claim 1. A system comprising: an integrated circuit including a hardware inexact floating-point logarithmic number system (FPLNS) multiplier configured to perform FPLNS functions, the integrated circuit configured to: a first integrated circuit including a first hardware inexact floating-point logarithmic number system (FPLNS) multiplier configured to perform FPLNS functions, the first integrated circuit configured to: access registers containing a first floating-point binary value and a first logarithmic binary value of the first floating-point binary value, each of the first floating-point binary value and the first logarithmic binary value being in an FPLNS data format, the first floating-point binary value in the FPLNS format including a sign bit followed by exponent bits, the exponent bits followed by mantissa bits; access registers containing a first floating-point binary value and a first logarithmic binary value of the first floating-point binary value, each of the first floating- point binary value and the first logarithmic binary value being in an FPLNS data format, the first floating-point binary value in the FPLNS format including a sign bit followed by exponent bits, the exponent bits followed by mantissa bits; access registers containing a second floating-point binary value and a second logarithmic binary value of the second floating-point binary value, each of the second floating-point binary value and the second logarithmic binary value being in an FPLNS data format, the second floating-point binary value in the FPLNS format; access registers containing a second floating-point binary value and a second logarithmic binary value of the second floating-point binary value, each of the second floating-point binary value and the second logarithmic binary value being in an FPLNS data format, the second floating-point binary value in the FPLNS format; multiplying, by the FPLNS multiplier, the first floating-point binary value and the second floating-point binary value, the FPLNS multiplier configured to: multiplying, by the first FPLNS multiplier, the first floating-point binary value and the second floating-point binary value, the first FPLNS multiplier configured to: add, by the FPLNS multiplier, the first logarithmic binary value to the second logarithmic binary value to form a first logarithmic sum, add, by the first FPLNS multiplier, the first logarithmic binary value to the second logarithmic binary value to form a first logarithmic sum, shift a bias constant by a number of bits of the mantissa of the first floating-point binary value to form a first shifted bias value, shift a bias constant by a number of bits of the mantissa of the first floating-point binary value to form a first shifted bias value, subtract a correction factor from the first shifted bias value to form a first corrected bias value, and subtract a correction factor from the first shifted bias value to form a first corrected bias value, and subtract the first corrected bias value from the first logarithmic sum to form a first result; and subtract the first corrected bias value from the first logarithmic sum to form a first result; and the integrated circuit being further configured to perform an antilogarithm on the first result to generate a multiplication result of the multiplication of the first floating-point binary value and the second floating-point binary value. the integrated circuit being further configured to perform an antilogarithm on the first result to generate a multiplication result of the multiplication of the first floating- point binary value and the second floating-point binary value; Mapping for the other claims is not being shown for purpose of brevity. This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented. Claims 3 and 12 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 1 0 of copending Application No. 19091302 in view of Johnson (US 2020/0125991 A1). Regarding claim s 3 and 12 , claim s 1 and 12 of 19091302 teaches all the limitations of claim s 1 and 10 respectively as stated above. 19091302 does not explicitly teach the multiplication result being in the FPLNS format . However, on the same field of endeavor, Johnson discloses a multiplication result being in an FPLNS format (Johnson Fig. 1 and paragraph [0020] “the log-multiply computing module 106 receives the log-domain numbers 130 (e.g., data representing the log-domain numbers 130). The log-multiply computing module 106 is configured to determine a product (in the linear domain) of the log-domain numbers 130 based on their summation (i.e., the value V of the unpacked log number, which represents the exponent of the number in the linear domain) of the first log-domain number 130a and the second log-domain number 130b. The log-multiply computing module 106 can output a third log-domain number 132 representing the product (in the linear domain) of the log-domain numbers 130”). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify claim s 1 and 12 of 19091302 such that the multiplication result in in the FPLNS format because performing operations in using operands in the FPLNS format normally generates a result in the FPLNS format (Johnson paragraphs [0020-0021]). Therefore, the combination of 19091302 as modified in view of Johnson teaches the multiplication result being in the FPLNS format. This is a provisional nonstatutory double patenting rejection. Claim s 6 and 15 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1 and 12 of copending Application No. 19091302 in view of Gustafsson et al. (NPL – “ Approximate Floating-Point Operations with Integer Units by Processing in the Logarithmic Domain ”), hereinafter Gustafsson. Gustafsson is cited in the IDS submitted on 11/07/2025. Regarding claims 6 and 15, claims 1 and 12 of 19091302 teaches all the limitations of claims 1 and 10 respectively as stated above. 19091302 does not explicitly teach wherein the correction factor is within a range of 0.04 to 0.06 . However, on the same field of endeavor, Gustafsson discloses a correction factor within a range of 0.04 to 0.06 (Gustafsson Table 2.2; the correction constant Cc value (column 2) has at least one row with a value in the range 0.04-0.06). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify claims 1 and 12 of 19091302 such that the correction factor is within a range of 0.04 to 0.06 in order to provide the optimal correction constant that will provide the optimal result (Gustafsson page 48 -49 section s 3 -3.1 ). Therefore, the combination of 19091302 as modified in view of Johnson teaches wherein the correction factor is within a range of 0.04 to 0.06. This is a provisional nonstatutory double patenting rejection. Allowable Subject Matter Claim s 1-18 would be allowable if rewritten to overcome the 35 U.S.C. 101 rejection discussed above, and if claims 2, 9, 11 and 18 are rewritten to overcome the 35 U.S.C. 112(b) rejection discussed above. The following is a statement of reasons for the indication of allowable subject matter: Gustafsson et al. (NPL – “ Approximate Floating-Point Operations with Integer Units by Processing in the Logarithmic Domain ”) is the closet prior art found. Gustafsson discloses performing a multiplication operation between a first binary floating-point value and a second binary floating-point value in the logarithmic domain by converting the first binary floating-point value to a first binary logarithmic value and the second binary floating-point value to a second binary logarithmic value as shown in Equations (2-4); adding the first binary logarithmic value and the second binary logarithmic value to generate sum; adding/subtracting a correction factor Cc to a bias constant CB to form a single constant C as shown in Equation (1); adding/subtracting the single constant C to the sum as shown in Equations (19-20) . Muller et al. (US 20220137962 A1) discloses a processor comprising a register file comprising a plurality of registers; and an execution unit configured to execute a logarithmic multiplication instruction defined by a corresponding opcode, a first source operand field taking a first source operand specifying one of the registers as a first source register holding a first number x, a second source operand field taking a second source operand specifying one of the registers as a second source register holding a second number y, and a destination field taking a destination operand specifying one of the registers as a destination register. The execution unit is further configured to retrieve the first number x from the first source register, retrieve the second number y from the second source register, and retrieve a bias constant B from a bias register. The execution unit is configured to add the first and second numbers together and subtract the bias number to determine the resulting number smult (i.e. smult=x+y-B). Further, Muller discloses, the sum may be performed in any order, e.g. Smuz,=y-B+x. The execution unit is further configured to store the resulting number in the destination register. Johnson (US 20200125991 A1) discloses a computing system comprising a computer circuit configured to receive a first log-domain number and a second log-domain number and compute a product of a first floating-point (linear domain) number and a second floating-point number based on the summation of the first log-domain number and the second log-domain number and output a third log-domain number representing the product (in the linear domain) of the log-domain numbers. Further, the third log-domain number is converted to the linear domain to approximate the product of the first floating-point number and the second floating-point number. However, none of the prior art references cited explicitly teach or suggest the concept of shifting the a bias constant by a number of bits of the mantissa of the first or second floating-point binary value to form a first shifted bias value. Therefore, none of the prior art references cited, taken alone or in combination, explicitly teach or suggest “ shift a bias constant by a number of bits of the mantissa of the first floating-point binary value to form a first shifted bias value , subtract a correction factor from the first shifted bias value to form a first corrected bias value, and subtract the first corrected bias value from the first logarithmic sum to form a first result” as recited in claims 1 and 10. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT Carlo Waje whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-5767 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT 9:00-6:00 M-F . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT James Trujillo can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571) 272-3677 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Carlo Waje/ Examiner, Art Unit 2151 (571)272-5767