Office Action Predictor
Last updated: April 17, 2026
Application No. 18/046,010

GAIN COMPENSATION FOR POWER AMPLIFIERS USING A TEMPERATURE SENSOR CIRCUIT

Final Rejection §103
Filed
Oct 12, 2022
Examiner
YUN, EUGENE
Art Unit
2648
Tech Center
2600 — Communications
Assignee
skyworks solutions, Inc.
OA Round
2 (Final)
85%
Grant Probability
Favorable
3-4
OA Rounds
2y 7m
To Grant
89%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allow Rate
842 granted / 986 resolved
+23.4% vs TC avg
Minimal +4% lift
Without
With
+4.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
34 currently pending
Career history
1020
Total Applications
across all art units

Statute-Specific Performance

§101
3.1%
-36.9% vs TC avg
§103
49.0%
+9.0% vs TC avg
§102
31.1%
-8.9% vs TC avg
§112
3.0%
-37.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 986 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chawla et al. (US 5,477,188) in view of Zhou et al. (US 10,611,246). Referring to Claim 18, Chawla teaches a method of operating an amplifier circuit (see ABSTRACT which states power amplifier), the method comprising: sensing, by a first transistor of a temperature sensor circuit (see first transistor 54 in fig. 3), an ambient temperature (see ambient temperature sensor 70 in fig. 4 which is the same circuit as in fig. 3), and sensing, by a second transistor of the temperature circuit (see second transistor 54 in fig. 3), a temperature at an amplifier (see col. 5, lines 49-63 which shows the transistor measuring heatsink temperature), the temperature sensor circuit being a differential circuit having a first path and a second path with the first and second transistors being arranged on the first and second paths of the differential circuit respectively (see col. 5, lines 49-63 which shows the circuit as a differential circuit). Chawla does not teach the temperature sensor circuit generating an output voltage inversely proportional to a temperature difference between the ambient temperature and the temperature at the amplifier. Zhou teaches the temperature sensor circuit generating an output voltage inversely proportional to a temperature difference between the ambient temperature and the temperature at the amplifier (see claim 13 which shows how the voltage output of a comparator is inversely proportional to the difference between the output of a temp array (ambient) and second comparator (amp)). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Zhou to the device of Chawla in order to mitigate high voltage and current requirements in the circuit. Referring to Claim 19, Zhou also teaches a first resistor and a second resistor arranged on the first and second paths of the differential circuit respectively (see resistors 406 and 410 on first and second paths in fig. 4), and a third resistor arranged to couple the first and second paths of the differential circuit in parallel (see resistor Rp in fig. 4 which couples the first and second paths). Referring to Claim 20, Chawla also teaches a bias network coupled to the temperature sensor circuit and being configured to bias the amplifier with a reference current modulated at least in part by the output voltage (see fig. 3 which shows a bias network as described in col. 8, lines 45-55 and col. 4, line 67 to col. 5, line 8 which shows the drain current as the reference current). Allowable Subject Matter Claim 21 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding Claim 21, Chawla, Zhou, and Yamashita do not teach a third transistor coupled to the temperature sensor circuit and being configured to receive the output voltage, wherein the bias network comprises a fourth transistor coupled to the third transistor. Claims 1-15, 17, and 23-24 are allowed. Regarding Claim 1, Chawla, Zhou, and Yamashita do not teach a temperature sensor circuit including a first transistor thermally isolated from the amplifier and being configured to sense an ambient temperature, and a second transistor thermally linked to the amplifier and being configured to sense a temperature at the amplifier, the temperature sensor circuit being a differential circuit having a first path and a second path with the first and second transistors being arranged on the first and second paths of the differential circuit respectively, the temperature sensor circuit being configured to generate an output voltage inversely proportional to a temperature difference between the ambient temperature and the temperature at the amplifier. Claims 17 and 23 are allowable for similar reasons as set forth in claim 1. Response to Arguments Applicant's arguments filed 12/9/2025 have been fully considered but they are not persuasive. The applicant argued that the cited art does not teach “a first transistor thermally isolated from the amplifier and being configured to sense an ambient temperature”. However, claim 18 does not teach the first transistor thermally isolated from the amplifier. Therefore, the cited art still teaches claims 18-20. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE YUN whose telephone number is (571)272-7860. The examiner can normally be reached 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wesley Kim can be reached at 5712727867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /EUGENE YUN/ Primary Examiner, Art Unit 2648
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Prosecution Timeline

Oct 12, 2022
Application Filed
Sep 10, 2025
Non-Final Rejection — §103
Dec 09, 2025
Response Filed
Feb 09, 2026
Final Rejection — §103
Apr 01, 2026
Examiner Interview Summary
Apr 01, 2026
Applicant Interview (Telephonic)
Apr 01, 2026
Response after Non-Final Action

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
85%
Grant Probability
89%
With Interview (+4.0%)
2y 7m
Median Time to Grant
Moderate
PTA Risk
Based on 986 resolved cases by this examiner. Grant probability derived from career allow rate.

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