DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
Response filed on 2 September 2025 has been entered. Applicant has canceled claims 10 and 15, amended claims 1, 9, 11, and 13 and added claims 17-20. Claims 1-9, 11-14, and 16-20 are pending.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-3, 5-7, 10, and 11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-7, 11-12, 16, and 18-20 rejected under 35 U.S.C. 103 as being unpatentable over Pearson et al. US PGPUB 20170301817 (hereinafter Pearson) in view of King et al US PGPUB 20050205954 (hereinafter King) and Hong et al. US PGPUB 20190386051 (hereinafter Hong).
Regarding claim 1, Pearson discloses (figs. 5-6J, 10, 13) a heteroepitaxial semiconductor device, comprising:
a seed layer (patterned a-Si strips 615, ¶83) comprising a first semiconductor material (a-Si), the seed layer comprising a first side, an opposing a second side arranged opposite to the first side, and lateral sides connecting the first side and the second side (figs. 6A-6B),
a separation layer (upper part of overlayer layer 620, ¶86-88) arranged at the first side of the seed layer, the separation layer comprising an aperture (625, fig. 6D ¶87),
a heteroepitaxial structure (Ge 630, 632, 634, ¶91-92) grown at the first side of the seed layer at least in the aperture, wherein the heteroepitaxial structure comprises a second semiconductor material (Ge) that is different from the first semiconductor material (a-Si), and
a first dielectric material layer (612 and lower portion of overlayer layer 620, ¶87-88, 90-91) arranged at the second side of the seed layer and covering the lateral sides of the seed layer,
Pearson does not disclose a second dielectric material layer arranged at the separation layer and at least partially encapsulating the heteroepitaxial structure;
a third dielectric material layer arranged on the first dielectric material layer opposite to the seed layer;
a fourth dielectric material layer arranged over the second dielectric material layer and the heteroepitaxial structure;
a microlens arranged on the fourth dielectric material layer and over the heteroepitaxial structure;
and a second substrate, comprising a third semiconductor material, arranged on the third dielectric material layer opposite to the first dielectric material layer one or more through silicon vias (TSVs) arranged lateral to both the heteroepitaxial structure and the seed layer, the one or more TSVs being formed through one or more dielectric material layers for providing an electrical connection with the second substrate and at least one contact arranged laterally adjacent to the microlens, the at least one contact being coupled to the one or more TSVs for electrical contact,
wherein the one or more TSVs extend from the at least one contact to the second substrate.
In the same field of endeavor, King discloses (fig. 2B) a second dielectric material (216) layer arranged at the separation layer (214 and 220) and at least partially encapsulating the heteroepitaxial structure (King fig. 2B ¶37-41);
a third dielectric material layer (202) arranged on the first dielectric material layer (212) opposite to the seed layer (King fig. 2B ¶28, where the third dielectric is underneath the first dielectric opposite the seed layer at the base of the seed channel 217);
a fourth dielectric material layer (228 King fig. 2A ¶38, 41) arranged over the second dielectric material layer and the heteroepitaxial structure;
a microlens (244 King ¶42) arranged on the fourth dielectric material layer and over the heteroepitaxial structure;
and a second substrate (200), comprising a third semiconductor material (King ¶28 where the silicon substrate would be different than the partially oxidized silicon layer 222 and corresponding to the substrate of Pearson), arranged on the third dielectric material layer opposite to the first dielectric material layer one or more through silicon vias (TSVs) (King ¶41, where vias 230 go through silicon containing layers) arranged lateral to both the heteroepitaxial structure and the seed layer.
It would have been obvious to one of ordinary skill in the art at the time of filing for the transistor structure to be vertically connected and including a microlens as disclosed by King, improving device performance with dielectric isolation for the heterostructure and improving control of light via lensing.
Pearson in view of King does not disclose the one or more TSVs being formed through one or more dielectric material layers for providing an electrical connection with the second substrate and at least one contact arranged laterally adjacent to the microlens, the at least one contact being coupled to the one or more TSVs for electrical contact, wherein the one or more TSVs extend from the at least one contact to the second substrate.
In the same field of endeavor, Hong discloses (fig. 6) the one or more TSVs being formed through one or more dielectric material layers for providing an electrical connection with the second substrate and at least one contact arranged laterally adjacent to the microlens, the at least one contact being coupled to the one or more TSVs for electrical contact, wherein the one or more TSVs extend from the at least one contact to the second substrate (Hong fig. 6 ¶57-58, where TSV1extends laterally to the microlens MR and TSV2 extends through the semiconductor substrate 1a). It would have been obvious to one of ordinary skill in the art at the time of filing for the vias to extend vertically through the device to the substrate and lens layers, improving miniaturization and compactness of the image sensor while electrically connecting transistor devices within the structure.
Regarding claim 2, Pearson in view of King and Hong discloses the heteroepitaxial semiconductor device of claim 1,
wherein the heteroepitaxial structure (Ge 630, 632, 634, ¶91-92) comprises a trunk portion (lower portion of 632 ¶92) arranged within the aperture (625 ¶87) and a top portion (upper portion of 632, fig. 6I) arranged on top of the trunk portion (lower portion of 632) and the separation layer (upper part of overlayer layer 620, ¶86-88), wherein a lateral extension of the trunk portion (lower portion of 632) is smaller than a lateral extension of the top portion (upper portion of 632),
the lateral extension of the trunk portion and the lateral extension of the top portion being measured parallel to the first side of the seed layer.
Regarding claim 3, Pearson in view of King and Hong discloses the heteroepitaxial semiconductor device of claim 2,
wherein the top portion (upper portion of 632) has an essentially pyramidal shape (the upper portion of 632 is described as faceted ¶92 and fig. 6I shows the cross-sectional shape as a flat pyramid).
Regarding claim 4, Pearson in view of King and Hong discloses the heteroepitaxial semiconductor device of claim 2.
Pearson does not explicitly disclose wherein the trunk portion (lower portion of 632 ¶92) has an aspect ratio in a range of 100:1 to 1:100. Pearson does disclose (fig. 5) a function of grain nucleation in the channels based on ratio of width and depth of these channels within this range to provide between NG 1 and 2 Ge grains (¶69).
It would have been obvious to one of ordinary skill in the art at the time of filing to use the same calculation (with the vertical as the new growth direction) to determine the aperture size, and therefore the trunk ratio, improving device performance and compatibility by controlling Ge grain orientation while also providing cross-sectional areas typical for Ge active regions (¶71).
Regarding claim 5, Pearson in view of King and Hong discloses the heteroepitaxial semiconductor device of claim 1,
wherein the seed layer has lateral dimensions measured parallel to the first side of the seed layer of 10 µm or less (fig. 5, where channel depth is less than 1 µm).
Regarding claim 6, Pearson in view of King and Hong discloses the heteroepitaxial semiconductor device of claim 1,
wherein the first semiconductor material is silicon and the second semiconductor material is germanium (¶83, 91-92).
Regarding claim 7, Pearson in view of King and Hong discloses the heteroepitaxial semiconductor device of claim 1,
wherein the separation layer (upper portion of 620, ¶86-88) comprises a buried dielectric material layer (where 620 is a dielectric material, and 620 extending beyond the seed region buries the lower portions of 620 as well as the dielectric layer 612).
Regarding claim 11, Pearson discloses an image sensor, comprising:
a heteroepitaxial semiconductor device, comprising:
a seed layer (patterned a-Si strips 615, ¶83) comprising a first semiconductor material (a-Si), the seed layer comprising a first side, a second side arranged opposite to the first side, and lateral sides connecting the first side and the second side;
a separation layer (upper part of overlayer layer 620, ¶86-88) arranged at the first side of the seed layer, the separation layer comprising an aperture (625, fig. 6D ¶87);
a heteroepitaxial structure (Ge 630, 632, 634, ¶91-92) grown at the first side of the seed layer at least in the aperture, wherein the heteroepitaxial structure comprises a second semiconductor material (Ge) that is different from the first semiconductor material (Si), and
a first dielectric material layer (612 and lower portion of overlayer layer 620, ¶87-88, 90-91) arranged at the second side of the seed layer and covering the lateral sides of the seed layer, wherein the heteroepitaxial structure forms a photosensitive part of a pixel of the image sensor (¶37).
Pearson does not disclose a second dielectric material layer arranged at the separation layer and at least partially encapsulating the heteroepitaxial structure;
a third dielectric material layer arranged on the first dielectric material layer opposite to the seed layer;
a fourth dielectric material layer arranged over the second dielectric material layer and the heteroepitaxial structure;
a microlens arranged on the fourth dielectric material layer and over the heteroepitaxial structure;
and a second substrate, comprising a third semiconductor material, arranged on the third dielectric material layer opposite to the first dielectric material layer one or more through silicon vias (TSVs) arranged lateral to both the heteroepitaxial structure and the seed layer, the one or more TSVs being formed through one or more dielectric material layers for providing an electrical connection with the second substrate and at least one contact arranged laterally adjacent to the microlens, the at least one contact being coupled to the one or more TSVs for electrical contact, wherein the one or more TSVs extend from the at least one contact to the second substrate.
In the same field of endeavor, King discloses (fig. 2B) a second dielectric material (216) layer arranged at the separation layer (214 and 220) and at least partially encapsulating the heteroepitaxial structure (King fig. 2B ¶37-41);
a third dielectric material layer (202) arranged on the first dielectric material layer (212) opposite to the seed layer (King fig. 2B ¶28, where the third dielectric is underneath the first dielectric opposite the seed layer at the base of the seed channel 217);
a fourth dielectric material layer (228 King fig. 2A ¶38, 41) arranged over the second dielectric material layer and the heteroepitaxial structure;
a microlens (244 King ¶42) arranged on the fourth dielectric material layer and over the heteroepitaxial structure;
and a second substrate (200), comprising a third semiconductor material (King ¶28 where the silicon substrate would be different than the partially oxidized silicon layer 222 and corresponding to the substrate of Pearson), arranged on the third dielectric material layer opposite to the first dielectric material layer one or more through silicon vias (TSVs) (King ¶41, where vias 230 go through silicon containing layers) arranged lateral to both the heteroepitaxial structure and the seed layer.
It would have been obvious to one of ordinary skill in the art at the time of filing for the transistor structure to be vertically connected and including a microlens as disclosed by King, improving device performance with dielectric isolation for the heterostructure and improving control of light via lensing.
Pearson in view of King does not disclose the one or more TSVs being formed through one or more dielectric material layers for providing an electrical connection with the second substrate and at least one contact arranged laterally adjacent to the microlens, the at least one contact being coupled to the one or more TSVs for electrical contact, wherein the one or more TSVs extend from the at least one contact to the second substrate.
In the same field of endeavor, Hong discloses (fig. 6) the one or more TSVs being formed through one or more dielectric material layers for providing an electrical connection with the second substrate and at least one contact arranged laterally adjacent to the microlens, the at least one contact being coupled to the one or more TSVs for electrical contact, wherein the one or more TSVs extend from the at least one contact to the second substrate (Hong fig. 6 ¶57-58, where TSV1extends laterally to the microlens MR and TSV2 extends through the semiconductor substrate 1a). It would have been obvious to one of ordinary skill in the art at the time of filing for the vias to extend vertically through the device to the substrate and lens layers, improving miniaturization and compactness of the image sensor while electrically connecting transistor devices within the structure.
Regarding claim 12, Pearson in view of King and Hong discloses the image sensor of claim 11.
King discloses (fig. 7) “a pixel array imager which is optimized for time-of-flight imaging” (King ¶51). It would have been obvious to one of ordinary skill in the art at the time of filing to include time-of-flight capabilities disclosed by King, improving accuracy as well as low-light image sensor performance.
Regarding claim 16, Pearson in view of King and Hong discloses the heteroepitaxial semiconductor device of claim 2.
Pearson does not explicitly disclose wherein the trunk portion (lower portion of 632 ¶92) has an aspect ratio in a range of 1:1 to 1:10. Pearson does disclose (fig. 5) a function of grain nucleation in the channels based on ratio of width and depth of these channels within this range to provide between NG 1 and 2 Ge grains (¶69).
It would have been obvious to one of ordinary skill in the art at the time of filing to use the same calculation (with the vertical as the new growth direction) to determine the aperture size, and therefore the trunk ratio, improving device performance and compatibility by controlling Ge grain orientation while also providing cross-sectional areas typical for Ge active regions (¶71).
Regarding claim 18, Pearson discloses a heteroepitaxial semiconductor device, comprising:
a seed layer (patterned a-Si strips 615, ¶83) comprising a first semiconductor material (a-Si), the seed layer comprising a first side, a second side arranged opposite to the first side, and lateral sides connecting the first side and the second side;
a separation layer (upper part of overlayer layer 620, ¶86-88) arranged at the first side of the seed layer, the separation layer comprising an aperture (625, fig. 6D ¶87);
a heteroepitaxial structure (Ge 630, 632, 634, ¶91-92) grown at the first side of the seed layer at least in the aperture, wherein the heteroepitaxial structure comprises a second semiconductor material (Ge) that is different from the first semiconductor material (Si);
a first dielectric material layer (612 and lower portion of overlayer layer 620, ¶87-88, 90-91) arranged at the second side of the seed layer and covering the lateral sides of the seed layer;
Pearson does not disclose a second dielectric material layer arranged at the separation layer and at least partially encapsulating the heteroepitaxial structure;
a fourth dielectric material layer arranged over the second dielectric material layer and the heteroepitaxial structure;
a microlens arranged on the fourth dielectric material layer and over the heteroepitaxial structure;
a second substrate, comprising a third semiconductor material, arranged on the second side of the first dielectric material layer, and
one or more through silicon vias (TSVs) arranged lateral to both the heteroepitaxial structure and the seed layer, the one or more TSVs being formed through one or more dielectric material layers for providing an electrical connection with the second substrate; and
at least one contact arranged laterally adjacent to the microlens, the at least one contact being coupled to the one or more TSVs for electrical contact,
wherein the one or more TSVs extend from the at least one contact to the second substrate.
In the same field of endeavor, King discloses (fig. 2B) a second dielectric material (216) layer arranged at the separation layer (214 and 220) and at least partially encapsulating the heteroepitaxial structure (King fig. 2B ¶37-41);
a fourth dielectric material layer (228 King fig. 2A ¶38, 41) arranged over the second dielectric material layer and the heteroepitaxial structure;
a microlens (244 King ¶42) arranged on the fourth dielectric material layer and over the heteroepitaxial structure;
a second substrate (200), comprising a third semiconductor material (King ¶28 where the silicon substrate would be different than the partially oxidized silicon layer 222 and corresponding to the substrate of Pearson), arranged on the second side of the first dielectric material layer, and
one or more through silicon vias (TSVs) (King ¶41, where vias 230 go through silicon containing layers) arranged lateral to both the heteroepitaxial structure and the seed layer.
It would have been obvious to one of ordinary skill in the art at the time of filing for the transistor structure to be vertically connected and including a microlens as disclosed by King, improving device performance with dielectric isolation for the heterostructure and improving control of light via lensing.
Pearson in view of King does not disclose the one or more TSVs being formed through one or more dielectric material layers for providing an electrical connection with the second substrate and at least one contact arranged laterally adjacent to the microlens, the at least one contact being coupled to the one or more TSVs for electrical contact, wherein the one or more TSVs extend from the at least one contact to the second substrate.
In the same field of endeavor, Hong discloses (fig. 6) the one or more TSVs being formed through one or more dielectric material layers for providing an electrical connection with the second substrate and at least one contact arranged laterally adjacent to the microlens, the at least one contact being coupled to the one or more TSVs for electrical contact, wherein the one or more TSVs extend from the at least one contact to the second substrate (Hong fig. 6 ¶57-58, where TSV1extends laterally to the microlens MR and TSV2 extends through the semiconductor substrate 1a). It would have been obvious to one of ordinary skill in the art at the time of filing for the vias to extend vertically through the device to the substrate and lens layers, improving miniaturization and compactness of the image sensor while electrically connecting transistor devices within the structure.
Regarding claim 19, Pearson in view of King and Hong discloses the heteroepitaxial semiconductor device of claim 18, further comprising:
one or more transistor structures or one or more diode structures arranged at the second side of the seed layer, wherein the one or more transistor structures or the one or more diode structures are arranged within the first dielectric material layer (Hong fig. 2A ¶27, where first transistors 5 are deposited on the substrate and located within the first dielectric 10 located on the second side of the seed layer of Pearson as modified by King and Hong); and
one or more metallic contacts extending at least partially through the first dielectric material layer to the one or more transistor structures or the one or more diode structures (Hong ¶58 “A plurality of transistors (not shown) may be disposed on the second semiconductor substrate 1a. The transistors may be electrically connected to a plurality of second interconnection lines 222 that are disposed in the second dielectric layer 220 and electrically connected to each other”).
Regarding claim 20, Pearson in view of King and Hong discloses the heteroepitaxial semiconductor device of claim 19, further comprising:
one or more further metallic contacts arranged within the second substrate and electrically connected to the one or more metallic contacts (Hong ¶58 “A plurality of transistors (not shown) may be disposed on the second semiconductor substrate 1a. The transistors may be electrically connected to a plurality of second interconnection lines 222 that are disposed in the second dielectric layer 220 and electrically connected to each other”).
Claims 8-9 and 13-14 and 17 rejected under 35 U.S.C. 103 as being unpatentable over Pearson in view of King, Hong, and Chen et al. US PGPUB 20160197115 (hereinafter Chen).
Regarding claim 8, Pearson in view of King and Hong discloses the heteroepitaxial semiconductor device of claim 1.
Pearson does not disclose further comprising: one or more transistor structures or one or more diode structures arranged at the second side of the seed layer,
wherein the one or more transistor structures or the one or more diode structures are arranged within the first dielectric material layer.
In the same field of endeavor, Chen discloses (fig. 3) an image sensor where “Various electrical components have been formed in back end of line (BEOL) layers 15 over the wafer 13, as is generally known in the art. For example, polysilicon gate material 17 may be formed over the photodiodes 23 and other devices, such as transistors, capacitors, diodes and the like may be formed in the wafer 13 or in the BEOL layer 15,” (Chen ¶24).
It would have been obvious to one of ordinary skill in the art at the time of filing to include transistors or diodes as disclosed by Chen, improving device performance by increasing charge storage and low-light performance.
Regarding claim 9, Pearson in view of King, Hong, and Chen discloses the heteroepitaxial semiconductor device of claim 8.
Pearson and Chen do not explicitly disclose further comprising: one or more metallic contacts extending at least partially from the third dielectric material layer through the first dielectric material layer to the one or more transistor structures or the one or more diode structures.
In the same field of endeavor, King discloses (fig. 2B) further comprising: one or more metallic contacts (230 King ¶41) extending at least partially from the third dielectric material layer through the first dielectric material layer (212 King ¶28, 37) to the one or more transistor structures or the one or more diode structures (transistor made up of 204, 206, 208, and 210, King ¶28). It would have been obvious to one of ordinary skill in the art at the time of filing for the transistor structure to be vertically connected, improving pixel density.
Regarding claim 13, Pearson discloses (figs. 6A-6J) a method for fabricating a heteroepitaxial semiconductor device, the method comprising: providing a structure that comprises:
a substrate (614 ¶81), a separation layer (upper part of overlayer layer 620, ¶86-88) on the substrate, and
a seed layer (patterned a-Si strips 615, ¶83) on the separation layer, the seed layer comprising a first semiconductor material (a-Si), and the seed layer comprising a first side, a second side arranged opposite to the first side, and lateral sides connecting the first side and the second side, wherein the first side of the seed layer faces the separation layer;
fabricating a first dielectric material layer (612 and lower portion of overlayer layer 620, ¶87-88, 90-91) at the second side of the seed layer and thereby covering the lateral sides of the seed layer with the first dielectric material layer (612 and lower portion of overlayer layer 620, ¶87-88, 90-91),
generating an aperture in the separation layer; growing a heteroepitaxial structure on the first side of the seed layer in the aperture (625, fig. 6D ¶87),
wherein the heteroepitaxial structure (Ge 630, 632, 634, ¶91-92) comprises a second semiconductor material (Ge), different from the first semiconductor material (a-Si).
Pearson does not disclose removing the substrate. In the same field of endeavor, Chen discloses removal of the substrate (41 Chen¶34). It would have been obvious to one of ordinary skill in the art at the time of filing to remove the substrate as disclosed by Chen, improving device capabilities by allowing subsequent back side processing of the device.
Pearson in view of Chen does not disclose fabricating a second dielectric material layer on the separation layer and at least partially encapsulating the heteroepitaxial structure with the second dielectric material layer;
fabricating a third dielectric material layer on the first dielectric material layer opposite to the seed layer;
fabricating a fourth dielectric material layer over the second dielectric material layer and the heteroepitaxial structure;
providing a microlens on the fourth dielectric material layer and over the heteroepitaxial structure;
providing a second substrate, comprising a third semiconductor material, arranged on the third dielectric material layer opposite to the first dielectric material layer;
forming one or more through silicon vias (TSVs) arranged lateral to both the heteroepitaxial structure and the seed layer, the one or more TSVs being formed through one or
more dielectric material layers for providing an electrical connection with the second substrate;
and forming at least one contact arranged laterally adjacent to the microlens, the at least one contact being coupled to the one or more TSVs for electrical contact, wherein the one or more TSVs extend from the at least one contact to the second substrate.
In the same field of endeavor, King discloses (fig. 2B)
fabricating a second dielectric material (216) layer arranged at the separation layer (214 and 220) and at least partially encapsulating the heteroepitaxial structure (King fig. 2B ¶37-41);
fabricating a third dielectric material layer (202) arranged on the first dielectric material layer (212) opposite to the seed layer (King fig. 2B ¶28, where the third dielectric is underneath the first dielectric opposite the seed layer at the base of the seed channel 217);
fabricating a fourth dielectric material layer (228 King fig. 2A ¶38, 41) arranged over the second dielectric material layer and the heteroepitaxial structure;
providing a microlens (244 King ¶42) arranged on the fourth dielectric material layer and over the heteroepitaxial structure;
providing a second substrate (200), comprising a third semiconductor material (King ¶28 where the silicon substrate would be different than the partially oxidized silicon layer 222 and corresponding to the substrate of Pearson), arranged on the third dielectric material layer opposite to the first dielectric material layer;
forming one or more through silicon vias (TSVs) (King ¶41, where vias 230 go through silicon containing layers) arranged lateral to both the heteroepitaxial structure and the seed layer.
It would have been obvious to one of ordinary skill in the art at the time of filing for the transistor structure to be vertically connected and including a microlens as disclosed by King, improving device performance with dielectric isolation for the heterostructure and improving control of light via lensing.
Pearson in view of King does not disclose the one or more TSVs being formed through one or more dielectric material layers for providing an electrical connection with the second substrate and forming at least one contact arranged laterally adjacent to the microlens, the at least one contact being coupled to the one or more TSVs for electrical contact, wherein the one or more TSVs extend from the at least one contact to the second substrate.
In the same field of endeavor, Hong discloses (fig. 6) the one or more TSVs being formed through one or more dielectric material layers for providing an electrical connection with the second substrate and at least one contact arranged laterally adjacent to the microlens, the at least one contact being coupled to the one or more TSVs for electrical contact, wherein the one or more TSVs extend from the at least one contact to the second substrate (Hong fig. 6 ¶57-58, where TSV1extends laterally to the microlens MR and TSV2 extends through the semiconductor substrate 1a). It would have been obvious to one of ordinary skill in the art at the time of filing for the vias to extend vertically through the device to the substrate and lens layers, improving miniaturization and compactness of the image sensor while electrically connecting transistor devices within the structure.
Regarding claim 14, Pearson in view of King, Hong and Chen discloses the method of claim 13.
Chen discloses further comprising: fabricating one or more transistor structures or one or more diode structures at the second side of the seed layer; and encapsulating the one or more transistor structures or the one or more diode structures with the first dielectric material layer (“Various electrical components have been formed in back end of line (BEOL) layers 15 over the wafer 13, as is generally known in the art. For example, polysilicon gate material 17 may be formed over the photodiodes 23 and other devices, such as transistors, capacitors, diodes and the like may be formed in the wafer 13 or in the BEOL layer 15,” Chen ¶24).
It would have been obvious to one of ordinary skill in the art at the time of filing to include transistors or diodes as disclosed by Chen, improving device performance by increasing charge storage and low-light performance.
Regarding claim 17, Pearson in view of King, Hong, and Chen discloses the heteroepitaxial semiconductor device of claim 9, further comprising:
one or more further metallic contacts arranged within the second substrate and electrically connected to the one or more metallic contacts (Hong ¶58 “A plurality of transistors (not shown) may be disposed on the second semiconductor substrate 1a. The transistors may be electrically connected to a plurality of second interconnection lines 222 that are disposed in the second dielectric layer 220 and electrically connected to each other”).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Seth D Lawson/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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