Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/25/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-6, 9-10, and 21-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vantrease (US20190294413A1) in view of Mills (US20210158135A1).
Regarding claim 1, Vantrease teaches a processing element for deep learning, the processing element implemented on one or more circuits, the processing element comprising:
a plurality of first subtractors, the plurality of first subtractors to generate intermediate activations by subtracting a first constant from quantized activations of a convolution (Figure 9: 930a-d, where each “SUB” contains a subtractor for 932/938 to handle activations, “For example, the inputs to the subtraction engine may include an 8-bit weight W.sub.q 934, an 8-bit input data element X.sub.q 932 (e.g., a pixel of an image or a feature map), an 8-bit zero-point integer W.sub.qz 936 for the weights, and an 8-bit zero-point integer X.sub.qz 938 for the input data elements.”),
a plurality of second subtractors the plurality of second subtractors to generate intermediate weights by subtracting a second constant from quantized weights of the convolution (Figure 9: 930a-d, where each “SUB” contains a subtractor for 934/936 to hand weights, “For example, the inputs to the subtraction engine may include an 8-bit weight W.sub.q 934, an 8-bit input data element X.sub.q 932 (e.g., a pixel of an image or a feature map), an 8-bit zero-point integer W.sub.qz 936 for the weights, and an 8-bit zero-point integer X.sub.qz 938 for the input data elements.”),
an input storage unit, the input storage unit to store the intermediate activations generated by the plurality of first subtractors (“Each PE may also include sequential logic circuitries (e.g., registers, latches, state machines, etc.) to store input data, weights, and output data for the adder and multiplier circuitry, and to synchronize the flow of the data into and out of the circuitry.”),
a weight storage unit, the weight storage unit to store the intermediate weights generated by the plurality of second subtractors (“Each PE may also include sequential logic circuitries (e.g., registers, latches, state machines, etc.) to store input data, weights, and output data for the adder and multiplier circuitry, and to synchronize the flow of the data into and out of the circuitry.”), and
a plurality of multipliers, the plurality of multipliers to perform multiplication operations on the intermediate activations and the intermediate weights, each multiplier corresponding to a different pair of subtractors, the different pair of subtractors comprising a different one of the plurality of first subtractors and a different one of the plurality of second subtractors (Figure 9: 922 of each PE, “For example, a PE may receive an input data element and a weight (e.g., from row input bus 922) and generate, using multiplier 923, a multiplication product to represent a weighted input data element.”, also see ¶108. Each “SUB”, as noted above, contains one of the first and second subtractors. Per Figure 9, each of 930-d is input into a different PE, which contain the multipliers. Therefore, for each of 920a-d, one of the plurality of multiplies is receiving input from a different one of the first and second subtractors, e.g. 930a to 920a vs. 930b to 920b)
wherein a multiplication operation by each multiplier includes a multiplication of an intermediate activation computed by the different one of the plurality of first subtractors and an intermediate weight computed by the different one of the plurality of second subtractors (Figure 9: 922, “For example, a PE may receive an input data element and a weight (e.g., from row input bus 922) and generate, using multiplier 923, a multiplication product to represent a weighted input data element.”, also see ¶108).
Vantrease does not teach the plurality of processing elements.
Mills teaches wherein the processing element (Figure 3: 314A-N) is one of a plurality of processing elements (Figure 3: 314A-N, see Figure 4 where 314 can be analogous to the processing element of Vantrease) which allows for parallel computation and load scaling (¶47, “Each of neural engines 314 performs computing operations for machine learning in parallel. Depending on the load of operation, the entire set of neural engines 314 may be operating or only a subset of the neural engines 314 may be operating while the remaining neural engines 314 are placed in a power-saving mode to conserve power. Each of neural engines 314 includes components for storing one or more kernels, for performing multiply-accumulate operations, and for post-processing to generate an output data 328, as described below in detail with reference to FIG. 4. Neural engines 314 may specialize in performing computation heavy operations such as convolution operations and tensor product operations. Convolution operations may include different kinds of convolutions, such as cross-channel convolutions (a convolution that accumulates values from different channels), channel-wise convolutions, and transposed convolutions.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize a plurality of the processing elements of Vantrease, thereby providing the claimed plurality of processing elements implemented in one or more circuits, in order to allow for parallel computation and load scaling.
Regarding claim 2, Vantrease as modified teaches all of the limitations of claim 1, further comprising:
an adder assembly, the adder assembly to generate an intermediate output of the processing element by accumulating products generated by the plurality of multipliers (“As described above, if X.sub.q and W.sub.q are 8-bit unsigned integers, X.sub.adj and Y.sub.adj may be 9-bit signed integers. Thus, the multiplication may be performed on 9-bit signed integers, and the product of each multiplication may be represented by, for example, an 18-bit integer. The sum Z of the products may be represented by, for example, a 32-bit integer.”); an additional multiplier, the additional multiplier to generate an output of the processing element by multiplying the intermediate output of the processing element with a constant, wherein the intermediate output is an integer, and the output is a floating-point number (“In the third step, the sum Z of the products from the second step may be scaled by a floating point scaling factor S.sub.XS.sub.W to convert the integer sum of products into a floating point number:”).
Regarding claim 3, Vantrease as modified teaches all of the limitations of claim 2, further comprising:
an additional multiplier, the additional multiplier to generate a partial sum by multiplying the intermediate partial sum with a constant, wherein the intermediate partial sum is an integer, and the partial sum is a floating- point number (“In the third step, the sum Z of the products from the second step may be scaled by a floating point scaling factor S.sub.XS.sub.W to convert the integer sum of products into a floating point number:”).
Regarding claim 4, Vantrease as modified teaches all of the limitations of claim 2, further comprising:
an accumulator, the accumulator to generate an intermediate partial sum by accumulating the intermediate output and the additional intermediate output (¶110).
Regarding claim 5, Vantrease as modified teaches all of the limitations of claim 4, further comprising:
an output storage unit configured to store the intermediate partial sum (¶110).
Regarding claim 6, Vantrease as modified teaches all of the limitations of claim 4, further comprising:
an additional multiplier, the additional multiplier to generate a partial sum by multiplying the intermediate partial sum with a constant, wherein the intermediate partial sum is an integer, and the partial sum is a floating- point number (“In the third step, the sum Z of the products from the second step may be scaled by a floating point scaling factor S.sub.XS.sub.W to convert the integer sum of products into a floating point number:”).
Regarding claim 9, Vantrease as modified teaches all of the limitations of claim 1, wherein
the input storage unit comprises a plurality of register files, each register file to store one or more intermediate activations to be used by a different multiplier of the plurality of multipliers (“Each PE may also include sequential logic circuitries (e.g., registers, latches, state machines, etc.) to store input data, weights, and output data for the adder and multiplier circuitry, and to synchronize the flow of the data into and out of the circuitry.”)
Regarding claim 10, Vantrease as modified teaches all of the limitations of claim 1, wherein
the weight storage unit comprises a plurality of register files, each register file to store one or more intermediate activations to be used by a different multiplier of the plurality of multipliers (“Each PE may also include sequential logic circuitries (e.g., registers, latches, state machines, etc.) to store input data, weights, and output data for the adder and multiplier circuitry, and to synchronize the flow of the data into and out of the circuitry.”)
Regarding claim 21, Vantrease as modified according to claim 1 performs the method of claim 21 under normal operation.
Regarding claim 22, Vantrease as modified according to claim 2 performs the method of claim 22 under normal operation.
Regarding claim 23, Vantrease as modified according to claim 3 performs the method of claim 23 under normal operation.
Regarding claim 24, Vantrease as modified according to claims 3-4 performs the method of claim 24 under normal operation.
Claim(s) 7 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vantrease (US20190294413A1) in view of Mills (US20210158135A1), further in view of Song (US20210208885A1).
Regarding claim 7, Vantrease as modified teaches all of the limitations of claim 2, but does not teach wherein: the adder assembly comprises a first adder and a second adder, the first adder to generate a first sum by accumulating products generated by two multipliers of the plurality of multipliers, the second adder to generate a second sum by accumulating products generated by two other multipliers of the plurality of multipliers, and the processing element further comprises a first pipeline register and a second pipeline register, the first pipeline register to store the first sum and the second pipeline register to store the second.
Song teaches a first adder and a second adder, the first adder is configured to generate a first sum by accumulating products generated by two multipliers of the plurality of multipliers, the second adder is configured to generate a second sum by accumulating products generated by two other multipliers of the plurality of multipliers, and the processing element further comprises a first pipeline register configured to store the first sum and a second pipeline register configured to store the second (¶74-75, products are generated and added in a tree. Each sum can be considered to be stored in its own register between adding because the values are carried over and therefore are at least temporarily stored).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize an adder assembly in Vantrease which comprises a first adder and a second adder, the first adder is configured to generate a first sum by accumulating products generated by two multipliers of the plurality of multipliers, the second adder is configured to generate a second sum by accumulating products generated by two other multipliers of the plurality of multipliers, and the processing element further comprises a first pipeline register configured to store the first sum and a second pipeline register configured to store the second in order to efficiently add products into partial sums.
Regarding claim 25, Vantrease as modified according to claim 7 performs the method of claim 25 under normal operation.
Allowable Subject Matter
Claims 11-17 and 19-20 are allowed.
Regarding claim 11, the prior art does not support a prima facie case of obviousness for the processing element array coupled with the buffer as claimed. While Vantrease and Mills, the closest prior art of record and cited herein, disclose similar processing elements and disclose buffers, the construction of claim 11 would not be prima facie obvious from the combination of Vantrease and Mills.
Response to Arguments
Applicant’s remarks filed 08/25/2026 have been fully considered.
Applicant’s arguments are moot in view of the new grounds of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCHYLER S SANKS whose telephone number is (571)272-6125. The examiner can normally be reached 06:30 - 15:30 Central Time, M-F.
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/SCHYLER S SANKS/Primary Examiner, Art Unit 2129
