CTFR 18/047,415 CTFR 93210 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 07-30-03-h AIA Claim Interpretation 07-30-03 AIA The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. 07-30-05 The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph: (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “a plurality of first subtractors” in claims 1 and 11– The Specification as originally filed does not describe a structure for the subtractor(s). “a plurality of second subtractors” in claims 1 and 11– The Specification as originally filed does not describe a structure for the subtractor(s). “an input storage unit” in claims 1 and 11– ¶60 of the originally filed Specification discloses that “storage units” are memory which store a byte, multiple bytes, or bits. Therefore, the limitation is interpreted as such or as any equivalent thereof. “a weight storage unit” in claims 1 and 11– ¶60 of the originally filed Specification discloses that “storage units” are memory which store a byte, multiple bytes, or bits. Therefore, the limitation is interpreted as such or as any equivalent thereof. “a plurality of multipliers” in claims 1 and 11– The Specification as originally filed does not describe a structure for the multiplier(s). “a different pair of subtractors” in claims 1 and 11– The Specification as originally filed does not describe a structure for the subtractor(s). “a different one of the plurality of first subtractors” in claims 1 and 11– The Specification as originally filed does not describe a structure for the subtractor(s). “a different one of the plurality of second subtractors” in claims 1 and 11– The Specification as originally filed does not describe a structure for the subtractor(s). “an adder assembly” in claims 2 and 13-14 – ¶80 of the originally filed specification recites that an adder assembly is a collection of adders. The adder assembly is interpreted as such or any equivalent thereof. “an additional multiplier” in claims 3 and 14– The Specification as originally filed does not describe a structure for the multiplier(s). “an accumulator” in claims 4 and 15 – The Specification as originally filed does not describe a structure for the accumulator(s). “an output storage unit” in claim 5 – ¶60 of the originally filed Specification discloses that “storage units” are memory which store a byte, multiple bytes, or bits. Therefore, the limitation is interpreted as such or as any equivalent thereof. “an additional multiplier” in claims 6 and 16– The Specification as originally filed does not describe a structure for the multiplier(s). “a first subtractor” in claims 8 and 18 – The Specification as originally filed does not describe a structure for the subtractor(s). “a second subtractor” in claims 8 and 18 – The Specification as originally filed does not describe a structure for the subtractor(s). “an additional processing element” in claim 15 – The Specification as originally filed does not describe a structure for the processing element. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. Claim Rejections - 35 USC § 112 07-30-01 AIA The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. 07-31-01 Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claims 1-6, 11, and 13-16 lack written description because the limitations interpreted under 35 USC 112(f) lack corresponding structure in the Specification as originally filed. 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 1-7, 9-17, 19-20 and 24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 1-6, 11, and 13-16 are indefinite because the limitations interpreted under 35 USC 112(f) lack corresponding structure in the Specification as originally filed. Claims 2-10 are indefinite by virtue of dependency on claim 1. Claims 12-20 are indefinite by virtue of dependency on claim 11. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 11-16, 19-20, 1-6, 9-10, and 21-24 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Vantrease (US20190294413A1) . Regarding claim 11 , Vantrease teaches a compute block for deep learning, the compute block comprising: a buffer, the buffer configured to store a portion of a quantized input tensor and a portion of a quantized filter (Figure 9, “Each row may also include a subtraction engine 930 a , 930 b , 930 c , . . . , or 930 d that takes quantized inputs (e.g., in UNIT8 format) and zero-point integers (e.g., in UNIT8 format) from a memory or a buffer. For example, the inputs to the subtraction engine may include an 8-bit weight W.sub.q 934 , an 8-bit input data element X.sub.q 932 (e.g., a pixel of an image or a feature map), an 8-bit zero-point integer W.sub.qz 936 for the weights, and an 8-bit zero-point integer X.sub.qz 938 for the input data elements.”), the quantized input tensor comprising a plurality of quantized activations of a convolution, the quantized filter comprising a plurality of quantized weights of the convolution (“For example, the inputs to the subtraction engine may include an 8-bit weight W.sub.q 934 , an 8-bit input data element X.sub.q 932 (e.g., a pixel of an image or a feature map), an 8-bit zero-point integer W.sub.qz 936 for the weights, and an 8-bit zero-point integer X.sub.qz 938 for the input data elements.”) and a processing element array, the processing element array to perform multiply-accumulate operations on the portion of the quantized input tensor and the portion of the quantized filter from the buffer (Figure 9), the processing element array comprising a plurality of processing elements (Figure 9: 920a-b with 930a-b), a processing element of the plurality of processing elements comprising: a plurality of first subtractors, the plurality of first subtractors to generate intermediate activations by subtracting a first constant from quantized activations in the portion of the quantized input tensor (Figure 9: 930a-d, where each “SUB” contains a subtractor for 932/938 to handle activations, “For example, the inputs to the subtraction engine may include an 8-bit weight W.sub.q 934 , an 8-bit input data element X.sub.q 932 (e.g., a pixel of an image or a feature map), an 8-bit zero-point integer W.sub.qz 936 for the weights, and an 8-bit zero-point integer X.sub.qz 938 for the input data elements.”), a plurality of second subtractors the plurality of second subtractors to generate intermediate weights by subtracting a second constant from quantized weights in the portion of the quantized filter (Figure 9: 930a-d, where each “SUB” contains a subtractor for 934/936 to hand weights, “For example, the inputs to the subtraction engine may include an 8-bit weight W.sub.q 934 , an 8-bit input data element X.sub.q 932 (e.g., a pixel of an image or a feature map), an 8-bit zero-point integer W.sub.qz 936 for the weights, and an 8-bit zero-point integer X.sub.qz 938 for the input data elements.”), an input storage unit, the input storage unit to store the intermediate activations generated by the plurality of first subtractors (“Each PE may also include sequential logic circuitries (e.g., registers, latches, state machines, etc.) to store input data, weights, and output data for the adder and multiplier circuitry, and to synchronize the flow of the data into and out of the circuitry.”), a weight storage unit, the weight storage unit to store the intermediate weights generated by the plurality of second subtractors (“Each PE may also include sequential logic circuitries (e.g., registers, latches, state machines, etc.) to store input data, weights, and output data for the adder and multiplier circuitry, and to synchronize the flow of the data into and out of the circuitry.”), and a plurality of multipliers, the plurality of multipliers to perform multiplication operations on the intermediate activations and the intermediate weights, each multiplier corresponding to a different pair of subtractors, the different pair of subtractors comprising a different one of the plurality of first subtractors and a different one of the plurality of second subtractors (Figure 9: 922 of each PE, “For example, a PE may receive an input data element and a weight (e.g., from row input bus 922 ) and generate, using multiplier 923 , a multiplication product to represent a weighted input data element.”, also see ¶108. Each “SUB”, as noted above, contains one of the first and second subtractors. Per Figure 9, each of 930-d is input into a different PE, which contain the multipliers. Therefore, for each of 920a-d, one of the plurality of multiplies is receiving input from a different one of the first and second subtractors, e.g. 930a to 920a vs. 930b to 920b) wherein a multiplication operation by a multiplier includes a multiplication of an intermediate activation from the input storage unit and an intermediate weight from the weight storage unit (Figure 9: 922, “For example, a PE may receive an input data element and a weight (e.g., from row input bus 922 ) and generate, using multiplier 923 , a multiplication product to represent a weighted input data element.”, also see ¶108). Regarding claim 12 , Vantrease teaches all of the limitations of claim 11, further comprising: a memory, the memory to store the quantized input tensor and the quantized filter, wherein the portion of the quantized input tensor and the portions of the quantized filter are written into the buffer from the memory (¶74, the state buffer receives weights and inputs from memory). Regarding claim 13 , Vantrease teaches all of the limitations of claim 11, wherein the processing element further comprises: an adder assembly, the adder assembly to generate an intermediate output of the processing element by accumulating products generated by the plurality of multipliers (Figure 9: 925). Regarding claim 14 , Vantrease teaches all of the limitations of claim 13, wherein the processing element further comprises: an adder assembly, the adder assembly to generate an intermediate output of the processing element by accumulating products generated by the plurality of multipliers (“As described above, if X.sub.q and W.sub.q are 8-bit unsigned integers, X.sub.adj and Y.sub.adj may be 9-bit signed integers. Thus, the multiplication may be performed on 9-bit signed integers, and the product of each multiplication may be represented by, for example, an 18-bit integer. The sum Z of the products may be represented by, for example, a 32-bit integer.”); an additional multiplier, the additional multiplier to generate an output of the processing element by multiplying the intermediate output of the processing element with a constant, wherein the intermediate output is an integer, and the output is a floating-point number (“In the third step, the sum Z of the products from the second step may be scaled by a floating point scaling factor S.sub.XS.sub.W to convert the integer sum of products into a floating point number:”). Regarding claim 15 , Vantrease teaches all of the limitations of claim 13, wherein the processing element array further comprises: an additional processing element, the additional processing element to generate an additional intermediate output; and an accumulator, the accumulator to generate an intermediate partial sum by accumulating the intermediate output and the additional intermediate output (¶110). Regarding claim 16 , Vantrease teaches all of the limitations of claim 15, further comprising: an additional multiplier, the additional multiplier to generate a partial sum by multiplying the intermediate partial sum with a constant, wherein the intermediate partial sum is an integer, and the partial sum is a floating- point number (“In the third step, the sum Z of the products from the second step may be scaled by a floating point scaling factor S.sub.XS.sub.W to convert the integer sum of products into a floating point number:”). Regarding claim 19 , Vantrease teaches all of the limitations of claim 11, wherein the input storage unit comprises a plurality of register files, each register file to store one or more intermediate activations to be used by a different multiplier of the plurality of multipliers (“Each PE may also include sequential logic circuitries (e.g., registers, latches, state machines, etc.) to store input data, weights, and output data for the adder and multiplier circuitry, and to synchronize the flow of the data into and out of the circuitry.”) Regarding claim 20 , Vantrease teaches all of the limitations of claim 11, wherein the weight storage unit comprises a plurality of register files, each register file to store one or more intermediate activations to be used by a different multiplier of the plurality of multipliers (“Each PE may also include sequential logic circuitries (e.g., registers, latches, state machines, etc.) to store input data, weights, and output data for the adder and multiplier circuitry, and to synchronize the flow of the data into and out of the circuitry.”) Regarding claim 1 , Vantrease according to claim 11 includes the processing element of claim 1 and therefore similarly anticipates claim 1. Regarding claim 2 , Vantrease according to claim 13 similarly anticipates claim 2. Regarding claim 3 , Vantrease according to claim 14 similarly anticipates claim 3. Regarding claim 4, Vantrease according to claim 15 similarly anticipates claim 4. Regarding claim 5 , Vantrease teaches all of the limitations of claim 4, further comprising: An output storage unit configured to store the intermediate partial sum (¶110). Regarding claim 6 , Vantrease according to claim 16 similarly anticipates claim 6. Regarding claims 9-10 , Vantrease according to claims 19-20 similarly anticipates claims 9-10, respectively. Regarding claim 21 , Vantrease according to claim 11 performs the method of claim 21 under normal operation. Regarding claim 22 , Vantrease according to claim 15 performs the method of claim 22 under normal operation. Regarding claim 23 , Vantrease according to claim 14 performs the method of claim 23 under normal operation. Regarding claim 24 , Vantrease according to claim 16 performs the method of claim 24 under normal operation . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim (s) 7, 17, and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vantrease (US20190294413A1) in view of Song (US20210208885A1) . Regarding claim 17 , Vantrease teaches all of the limitations of claim 13, but does not teach wherein: the adder assembly comprises a first adder and a second adder, the first adder to generate a first sum by accumulating products generated by two multipliers of the plurality of multipliers, the second adder to generate a second sum by accumulating products generated by two other multipliers of the plurality of multipliers, and the processing element further comprises a first pipeline register and a second pipeline register, the first pipeline register to store the first sum and the second pipeline register to store the second. Song teaches a first adder and a second adder, the first adder is configured to generate a first sum by accumulating products generated by two multipliers of the plurality of multipliers, the second adder is configured to generate a second sum by accumulating products generated by two other multipliers of the plurality of multipliers, and the processing element further comprises a first pipeline register configured to store the first sum and a second pipeline register configured to store the second (¶74-75, products are generated and added in a tree. Each sum can be considered to be stored in its own register between adding because the values are carried over and therefore are at least temporarily stored). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize an adder assembly in Vantrease which comprises a first adder and a second adder, the first adder is configured to generate a first sum by accumulating products generated by two multipliers of the plurality of multipliers, the second adder is configured to generate a second sum by accumulating products generated by two other multipliers of the plurality of multipliers, and the processing element further comprises a first pipeline register configured to store the first sum and a second pipeline register configured to store the second in order to efficiently add products into partial sums. Regarding claims 7 and 25 , Vantrease as modified according to claim 17 performs the method of claim 25 under normal operation and covers the limitations of claim 7. Response to Arguments Applicant’s remarks filed 04/13/2026 have been fully considered. Applicant has stated that the amended claims do not fall under 35 USC 112(f). However, per the three-prong analysis in MPEP 2181, I, the claims still fall under 35 USC 112(f). In the instant application, adding the term “circuit” to “processing element”, i.e. “processing element circuit” or “processing circuit” would not fall under 35 USC 112(f). Applicant’s remarks assert that Vantrease does not teach the first and second subtractors or multiplies as recited in the amended claims. As explained/shown herein, Vantrease discloses first and second subtractors and a different set of first/second subtractors for each multiplier. Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCHYLER S SANKS whose telephone number is (571)272-6125. The examiner can normally be reached 06:30 - 15:30 Central Time, M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michael Huntley can be reached at (303) 297-4307. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SCHYLER S SANKS/Primary Examiner, Art Unit 2129 Application/Control Number: 18/047,415 Page 2 Art Unit: 2129 Application/Control Number: 18/047,415 Page 3 Art Unit: 2129 Application/Control Number: 18/047,415 Page 4 Art Unit: 2129 Application/Control Number: 18/047,415 Page 5 Art Unit: 2129 Application/Control Number: 18/047,415 Page 6 Art Unit: 2129 Application/Control Number: 18/047,415 Page 7 Art Unit: 2129 Application/Control Number: 18/047,415 Page 8 Art Unit: 2129 Application/Control Number: 18/047,415 Page 9 Art Unit: 2129 Application/Control Number: 18/047,415 Page 10 Art Unit: 2129 Application/Control Number: 18/047,415 Page 11 Art Unit: 2129 Application/Control Number: 18/047,415 Page 12 Art Unit: 2129 Application/Control Number: 18/047,415 Page 13 Art Unit: 2129 Application/Control Number: 18/047,415 Page 14 Art Unit: 2129 Application/Control Number: 18/047,415 Page 15 Art Unit: 2129
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