DETAILED ACTION
This action is responsive to U.S. Patent Application No. 18/047,954 filed on 19 October 2022.
Regarding Applicant’s Petition Under 37 CFR 1.59(b) to Expunge Information, Applicant identified four documents for expungement from the record (See Petition for Review by the Office of Petitions (filed 16 December 2024) at 1), including an Amendment/Request for Reconsideration-After Non-Final Rejection (filed 16 November 2022), Claims (filed 16 November 2022), Applicant Arguments/Remarks Made in an Amendment (filed 16 November 2022), and Electronic Filing System Acknowledgment Receipt (filed 16 November 2022). Each of the four documents were reviewed by the Examiner.
None of the documents identified by Applicant in the Petition Under 37 CFR 1.59(b) to Expunge Information are considered by the Examiner to be material to the determination of patentability (See Petition Decision (mailed 20 May 2025) at 2 (defining materiality “as any information which the examiner considers as being important to a determination of patentability of the application.”).
Prosecution on the merits of claims 1-20, filed 22 May 2025 in Applicant’s Preliminary Amendment, is as follows.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement(s) (IDS). The IDS(es) has/have been considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 7-10, and 17-20 are rejected under 35 U.S.C. § 102(a)(2) as being anticipated by U.S. Patent Publication No. 2023/0178651 (filed Dec. 8, 2021) (hereinafter “Zhang”).
Regarding independent claim 1, Zhang discloses: A vertical transport field effect transistor (VTFET) (FIG. 32A, depicting a VTFET device, [0041]), comprising:
a plurality of field effect transistor, FET, structures (FIG. 32A, depicting a plurality of VTFETs including top and bottom VTFETs 1 and 2, [0007]) on a substrate (FIG. 32A, depicting wherein the top and bottom VTFETs 1 and 2 are on substrate 102, [0046]);
the plurality of FET structures (FIG. 32A, depicting a plurality of VTFETs including top and bottom VTFETs 1 and 2) comprising:
a first n-type FET structure (FIG. 32A, [0066]: “Thus, in accordance with the present techniques, the bottom VTFETs (i.e., bottom VTFET1 and bottom VTFET2) can be either an NFET or a PFET. Likewise, the top VTFETs (i.e., top VTFET1 and top VTFET2) can be either an NFET or a PFET. In the example that follows, the bottom VTFETs (i.e., bottom VTFET1 and bottom VTFET2) are NFETs while the top VTFETs (i.e., top VTFET1 and top VTFET2) are PFETs. However, given the instant description, one skilled in the art would be able to instead form the bottom VTFETs (i.e., bottom VTFET1 and bottom VTFET2) as PFETs and the top VTFETs (i.e., top VTFET1 and top VTFET2) as NFETs.”) oriented in a first plane direction relative to the substrate (FIG. 32A, depicting wherein the bottom VTFET devices, which may be NFETs, are oriented in a first plane direction with respect to the substrate 102, [0048]); and
a first p-type FET structure (FIG. 32A, [0066]: “Thus, in accordance with the present techniques, the bottom VTFETs (i.e., bottom VTFET1 and bottom VTFET2) can be either an NFET or a PFET. Likewise, the top VTFETs (i.e., top VTFET1 and top VTFET2) can be either an NFET or a PFET. In the example that follows, the bottom VTFETs (i.e., bottom VTFET1 and bottom VTFET2) are NFETs while the top VTFETs (i.e., top VTFET1 and top VTFET2) are PFETs. However, given the instant description, one skilled in the art would be able to instead form the bottom VTFETs (i.e., bottom VTFET1 and bottom VTFET2) as PFETs and the top VTFETs (i.e., top VTFET1 and top VTFET2) as NFETs.”) oriented in a second plane direction relative to the substrate (FIG. 32A, depicting wherein the top VTFET devices, which may be PFETs, are oriented in a second plane direction with respect to the substrate 102, wherein the first and second plane directions are the same, [0048]);
wherein the first n-type FET structure (FIG. 32A, depicting wherein the bottom VTFET devices, which may be NFETs) and the first p-type FET structure (FIG. 32A, depicting wherein the top VTFET devices, which may be PFETs) each comprises a channel comprising a FIN (FIGS. 32A/33, depicting wherein each of the top and bottom VTFETS include a vertical fin channel 2512/2514, [0093]) having a FIN height, H, wherein H defines the FIN height orthogonal to a surface of the substrate (FIGS. 32A/33, depicting wherein each of the vertical fin channels 2512/2514 have a fin height H, wherein H defines the height of the vertical fin channel 2512/2514 in a direction orthogonal to a surface of the substrate 102),
each FIN (FIGS. 32A/33, vertical fin channels 2512/2514) being configured to transport charge carriers orthogonal to the surface of the substrate along the FIN height (FIGS. 32A/33, depicting wherein the source/drain regions 2508/2510 are disposed above/below the vertical fin channel such that charge carriers would be transported orthogonal to the surface of the substrate 102).
Regarding claim 3, Zhang further discloses wherein the first n-type FET structure (FIG. 32A, depicting the bottom VTFET devices, which may be NFETs) comprises an NMOS transistor (FIGS. 32A/33, depicting wherein the bottom VTFET devices, which may be NFETs, are MOS transistors, [0049], [0088], [0090]); and
the first p-type FET structure (FIG. 32A, depicting the top VTFET devices, which may be PFETs) comprises a PMOS transistor (FIGS. 32A/33, depicting wherein the top VTFET devices, which may be PFETs, are MOS transistors, [0049], [0088], [0090]).
Regarding claim 7, Zhang further discloses wherein the NMOS transistor (FIGS. 32A/33, depicting wherein the bottom VTFET devices, which may be NFETs, are MOS transistors, [0049], [0088], [0090]) and the PMOS transistor (FIGS. 32A/33, depicting wherein the top VTFET devices, which may be PFETs, are MOS transistors, [0049], [0088], [0090]) of the VTFET are arranged in a vertical stack configuration relative to the surface of the substrate to form a vertical transport complementary FET, (VTCFET) (FIGS. 32A/33, depicting wherein the top and bottom VTFETs are vertically stacked relative to the surface of the substrate 102 to form a vertical transport complementary FET, (VTCFET); [0043]: “With a monolithically stacked vertical transport field-effect transistor (VTFET) device architecture, one VTFET device is placed directly on top of another, complementary VTFET device. For instance, a p-channel FET (PFET) VTFET device can be stacked on top of an n-channel FET (NFET) VTFET device, or vice versa.”).
Regarding claim 8, Zhang further discloses wherein each of the first n-type FET structure (FIG. 32A, depicting the bottom VTFET devices, which may be NFETs) and the first p-type FET structure (FIG. 32A, depicting the top VTFET devices, which may be PFETs) further comprises: a FIN width, W, and a FIN length, L, (FIGS. 32A/B, depicting wherein the vertical fin channels 2512/2514 possess a width and a length) the FIN length being adjustable to provide a predefined effective channel width, Weff, for the channel (FIGS. 32A/B, depicting wherein the vertical fin channels 2512/2514 possess a length and width that are different from each other and are thus adjustable and further provide the vertical fin channels 2512/2514 with a predetermined effective channel width Weff).
Regarding claim 9, Zhang further discloses wherein each of the first n-type FET structure (FIG. 32A, depicting the bottom VTFET devices, which may be NFETs) and the first p- type FET structure (FIG. 32A, depicting the top VTFET devices, which may be PFETs) further comprises a gate structure (FIG. 32A, depicting wherein the top and bottom VFET devices each include a gate stack comprising a gate dielectric and a gate conductor, [0026], [0041]), the gate structure surrounding the channel (FIGS. 32A/B, 33, depicting wherein the gate stack (i.e., gate dielectric 2404/1702 and gate conductor 2406/1704) surrounds the vertical fin channels 2512/2514).
Regarding independent claim 10, Zhang discloses: A method of fabricating a vertical transport field effect transistor (VTFET) (FIGS. 1-33, depicting a method of forming a VTFET device, [0046]), the method comprising:
forming a plurality of FET structures (FIGS. 1-33, depicting the formation of a plurality of VTFETs including top and bottom VTFETs 1 and 2, [0007]) on a substrate (FIGS. 1-33, depicting wherein the top and bottom VTFETs 1 and 2 are on substrate 102, [0046]);
the plurality of FET structures (FIG. 32A, depicting a plurality of VTFETs including top and bottom VTFETs 1 and 2) comprising:
a first n-type FET structure (FIG. 32A, [0066]: “Thus, in accordance with the present techniques, the bottom VTFETs (i.e., bottom VTFET1 and bottom VTFET2) can be either an NFET or a PFET. Likewise, the top VTFETs (i.e., top VTFET1 and top VTFET2) can be either an NFET or a PFET. In the example that follows, the bottom VTFETs (i.e., bottom VTFET1 and bottom VTFET2) are NFETs while the top VTFETs (i.e., top VTFET1 and top VTFET2) are PFETs. However, given the instant description, one skilled in the art would be able to instead form the bottom VTFETs (i.e., bottom VTFET1 and bottom VTFET2) as PFETs and the top VTFETs (i.e., top VTFET1 and top VTFET2) as NFETs.”) oriented in a first plane direction relative to the substrate (FIG. 32A, depicting wherein the bottom VTFET devices, which may be NFETs, are oriented in a first plane direction with respect to the substrate 102, [0048]); and
a first p-type FET structure (FIG. 32A, [0066]: “Thus, in accordance with the present techniques, the bottom VTFETs (i.e., bottom VTFET1 and bottom VTFET2) can be either an NFET or a PFET. Likewise, the top VTFETs (i.e., top VTFET1 and top VTFET2) can be either an NFET or a PFET. In the example that follows, the bottom VTFETs (i.e., bottom VTFET1 and bottom VTFET2) are NFETs while the top VTFETs (i.e., top VTFET1 and top VTFET2) are PFETs. However, given the instant description, one skilled in the art would be able to instead form the bottom VTFETs (i.e., bottom VTFET1 and bottom VTFET2) as PFETs and the top VTFETs (i.e., top VTFET1 and top VTFET2) as NFETs.”) oriented in a second plane direction relative to the substrate (FIG. 32A, depicting wherein the top VTFET devices, which may be PFETs, are oriented in a second plane direction with respect to the substrate 102, wherein the first and second plane directions are the same, [0048]);
wherein the first n-type FET structure (FIG. 32A, depicting wherein the bottom VTFET devices, which may be NFETs) and the first p-type FET structure (FIG. 32A, depicting wherein the top VTFET devices, which may be PFETs) each comprises a channel comprising a FIN (FIGS. 32A/33, depicting wherein each of the top and bottom VTFETS include a vertical fin channel 2512/2514, [0093]) having a FIN height, H, wherein H defines the FIN height orthogonal to a surface of the substrate (FIGS. 32A/33, depicting wherein each of the vertical fin channels 2512/2514 have a fin height H, wherein H defines the height of the vertical fin channel 2512/2514 in a direction orthogonal to a surface of the substrate 102),
each FIN (FIGS. 32A/33, vertical fin channels 2512/2514) being configured to transport charge carriers orthogonal to the surface of the substrate along the FIN height (FIGS. 32A/33, depicting wherein the source/drain regions 2508/2510 are disposed above/below the vertical fin channel such that charge carriers would be transported orthogonal to the surface of the substrate 102).
Regarding claim 17, Zhang further discloses wherein the method further comprises: defining a FIN width, W, and a FIN length, L, (FIGS. 1-33, depicting wherein the vertical fin channels 2512/2514 possess a width and a length) the FIN length being adjustable to provide a predefined effective channel width, Weff, for the channel (FIGS. 1-33, depicting wherein the vertical fin channels 2512/2514 possess a length and width that are different from each other and are thus adjustable and further provide the vertical fin channels 2512/2514 with a predetermined effective channel width Weff).
Regarding claim 18, Zhang further discloses wherein the method further comprises: forming a gate structure (FIGS. 1-33, depicting the formation of a gate stack comprising a gate dielectric and a gate conductor, [0026], [0041]), the gate structure surrounding the channel (FIGS. 32A/B, 33, depicting wherein the gate stack (i.e., gate dielectric 2404/1702 and gate conductor 2406/1704) surrounds the vertical fin channels 2512/2514).
Regarding claim 19, Zhang further discloses wherein Weff is defined by an equation Weff=2L+ 2W (FIGS. 1-33, depicting wherein the vertical fin channels 2512/2514 are surrounded by a gate stack (i.e., gate dielectric 2404/1702 and gate conductor 2406/1704) such that all four sides of the vertical fin channels 2512/2514 are surrounded by the gate stack, and thus the Weff of the vertical fin channels 2512/2514 can be calculated as 2L+ 2W)
Regarding claim 20, Zhang further discloses wherein an effective length of the gate structure, Leff, is defined based on the FIN height (FIGS. 1-33, depicting wherein the source/drain regions 2508/2510 are disposed above/below the vertical fin channel such that charge carriers would be transported orthogonal to the surface of the substrate 102, and such that the effective length of the gate stack (i.e., gate dielectric 2404/1702 and gate conductor 2406/1704) would be based on the height of the vertical fin channels 2512/2514).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 4-6, and 11-16 are rejected under 35 U.S.C. § 103 as being unpatentable over Zhang in view of U.S. Patent Publication No. 2018/0240716 (filed Feb. 17, 2017) (hereinafter “Cheng”).
Regarding claim 2, Zhang does not specifically disclose wherein the first plane direction is oriented 45 degrees relative to the second plane direction.
In the same field of endeavor, Cheng discloses a VTFET structure (FIG. 1, VFET structure 5, [0035]) including both an n-type FET structure (FIG. 1, NFET device 150, [0035]) and a p-type FET structure (FIG. 1, PFET device 152, [0035]) on a substrate (FIG. 1, semiconductor substrate 10, [0037]), each of the n-type and p-type FET structures including fins configured to transport charge carriers orthogonal to the surface of the substrate (FIG. 1, fins 52B and 62B, configured to transport charge carriers in a direction orthogonal to the surface of the semiconductor substrate 10, [0040]). Cheng further discloses wherein each of the substrate 10, NFET device 150, and PFET device 152 possess certain crystal structures identified by Miller indices, and further wherein the semiconductor substrate 10 is a (100) semiconductor substrate, [0041], the NFET has a (100) channel transport direction, [0041], and the PFET has a (110) channel transport direction, [0041]. Regarding the varying crystal structures, in [0033], Cheng states: “In semiconductor materials, carrier mobility is strongly dependent on channel surface orientation and transport direction. In an unstrained channel, {100} surface gives the highest mobility for electrons while {110} surfaces combined with <110> channel direction yield the highest mobility for holes.” Cheng further states in [0035]-[0036]: “The NFET 150 has a channel transport direction <100> and a channel surface orientation {001}. In the NFET device 150, the {001} surface orientation favors electron mobility. The PFET 152 has a channel transport direction <110> and a channel surface orientation {1-10}. In the PFET device 152, the channel transport direction <110> is the direction that holes (i.e., which are the majority carrier in PFETs) travel between the source and drain (e.g., between source/drain 62A and source/drain 62C). The <110> orientation for the channel transport direction with {110} or {1-10} family surfaces provide the highest mobility for holes.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed VTFET device of Zhang by substituting the substrate (100), NFET fin (100), and PFET fin (110) crystal structures of Cheng, thereby resulting in a configuration wherein the vertical fin structures 2512 of the NFETs are oriented 45 degrees relative to the second plane direction of the vertical fin structures 2514 of the PFETs in order improve electron mobility in the NFET and hole mobility in the PFET. See Cheng [0033], [0035]-[0036].
Regarding claim 4, Zhang does not specifically disclose wherein the substrate of the VTFET is a (100) silicon substrate.
In the same field of endeavor, Cheng discloses a VTFET structure (FIG. 1, VFET structure 5, [0035]) including both an n-type FET structure (FIG. 1, NFET device 150, [0035]) and a p-type FET structure (FIG. 1, PFET device 152, [0035]) on a substrate (FIG. 1, semiconductor substrate 10, [0037]), each of the n-type and p-type FET structures including fins configured to transport charge carriers orthogonal to the surface of the substrate (FIG. 1, fins 52B and 62B, configured to transport charge carriers in a direction orthogonal to the surface of the semiconductor substrate 10, [0040]). Cheng further discloses wherein each of the substrate 10, NFET device 150, and PFET device 152 possess certain crystal structures identified by Miller indices, and further wherein the semiconductor substrate 10 is a (100) semiconductor substrate, [0041], the NFET has a (100) channel transport direction, [0041], and the PFET has a (110) channel transport direction, [0041]. Regarding the varying crystal structures, in [0033], Cheng states: “In semiconductor materials, carrier mobility is strongly dependent on channel surface orientation and transport direction. In an unstrained channel, {100} surface gives the highest mobility for electrons while {110} surfaces combined with <110> channel direction yield the highest mobility for holes.” Cheng further states in [0035]-[0036]: “The NFET 150 has a channel transport direction <100> and a channel surface orientation {001}. In the NFET device 150, the {001} surface orientation favors electron mobility. The PFET 152 has a channel transport direction <110> and a channel surface orientation {1-10}. In the PFET device 152, the channel transport direction <110> is the direction that holes (i.e., which are the majority carrier in PFETs) travel between the source and drain (e.g., between source/drain 62A and source/drain 62C). The <110> orientation for the channel transport direction with {110} or {1-10} family surfaces provide the highest mobility for holes.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed VTFET device of Zhang by substituting the substrate (100), NFET fin (100), and PFET fin (110) crystal structures of Cheng, thereby resulting in a configuration wherein substrate 102 of the VTFET is a (100) silicon substrate in order improve electron mobility in the NFET and hole mobility in the PFET. See Cheng [0033], [0035]-[0036].
Regarding claim 5, Zhang in view of Cheng further discloses wherein the FIN of the PMOS transistor (FIG. 32A, vertical fin structures 2514 of the PFETs) is oriented in a plane direction relative to the substrate surface (FIG. 32A, depicting wherein the top VTFET devices, which may be PFETs including vertical fin structures 2514, are oriented in a plane direction with respect to the substrate 102, [0048]).
Regarding claim 6, Zhang in view of Cheng further discloses wherein the FIN of the NMOS transistor (FIG. 32A, depicting wherein the vertical fin structures 2512 of the NFETs) is oriented in a plane direction relative to the substrate surface (FIG. 32A, depicting wherein the bottom VTFET devices, which may be NFETs including vertical fin structures 2512, are oriented in a plane direction with respect to the substrate 102, [0048]).
Regarding claim 11, Zhang does not specifically disclose wherein the first plane direction is oriented 45 degrees relative to the second plane direction.
In the same field of endeavor, Cheng discloses a VTFET structure (FIG. 1, VFET structure 5, [0035]) including both an n-type FET structure (FIG. 1, NFET device 150, [0035]) and a p-type FET structure (FIG. 1, PFET device 152, [0035]) on a substrate (FIG. 1, semiconductor substrate 10, [0037]), each of the n-type and p-type FET structures including fins configured to transport charge carriers orthogonal to the surface of the substrate (FIG. 1, fins 52B and 62B, configured to transport charge carriers in a direction orthogonal to the surface of the semiconductor substrate 10, [0040]). Cheng further discloses wherein each of the substrate 10, NFET device 150, and PFET device 152 possess certain crystal structures identified by Miller indices, and further wherein the semiconductor substrate 10 is a (100) semiconductor substrate, [0041], the NFET has a (100) channel transport direction, [0041], and the PFET has a (110) channel transport direction, [0041]. Regarding the varying crystal structures, in [0033], Cheng states: “In semiconductor materials, carrier mobility is strongly dependent on channel surface orientation and transport direction. In an unstrained channel, {100} surface gives the highest mobility for electrons while {110} surfaces combined with <110> channel direction yield the highest mobility for holes.” Cheng further states in [0035]-[0036]: “The NFET 150 has a channel transport direction <100> and a channel surface orientation {001}. In the NFET device 150, the {001} surface orientation favors electron mobility. The PFET 152 has a channel transport direction <110> and a channel surface orientation {1-10}. In the PFET device 152, the channel transport direction <110> is the direction that holes (i.e., which are the majority carrier in PFETs) travel between the source and drain (e.g., between source/drain 62A and source/drain 62C). The <110> orientation for the channel transport direction with {110} or {1-10} family surfaces provide the highest mobility for holes.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed VTFET device of Zhang by substituting the substrate (100), NFET fin (100), and PFET fin (110) crystal structures of Cheng, thereby resulting in a configuration wherein the vertical fin structures 2512 of the NFETs are oriented 45 degrees relative to the second plane direction of the vertical fin structures 2514 of the PFETs in order improve electron mobility in the NFET and hole mobility in the PFET. See Cheng [0033], [0035]-[0036].
Regarding claim 12, Zhang in view of Cheng further discloses wherein the first n-type FET structure (FIG. 32A, depicting the bottom VTFET devices, which may be NFETs) comprises an NMOS transistor (FIGS. 32A/33, depicting wherein the bottom VTFET devices, which may be NFETs, are MOS transistors, [0049], [0088], [0090]); and
the first p-type FET structure (FIG. 32A, depicting the top VTFET devices, which may be PFETs) comprises a PMOS transistor (FIGS. 32A/33, depicting wherein the top VTFET devices, which may be PFETs, are MOS transistors, [0049], [0088], [0090]).
Regarding claim 13, Zhang does not specifically disclose wherein the substrate is a (100) silicon substrate.
In the same field of endeavor, Cheng discloses a VTFET structure (FIG. 1, VFET structure 5, [0035]) including both an n-type FET structure (FIG. 1, NFET device 150, [0035]) and a p-type FET structure (FIG. 1, PFET device 152, [0035]) on a substrate (FIG. 1, semiconductor substrate 10, [0037]), each of the n-type and p-type FET structures including fins configured to transport charge carriers orthogonal to the surface of the substrate (FIG. 1, fins 52B and 62B, configured to transport charge carriers in a direction orthogonal to the surface of the semiconductor substrate 10, [0040]). Cheng further discloses wherein each of the substrate 10, NFET device 150, and PFET device 152 possess certain crystal structures identified by Miller indices, and further wherein the semiconductor substrate 10 is a (100) semiconductor substrate, [0041], the NFET has a (100) channel transport direction, [0041], and the PFET has a (110) channel transport direction, [0041]. Regarding the varying crystal structures, in [0033], Cheng states: “In semiconductor materials, carrier mobility is strongly dependent on channel surface orientation and transport direction. In an unstrained channel, {100} surface gives the highest mobility for electrons while {110} surfaces combined with <110> channel direction yield the highest mobility for holes.” Cheng further states in [0035]-[0036]: “The NFET 150 has a channel transport direction <100> and a channel surface orientation {001}. In the NFET device 150, the {001} surface orientation favors electron mobility. The PFET 152 has a channel transport direction <110> and a channel surface orientation {1-10}. In the PFET device 152, the channel transport direction <110> is the direction that holes (i.e., which are the majority carrier in PFETs) travel between the source and drain (e.g., between source/drain 62A and source/drain 62C). The <110> orientation for the channel transport direction with {110} or {1-10} family surfaces provide the highest mobility for holes.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed VTFET device of Zhang by substituting the substrate (100), NFET fin (100), and PFET fin (110) crystal structures of Cheng, thereby resulting in a configuration wherein substrate 102 of the VTFET is a (100) silicon substrate in order improve electron mobility in the NFET and hole mobility in the PFET. See Cheng [0033], [0035]-[0036].
Regarding claim 14, Zhang in view of Cheng further discloses wherein the FIN of the PMOS transistor (FIG. 32A, vertical fin structures 2514 of the PFETs) is oriented in a plane direction relative to the substrate surface (FIG. 32A, depicting wherein the top VTFET devices, which may be PFETs including vertical fin structures 2514, are oriented in a plane direction with respect to the substrate 102, [0048]).
Regarding claim 15, Zhang in view of Cheng further discloses wherein the FIN of the NMOS transistor (FIG. 32A, depicting wherein the vertical fin structures 2512 of the NFETs) is oriented in a plane direction relative to the substrate surface (FIG. 32A, depicting wherein the bottom VTFET devices, which may be NFETs including vertical fin structures 2512, are oriented in a plane direction with respect to the substrate 102, [0048]).
Regarding claim 16, Zhang in view of Cheng further discloses wherein the NMOS transistor (FIGS. 32A/33, depicting wherein the bottom VTFET devices, which may be NFETs, are MOS transistors, [0049], [0088], [0090]) and the PMOS transistor (FIGS. 32A/33, depicting wherein the top VTFET devices, which may be PFETs, are MOS transistors, [0049], [0088], [0090]) are arranged in a vertical stack configuration relative to the surface of the substrate to form a vertical transport complementary FET, (VTCFET) (FIGS. 32A/33, depicting wherein the top and bottom VTFETs are vertically stacked relative to the surface of the substrate 102 to form a vertical transport complementary FET, (VTCFET); [0043]: “With a monolithically stacked vertical transport field-effect transistor (VTFET) device architecture, one VTFET device is placed directly on top of another, complementary VTFET device. For instance, a p-channel FET (PFET) VTFET device can be stacked on top of an n-channel FET (NFET) VTFET device, or vice versa.”).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: U.S. Patent Publication Nos.: 2024/0072051 (filed Sept. 25, 2022); 2020/0343222 (filed Apr. 26, 2019); 2020/0161303 (filed Nov. 22, 2019); U.S. Patent No. 9,799,749 (filed Sept. 18, 2016).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM D WEILAND whose telephone number is (703)756-4760. The examiner can normally be reached Monday - Friday 9am-5pm.
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ADAM D. WEILAND
Examiner
Art Unit 4128
/ADAM D WEILAND/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813