Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 20-23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Maeda (20100060354).
Regarding claim 20, Maeda (Fig. 1) discloses a circuit having an input (IN) and an output (OUT), the circuit comprising: a filter network (FL2) having first and second terminals and a switching network (SW1 and SW2) having an input coupled to the input of the circuit and having an output, the switching network comprising: one or more switches (SW1/SW2) coupled to the filter network and configured such that in a first state (switch (SW1) closes and switch (SW2) opens) provides a first signal path having a first filter configuration between the input of the circuit and the output of the circuit and in a second state (switch (SW1) opens and switch (SW2) cloases) provides a second signal path having a second, different filter configuration between the input of the circuit and the output of the circuit.
Regarding claim 21, wherein the filter network is provided as a pulse shaping network (PSN) configured to filter a modulated power signal provided is considered an intended use of the invention, wherein the reference circuit can be used in a pulse shaping network, which has at least one passive component (inductor/capacitor of Fig. 1).
Regarding claim 22, wherein the switching network (SW1) is coupled across the filter network (FL2) and configured to selectively short (SW2) the filter network.
Regarding claim 23, wherein the switching network (SW1) is coupled across at least one electronic element (C24/C26) of the filter network (FL2) and configured to alter a transfer function of the filter network by selectively shorting (SW2 closes) the at least one electronic element.
Claim(s) 20, 21, 24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Saragourtz et al. (3,718,873), hereafter called SARAGOURTZ.
Regarding claim 20, SARAGOURTZ (Fig. 7a) discloses a circuit having an input and an output, where switches (82 and 84) are connected, the circuit comprising: a filter network formed by capacitors (70, 72 and 80) and inductors (74, 76 and 78) having first and second terminals, where switches (82 and 84) are connected; and a switching network (82 and 84) having an input coupled to the input of the circuit and having an output, the switching network comprising: one or more switches (82/84) coupled to the filter network and configured such that in a first state (switches (82 and 84) connected to capacitors (70 and 72), respectively, to form a path between input and output), the switching network provides a first signal path having a first filter configuration (high pass filter formed by capacitors (70 and 72) and inductor (74)) between the input of the circuit and the output of the circuit and in a second state (switches (82 and 84) connected to inductors (76 and 78), respectively, to form a path between input and output), the switching network provides a second signal path having a second, different filter configuration (low pass filter formed by inductors (76 and 78) and capacitor (80)) between the input of the circuit and the output of the circuit.
Regarding claim 21, wherein the filter network is provided as a pulse shaping network (PSN) configured to filter a modulated power signal provided is considered an intended use of the invention, wherein the reference circuit can be used in a pulse shaping network, which has at least one passive component (inductor/capacitor of Fig. 7a).
Regarding claim 24, wherein the switching network (82 and 84) is coupled between the input of the circuit and the output of the circuit to electrically connect the input of the circuit from the output of the circuit.
Claim(s) 20 and 21 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by ISHIHARA et al. (20190131941), hereafter called ISHIHARA.
Regarding claim 20, ISHIHARA (Figs. 3-5) discloses a circuit (box includes filters (FL1 and FL2)) having an input and an output, the circuit comprising: a filter network (Fl1 and FL2) formed by capacitors (C1-C3) and inductors (L1-L3) having first and second terminals; and a switching network (SW1 and SW2) having an input coupled to the input of the circuit and having an output, the switching network comprising: one or more switches (SW1/Sw2) coupled to the filter network and configured such that in a first state (switch (SW1) closes and switch (SW2) opens) to form a path between input and output, the switching network provides a first signal path having a first filter configuration (low pass filter (FL1)) between the input of the circuit and the output of the circuit and in a second state (switch (SW1) opens and switch (SW2) closes) to form a path between input and output, the switching network provides a second signal path having a second, different filter configuration (high pass filter (FL2)) between the input of the circuit and the output of the circuit.
Regarding claim 21, wherein the filter network is provided as a pulse shaping network (PSN) configured to filter a modulated power signal provided is considered an intended use of the invention, wherein the reference circuit can be used in a pulse shaping network, which has at least one passive component (inductor/capacitor of Fig. 3).
Allowable Subject Matter
Claims 25-28 and 30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 25, prior art(s) does not disclose the switching network comprises a plurality of switches and at least a first set of the plurality of switches are located on a first integrated circuit die and at least a second set of the plurality of switches are located on a second, different integrated circuit die.
Regarding claims 26-28 and 30, prior art(s) does not disclose the switching network comprises a plurality of switches, and wherein at least some of the plurality of switches in the switching network are coupled in a T-configuration.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional reference(s) cited in PTO-892 show further analogous prior art circuitry.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Khanh V. Nguyen whose telephone number is (571) 272-1767. The examiner can normally be reached from 8:30 AM – 5:00 PM EST.
Examiner interviews are available via telephone and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LINDGREN BALTZELL ANDREA can be reached on (571) 272-5918. The fax phone numbers for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application lnformation Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KHANH V NGUYEN/ Primary Examiner, Art Unit 2843