DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Claims 1, 10 and 13 have been amended. Claims 19-20 have been newly added. Claims 1-20 remain pending and are ready for examination.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on October 16th, 2025 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 19-20 objected to because of the following informalities: Claims 19 and 20 repeatedly use the term “an n number of word lines”, sometimes using the term to refer to a first set of word lines and sometimes using the term to refer to a second set of word lines. The claims should be amended to better clarify which number of word lines refer to the same n number and which refer to a different number, by changing the repeated use of the term “n number of…”, making it clear whether or not the “n number” corresponds to the same number or a different number.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 5 and 7-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chibvongodze et al. (US Publication No. 2020/0365210 -- "Chibvongodze") in view of Yip et al. (US Publication No. 2022/0076751 -- "Yip") in further view of Kwon et al. (US Publication No. 2022/0130849 -- "Kwon") and further in view of Sukekawa (US Publication No. 2020/0286859 – “Sukekawa”).
Regarding claim 1, Chibvongodze teaches A memory device comprising: a first wafer including a first memory block and a second memory block; and a second wafer, arranged in a vertical direction with respect to the first wafer, including a third memory block with a stack number of vertically stacked word lines and a number of strings, (Chibvongodze paragraph [0039], In one embodiment, memory structure 126 comprises a three-dimensional memory array of non-volatile memory cells in which multiple memory levels are formed above a single substrate, such as a wafer. The memory structure may comprise any type of non-volatile memory that are monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon (or other type of) substrate. In one example, the non-volatile memory cells comprise vertical NAND strings with charge-trapping material. The plurality of semiconductor wafers contains flash NAND memory consisting of a plurality of memory blocks as well as word line and strings, which can be arranged in a vertical configuration) each respectively larger than a stack number of vertically stacked word lines (Chibvongodze Fig. 4; Chibvongodze paragraph [0096], FIG. 4 is a perspective view of a portion of one example embodiment of a monolithic three dimensional memory array that can comprise memory structure 126, which includes a plurality non-volatile memory cells. For example, FIG. 4 shows a portion of one block comprising memory. The structure depicted includes a set of bit lines BL positioned above a stack of alternating dielectric layers and conductive layers with vertical columns of materials extending through the dielectric layers and conductive layers. For example purposes, one of the dielectric layers is marked as D and one of the conductive layers (also called word line layers) is marked as W. The wordlines comprised in the block may be stacked in the vertical direction).
Chibvongodze does not teach a number of strings of the first memory block and each respectively larger than a stack number of vertically stacked word lines and a number of strings of the second memory block, and sharing, by the third memory block, a plurality of word line drivers with the first memory block and the second memory block; wherein the plurality of word line drivers are included in one of the first wafer and the second wafer, and are configured on a substrate of one of the first wafer and the second wafer.
However, Yip teaches sharing, by the third memory block, a plurality of word line drivers with the first memory block and the second memory block (Yip paragraph [0013], A memory sub-system can include high density non-volatile memory devices where retention of data is desired when no power is supplied to the memory device. For example, NAND memory, such as 3D flash NAND memory, offers storage in the form of compact, high density configurations. A non-volatile memory device is a package of one or more die, each including one or more planes. For some types of non-volatile memory devices (e.g., NAND memory), each plane includes of a set of physical blocks. Each block includes of a set of pages. Each page includes a set of memory cells (“cells”). A cell is an electronic circuit that stores information. A data block hereinafter refers to a unit of the memory device used to store data and can include a group of memory cells, a word line group, a word line, or individual memory cells. Each data block can include a number of sub-blocks, where each sub-block is defined by a set of associated pillars (e.g., vertical conductive traces) extending from a shared bit line. Memory pages (also referred to herein as “pages”) store one or more bits of binary data corresponding to data received from the host system. To achieve high density, a string of memory cells in a non-volatile memory device can be constructed to include a number of memory cells at least partially surrounding a pillar of channel material. The memory cells can be coupled to access lines, which are commonly referred to as “word lines,” often fabricated in common with the memory cells, so as to form an array of strings in a block of memory. The compact nature of certain non-volatile memory devices, such as 3D flash NAND memory, means word lines are common to many memory cells within a block of memory. The plurality of memory blocks utilizes a shared and overlapping 'word line' structure, also see Yip paragraph [0041], In one embodiment, each respective control gate 350 is connected to a separate word line (i.e., access line), such that each device or memory cell can be separately controlled. The string 300 can be one of multiple strings of memory cells in a block of memory cells in memory device 130. For example, when multiple strings of memory cells are present, each memory cell 312 in string 300 may be connected to a corresponding shared word line, to which a corresponding memory cell in each of the multiple strings is also connected).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Chibvongodze with those of Yip. Yip teaches a plurality of blocks utilizing a shared word line driver, with a large block sharing with at least two small blocks. Yip teaches a flexible quantity of word lines and bit lines, resulting in flexible storage capacity for the memory blocks, while also using a shared vertical word line driver, which can improve memory function and area utilization in the memory devices (Yip paragraph [0016], Advantages of the present disclosure include, but are not limited to, improved area utilization in the memory device. With the vertical string driver circuits being positioned above the memory array, the area under the array on the substrate that would have been occupied by those drivers is available for other circuitry. In addition, as there is a decreased need for vias or other electrical connections to run through the memory array, the storage capacity is increased. Furthermore, when the semiconductor devices of the vertical string driver circuits are formed in a common layer with the select gate devices of the memory strings, the processing costs are greatly reduced, since both sets of devices can be NMOS devices, and fabricated using fewer processing steps/layers).
Chibvongodze in view of Yip does not teach a number of strings of the first memory block and each respectively larger than a stack number of vertically stacked word lines and a number of strings of the second memory block; wherein the plurality of word line drivers are included in one of the first wafer and the second wafer, and are configured on a substrate of one of the first wafer and the second wafer.
However, Kwon teaches a number of strings of the first memory block and each respectively larger than a stack number of vertically stacked word lines and a number of strings of the second memory block (Kwon claim 2, The memory device of claim 1, wherein at least some of the gate electrode layers comprise string selection lines, such that at least one string selection line is included in each of the memory blocks, wherein the number of the string selection lines included in each of the main blocks is greater than the number of the string selection lines included in the first spare block. The number of strings of the first memory block is larger than the corresponding number of strings in the secondary memory blocks, also see Kwon paragraph [0007], The gate electrode layers in each of the memory blocks provide at least one ground selection line, a plurality of word lines, and a plurality of string selection lines, wherein the string selection lines are separated from each other in a second direction, intersecting the first direction and parallel to the upper surface of the substrate. The numbers of the string selection lines included in each memory block of a first group of the memory blocks are different from the number of the string selection lines included in each memory block of a second group of the memory blocks).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Chibvongodze and Yip with those of Kwon. Kwon teaches having a different number of strings in a primary (i.e., first) memory block as opposed to a second memory block. Having a different number of strings with the memory block can improve the flexibility of the memory device for different functions or spare block operations (Kwon paragraph [0062], In an embodiment of the present inventive concept, the number of string selection lines included in the spare block SBK may be N (where N is a natural number of 2 or more), and the number of string selection lines included in the main block MBK may be M (where M is a natural number greater than N). Each string selection line (e.g., extending between a second separation layer MS2 and upper separation layer SS) in the main block MBK may have a length in the second direction the same as a length in the second direction of the string selection lines in the spare blocks SBK. However, because the number of string selection lines included in the spare block SBK is smaller than the number of string selection lines included in the main blocks MBK, the spare block SBK may have a shorter length than the main block MBK in the second direction, and the main block MBK and/or peripheral circuits may be arranged in an extra space reserved by reducing a space occupied by the spare block SBK, to improve a degree of integration of the memory device. The main blocks MBK may be described as a first group of memory blocks, and the spare block SBK (or a plurality of spare blocks) may be described as a second group of memory blocks).
Chibvongodze in view of Yip in further view of Kwon does not teach wherein the plurality of word line drivers are included in one of the first wafer and the second wafer, and are configured on a substrate of one of the first wafer and the second wafer.
However, Sukekawa teaches wherein the plurality of word line drivers are included in one of the first wafer and the second wafer, and are configured on a substrate of one of the first wafer and the second wafer (Sukekawa paragraph [0004], A potential application for wafer-bonding technology pertains to the fabrication of memory. In some applications, one of the bonded wafers may comprise a memory array having conventional memory circuitry (e.g., wordlines, bitlines, etc.), and another of the bonded wafers may comprise conventional peripheral circuitry (i.e., circuitry utilized in conjunction with the memory array, but typically provided peripheral to the memory array; such as, for example, wordline-driver circuitry, sense-amplifier circuitry, input circuitry, output circuitry, etc.). The problematic misalignment encountered during wafer-bonding technology may render it difficult to couple the memory circuitry along one of the bonded wafers with the peripheral circuitry along another of the bonded wafers. It would be desirable to develop methodologies suitable for enabling coupling of the memory circuitry from a first wafer with the peripheral circuitry provided by a second wafer bonded to the first wafer. A second wafer may contain peripheral circuitry, such as a wordline driver, which can also include being mounted on a substrate, such as described in Sukekawa paragraph [0029], The semiconductor wafer 10 may comprise any suitable semiconductor material; and may, for example, comprise monocrystalline silicon. The semiconductor wafer 10 may be referred to as a semiconductor substrate. The term “semiconductor substrate” means any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductor substrates described above. In the illustrated embodiment, the wafer 10 corresponds to a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, etc. Wherein the peripheral circuit components are described as being part of the semiconductor substrate, also see Sukekawa paragraphs [0031-0032]).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Chibvongodze and Yip and Kwon with those of Sukekawa. Sukekawa teaches using a particular semiconductor wafer for storing peripheral circuitry such as wordline drivers, which can allow for more efficient and effective wafer bonding (i.e., see Sukekawa paragraphs [0003-0004], Problems may be encountered during the bonding of the wafers which may lead to misalignment of the wafers relative to one another. Substantial effort has been directed toward compensating for potential alignment errors occurring during lithographic (e.g., photolithographic) processes. However, the alignment errors incurred during wafer-bonding may be significantly larger than the alignment errors incurred during lithographic processes. Accordingly, it is desirable to develop methodologies tailored for compensating for the relatively large misalignments which may occur during wafer-bonding. A potential application for wafer-bonding technology pertains to the fabrication of memory. In some applications, one of the bonded wafers may comprise a memory array having conventional memory circuitry (e.g., wordlines, bitlines, etc.), and another of the bonded wafers may comprise conventional peripheral circuitry (i.e., circuitry utilized in conjunction with the memory array, but typically provided peripheral to the memory array; such as, for example, wordline-driver circuitry, sense-amplifier circuitry, input circuitry, output circuitry, etc.). The problematic misalignment encountered during wafer-bonding technology may render it difficult to couple the memory circuitry along one of the bonded wafers with the peripheral circuitry along another of the bonded wafers. It would be desirable to develop methodologies suitable for enabling coupling of the memory circuitry from a first wafer with the peripheral circuitry provided by a second wafer bonded to the first wafer).
Regarding claim 5, Chibvongodze in view of Yip in further view of Kwon in further view of Sukekawa teaches The memory device according to claim 1, wherein the third memory block vertically overlaps the first memory block and the second memory block (Yip paragraph [0013], A memory sub-system can include high density non-volatile memory devices where retention of data is desired when no power is supplied to the memory device. For example, NAND memory, such as 3D flash NAND memory, offers storage in the form of compact, high density configurations. A non-volatile memory device is a package of one or more die, each including one or more planes. For some types of non-volatile memory devices (e.g., NAND memory), each plane includes of a set of physical blocks. Each block includes of a set of pages. Each page includes a set of memory cells (“cells”). A cell is an electronic circuit that stores information. A data block hereinafter refers to a unit of the memory device used to store data and can include a group of memory cells, a word line group, a word line, or individual memory cells. Each data block can include a number of sub-blocks, where each sub-block is defined by a set of associated pillars (e.g., vertical conductive traces) extending from a shared bit line. Each memory block can have a different word line count resulting in a difference storage capacity and cell count, and can be vertically overlapped, see Yip paragraph [0033], In one embodiment, memory device 130 includes memory array 137 and vertical string driver (VSD) circuit 139. Memory array 137 can include a number of layers of memory cells, each arranged in a two-dimensional grid. Each layer can include columns, also referred to as bit lines (BLs), and rows, also referred to as word lines (WLs). Each word line can refer to one or more rows of memory cells of a memory device that are used with one or more bit lines to generate the address of each of the memory cells. The intersection of a bit line and a word line constitutes the address of the memory cell. In one embodiment, memory array 137 can include multiple layers stacked vertically on top of one other to form a three-dimensional memory array. A block refers to a unit of the memory device 130 used to store data and can include a group of memory cells, a word line group, a word line, or individual memory cells. One or more blocks can be grouped together to form a plane of the memory device 130 in order to allow concurrent operations to take place on each plane).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Chibvongodze with those of Yip and Kwon and Sukekawa. Yip teaches a particular block structure utilizing overlapping vertical blocks, which can improve the coupling and operation processes based on the particular alignment (Yip paragraph [0034], In one embodiment, one or more string driver circuits, such as vertical string driver circuit 139, are disposed above memory array 137. In one embodiment, memory device includes a substrate (illustrated in FIG. 2), with the memory array 137 being disposed above the substrate, and the vertical string driver circuit 139 being disposed above the memory array 137 (i.e., on the opposite side of the memory array 137 from the substrate, such that the memory array 137 is positioned between the substrate and the vertical string driver circuit 139.) In one embodiment each of the word lines in the memory array 137 can be coupled to one or more respective access vertical string driver circuits 139. The vertical string driver circuits 139 can be configured to condition a page of a respective block of memory array 137 for a memory access operation, such as programming data (i.e., writing data), reading data, or erasing data. Each of the vertical string driver circuits 139 can be coupled to a respective global access line. Each of the global access lines can be selectively coupled to respective local access lines within a block during a memory access operation associated with a page within the block. The vertical string driver circuits 139 can be controlled based on signals from local media controller 135. Each of the vertical string driver circuits 139 can include or be coupled to a respective power circuit, and can provide voltages to respective word lines of the memory array 137 based on voltages provided by the respective power circuit. The voltages provided by the power circuits can be based on signals received from local media controller 135 and can vary depending on the memory access operation being performed. Further details with regard to the design, position, and operation of the vertical string driver circuits 139 are described below).
Regarding claim 7, Chibvongodze in view of Yip in further view of Kwon in further view of Sukekawa teaches The memory device according to claim 1, wherein the third memory block is programmed, read, and erased independent of the first memory block and the second memory block (Chibvongodze paragraph [0135], FIG. 12 is a flowchart of one embodiment of a process 1200 of parallel programming in an integrated memory module. The process 1200 may be used to program a first set of memory cells on the first memory die 102a in parallel with a second set of memory cells on the second memory 102b. Process 1200 may use any of the internal signal paths described herein in order to transfer signals (e.g., voltages, currents) between dies 102(a), 102(b), 104, but is not limited to the examples described herein. In some embodiments, even though memory cells on the first memory die 102a are programmed in parallel with memory cells on the second memory die 102b, the control die 104 may erase the memory cells on the first memory die 102a independent of the memory cells on the second memory die 102b. Each memory die/block can function independently and be managed for I/O operations such as programming and reading without input or connection to the other blocks/dies).
Regarding claim 8, Chibvongodze in view of Yip in further view of Kwon in further view of Sukekawa teaches The memory device according to claim 1, wherein the first wafer and the second wafer are bonded to each other (Chibvongodze paragraph [0049], The semiconductor wafers 135 may start as an ingot of monocrystalline silicon grown according to either a CZ, FZ or other process. The semiconductor wafers 135 may be cut and polished on major surfaces to provide smooth surfaces. The integrated circuits 103, 105a, 105b may be formed on and/or in the major surfaces. The dicing of the wafers 135 into semiconductor dies may occur before or after bonding. In one embodiment, the three wafers 135a, 135b, 135c are bonded together. After bonding the three wafers together, dicing is performed. Therefore, numerous integrated memory modules 100 may be formed from the three wafers 135. In another embodiment, the three wafers 135a, 135b, 135c are diced into semiconductor dies 104, 102a, 102b. Then, one of each of the semiconductor dies 104, 102a, 102b are bonded together to form an integrated memory module 100. Regardless of whether dicing occurs prior to or after bonding, it may be stated that the integrated memory module 100 contains a control semiconductor die 104, a first memory semiconductor die 102a, and a second memory semiconductor die 102b bonded together. The first and second wafers are bonded together, as shown in Figures 1B-1D).
Regarding claim 9, Chibvongodze in view of Yip in further view of Kwon in further view of Sukekawa teaches The memory device according to claim 1, wherein word lines of the third memory block that share word line drivers with the first memory block are stacked over word lines of the third memory block that share word line drivers with the second memory block (Yip paragraph [0013], A memory sub-system can include high density non-volatile memory devices where retention of data is desired when no power is supplied to the memory device. For example, NAND memory, such as 3D flash NAND memory, offers storage in the form of compact, high density configurations. A non-volatile memory device is a package of one or more die, each including one or more planes. For some types of non-volatile memory devices (e.g., NAND memory), each plane includes of a set of physical blocks. Each block includes of a set of pages. Each page includes a set of memory cells (“cells”). A cell is an electronic circuit that stores information. A data block hereinafter refers to a unit of the memory device used to store data and can include a group of memory cells, a word line group, a word line, or individual memory cells. Each data block can include a number of sub-blocks, where each sub-block is defined by a set of associated pillars (e.g., vertical conductive traces) extending from a shared bit line. Memory pages (also referred to herein as “pages”) store one or more bits of binary data corresponding to data received from the host system. To achieve high density, a string of memory cells in a non-volatile memory device can be constructed to include a number of memory cells at least partially surrounding a pillar of channel material. The memory cells can be coupled to access lines, which are commonly referred to as “word lines,” often fabricated in common with the memory cells, so as to form an array of strings in a block of memory. The compact nature of certain non-volatile memory devices, such as 3D flash NAND memory, means word lines are common to many memory cells within a block of memory. The plurality of memory blocks utilizes a shared and overlapping 'word line' structure, also see Yip paragraph [0041], In one embodiment, each respective control gate 350 is connected to a separate word line (i.e., access line), such that each device or memory cell can be separately controlled. The string 300 can be one of multiple strings of memory cells in a block of memory cells in memory device 130. For example, when multiple strings of memory cells are present, each memory cell 312 in string 300 may be connected to a corresponding shared word line, to which a corresponding memory cell in each of the multiple strings is also connected).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Chibvongodze with those of Yip and Kwon and Sukekawa. Yip teaches a plurality of blocks utilizing a shared word line driver, with a large block sharing with at least two small blocks. Yip teaches a flexible quantity of word lines and bit lines, resulting in flexible storage capacity for the memory blocks, while also using a shared vertical word line driver, which can improve memory function and area utilization in the memory devices (Yip paragraph [0016], Advantages of the present disclosure include, but are not limited to, improved area utilization in the memory device. With the vertical string driver circuits being positioned above the memory array, the area under the array on the substrate that would have been occupied by those drivers is available for other circuitry. In addition, as there is a decreased need for vias or other electrical connections to run through the memory array, the storage capacity is increased. Furthermore, when the semiconductor devices of the vertical string driver circuits are formed in a common layer with the select gate devices of the memory strings, the processing costs are greatly reduced, since both sets of devices can be NMOS devices, and fabricated using fewer processing steps/layers).
Claim(s) 2-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chibvongodze in view of Yip in further view of Kwon in further view of Sukekawa as applied to claim 1 above, and further in view of Cernea et al. (US Publication No. 2013/0339571 -- "Cernea").
Regarding claim 2, Chibvongodze in view of Yip in further view of Kwon and Sukekawa further in view of Cernea teaches The memory device according to claim 1, wherein the word line drivers vertically overlap the first and second memory blocks (Cernea paragraph [0220], In one 3D architecture shown in FIG. 8, the global bit lines GBLs are at the bottom of the memory layer and therefore are formed as one of these metal layers, such as metal layer-1 or metal layer-2. The vertical switch layer 1 then contains the LBL to GBL switches connecting the GBLs to the vertical local bit lines in the memory layer. Access to the word line are via the top metal layer from the top side the memory layer and therefore the word line drivers are implemented in the vertical switch layer 2 connecting each word line to a metal pad at top metal layer. Cernea teaches a vertical alignment for the word line drivers).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Chibvongodze and Yip and Kwon and Sukekawa with those of Cernea. Cernea teaches a structure with the word line driver components vertically overlapping and configuring with other components. This vertical configuration allows for more diverse access lines and greater flexibility with the overall 3D structure (Cernea paragraph [0186], The word line driver 350 can then switch between an exposed word line segment and a word line power source (not shown). The word line driver can have a width as wide as the segment of a word line. FIG. 18 shows two adjacent word line drivers 350-Even and 350-Odd, respectively switching two adjacent segments 312-Even and 312-Odd from two adjacent word lines across the y-direction. It will be seen that the even WL access line 355-Even along the y-direction accesses the even banks of word lines along the y-direction. Similarly, the odd WL access line 355-Odd along the y-direction accesses the odd banks of word lines along the y-direction. Each of these access lines only access alternate word line segment because these segments are not isolated by an oxide layer 404).
Regarding claim 3, Chibvongodze in view of Yip in further view of Kwon and Sukekawa further in view of Cernea teaches The memory device according to claim 1, wherein the word line drivers vertically overlap the third memory block (Cernea paragraph [0220], In one 3D architecture shown in FIG. 8, the global bit lines GBLs are at the bottom of the memory layer and therefore are formed as one of these metal layers, such as metal layer-1 or metal layer-2. The vertical switch layer 1 then contains the LBL to GBL switches connecting the GBLs to the vertical local bit lines in the memory layer. Access to the word line are via the top metal layer from the top side the memory layer and therefore the word line drivers are implemented in the vertical switch layer 2 connecting each word line to a metal pad at top metal layer. Cernea teaches a vertical alignment for the word line drivers).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Chibvongodze and Yip and Kwon and Sukekawa with those of Cernea. Cernea teaches a structure with the word line driver components vertically overlapping and configuring with other components. This vertical configuration allows for more diverse access lines and greater flexibility with the overall 3D structure (Cernea paragraph [0186], The word line driver 350 can then switch between an exposed word line segment and a word line power source (not shown). The word line driver can have a width as wide as the segment of a word line. FIG. 18 shows two adjacent word line drivers 350-Even and 350-Odd, respectively switching two adjacent segments 312-Even and 312-Odd from two adjacent word lines across the y-direction. It will be seen that the even WL access line 355-Even along the y-direction accesses the even banks of word lines along the y-direction. Similarly, the odd WL access line 355-Odd along the y-direction accesses the odd banks of word lines along the y-direction. Each of these access lines only access alternate word line segment because these segments are not isolated by an oxide layer 404).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chibvongodze in view of Yip in further view of Kwon in further view of Sukekawa as applied to claim 1 above, and further in view of Kim et al. (US Publication No. 2023/0126807 -- "Kim").
Regarding claim 4, Chibvongodze in view of Yip in further view of Kwon in further view of Sukekawa and further in view of Kim teaches The memory device according to claim 1, wherein the first wafer further includes a first bit line that is coupled to the first and second memory blocks, the second wafer further includes a second bit line that is coupled to the third memory block, (Chibvongodze paragraph [0143-0144], Step 1304 includes sensing bit lines in the first memory die 102a using a first set of sense amplifiers 250 on the control die 104. Step 1304 includes sensing bit lines of a first selected block in the first memory die 102(a) through the bond pads 270b, in one embodiment. Step 1304 includes sensing bit lines of the first selected block in the first memory die 102(a) through the bond pads 274b, in one embodiment. Step 1304 includes sensing bit lines of the first selected block in the first memory die 102(a) through bond pads 270b and bond pads 274b, in one embodiment. Step 1306 includes sensing bit lines in the second memory die 102b using a second set of sense amplifiers 250 on the control die 104. Step 1306 includes sensing bit lines of a second selected block in the second memory die 102(b) through the bond pads 272b, in one embodiment. Step 1306 includes sensing bit lines of the second selected block in the second memory die 102(b) through the bond pads 276b, in one embodiment. Step 1306 includes sensing bit lines of the second selected block in the second memory die 102(b) through bond pads 272b and bond pads 276b, in one embodiment. A first- and second-bit line may be used to connect between a plurality of memory blocks, each of which may correspond to a wafer) and the first bit line and the second bit line are coupled in common to one page buffer (Kim paragraph [0049], The memory cell array 330 may be connected to the page buffer 340 through bit lines BL, and may be connected to the row decoder 360 through word lines WL, string selection lines SSL, and ground selection lines GSL. A plurality of bit lines (i.e., first and second), may be connected to a singular page buffer, also see Kim paragraph [0051], The page buffer 340 may include a plurality of page buffers PB1 to PBn (n is an integer of 3 or more), and the plurality of page buffers PB1 to PBn may be connected to the memory cells through a plurality of bit lines BL, respectively. The page buffer 340 may select at least one of the bit lines BL in response to the column address Y-ADDR. The page buffer 340 may operate as a write driver or a sense amplifier according to an operation mode. For example, at the time of a programming operation, the page buffer 340 may apply a bit line voltage corresponding to data to be programmed to the selected bit line. At the time of a read operation, the page buffer 340 may sense a current or a voltage of the selected bit line to sense data stored in the memory cell).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Chibvongodze and Yip and Kwon and Sukekawa with those of Kim. Kim teaches a first and second bit line coupled to a common one page buffer, which can allow the memory system to select one of the bit lines to read the data into the page buffer, resulting in improved performance and integration for the selected bit lines (Kim paragraphs [0051], The page buffer 340 may include a plurality of page buffers PB1 to PBn (n is an integer of 3 or more), and the plurality of page buffers PB1 to PBn may be connected to the memory cells through a plurality of bit lines BL, respectively. The page buffer 340 may select at least one of the bit lines BL in response to the column address Y-ADDR. The page buffer 340 may operate as a write driver or a sense amplifier according to an operation mode. For example, at the time of a programming operation, the page buffer 340 may apply a bit line voltage corresponding to data to be programmed to the selected bit line. At the time of a read operation, the page buffer 340 may sense a current or a voltage of the selected bit line to sense data stored in the memory cell).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chibvongodze in view of Yip in further view of Kwon in further view of Sukekawa as applied to claim 1 above, and further in view of Park et al. (US Patent No. 5,999,463 -- "Park").
Regarding claim 6, Chibvongodze in view of Yip in further view of Kwon in further view of Sukekawa and further in view of Park teaches The memory device according to claim 1, wherein the third memory block does not share a select line driver with the first memory block and does not share a select line driver with the second memory block (Park column 7; line 63-column 8; line 15, As described above, all of the normal column selection line drivers 409 and 411 include the fuse, and the redundant column selection line drivers 405 and 407 may all not include the fuse. Accordingly, when a defective memory cell exists in one memory block of the two memory blocks 401 and 403, the redundant column selection line drivers are all activated. That is, since the two redundant column selection line drivers 405 and 407 both do not include a fuse, when a column address CA that is the same as the repair address is input to the column redundancy fuse box 413, the redundant column selection lines RCSL0 and RCSL1 output by the two redundant column selection line drivers 405 and 407 are all activated. Therefore, when a defective memory cell exists in both of the two memory blocks 401 and 403 or even if a defective memory cell exists in only one of the two memory blocks, it is replaced by a redundant memory cell simultaneously. The memory blocks can have different select line drivers depending upon the configuration and addresses input into the system).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Chibvongodze and Yip and Kwon and Sukekawa with those of Park. Park teaches a plurality of memory blocks which can utilize different select line drivers based on a variety of factors, which can reduce overall processing consumption and improve address reliability (Park column 2; lines 7-28, These and other objects are provided according to the present invention, by commonly storing addresses of defective memory cells of a plurality of memory blocks in a shared redundancy address storing unit, also referred herein as a column redundancy fuse box. Redundant selection line drivers such as redundant column selection line drivers, that are associated with the memory block having the defective memory cells are selectively activated, in response to receipt of an address of a defective memory cell by the shared redundancy address storage unit. A normal selection line driver that is associated with the memory block having defective memory cells is also selectively deactivated in response to receipt of an address of a defective memory cell by the shared redundancy address storing unit. Thus, the address of a defective row or column is commonly stored, and then the appropriate block driver is selectively activated or deactivated. The multibit address storage maybe commonly shared, and a single bit can be used to selectively activate or deactivate the appropriate blocks. Thus, the area of fuse boxes and the current consumption thereof can be reduced).
Claim(s) 10, 12-13 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chibvongodze in view of Kwon in further view of Kim and further in view of Sukekawa.
Regarding claim 10, Chibvongodze teaches A memory device comprising: a first wafer and including a plurality of small blocks; and a second wafer, arranged in a vertical direction with respect to the first wafer, (Chibvongodze paragraph [0039], In one embodiment, memory structure 126 comprises a three-dimensional memory array of non-volatile memory cells in which multiple memory levels are formed above a single substrate, such as a wafer. The memory structure may comprise any type of non-volatile memory that are monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon (or other type of) substrate. In one example, the non-volatile memory cells comprise vertical NAND strings with charge-trapping material. The plurality of semiconductor wafers contains flash NAND memory consisting of a plurality of memory blocks as well as word line and strings, which can be arranged in a vertical configuration) a stack number of vertically stacked word lines (Chibvongodze Fig. 4; Chibvongodze paragraph [0096], FIG. 4 is a perspective view of a portion of one example embodiment of a monolithic three dimensional memory array that can comprise memory structure 126, which includes a plurality non-volatile memory cells. For example, FIG. 4 shows a portion of one block comprising memory. The structure depicted includes a set of bit lines BL positioned above a stack of alternating dielectric layers and conductive layers with vertical columns of materials extending through the dielectric layers and conductive layers. For example purposes, one of the dielectric layers is marked as D and one of the conductive layers (also called word line layers) is marked as W. The wordlines comprised in the block may be stacked in the vertical direction).
Chibvongodze does not teach a first wafer configured to store hot data, and a second wafer, configured to store cold data, including a plurality of large blocks in which a stack number of vertically stacked word lines and a number of strings of a large block are larger than a stack number of vertically stacked word lines and a number of strings of a small block; wherein a plurality of word line drivers are included in one of the first wafer and the second wafer, and are configured on a substrate of one of the first wafer and the second wafer.
However, Kwon teaches including a plurality of large blocks in which a stack number of word lines and a number of strings of a large block are larger than a stack number of word lines and a number of strings of a small block (Kwon claim 2, The memory device of claim 1, wherein at least some of the gate electrode layers comprise string selection lines, such that at least one string selection line is included in each of the memory blocks, wherein the number of the string selection lines included in each of the main blocks is greater than the number of the string selection lines included in the first spare block. The number of strings of the first memory block is larger than the corresponding number of strings in the secondary memory blocks, also see Kwon paragraph [0007], The gate electrode layers in each of the memory blocks provide at least one ground selection line, a plurality of word lines, and a plurality of string selection lines, wherein the string selection lines are separated from each other in a second direction, intersecting the first direction and parallel to the upper surface of the substrate. The numbers of the string selection lines included in each memory block of a first group of the memory blocks are different from the number of the string selection lines included in each memory block of a second group of the memory blocks).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Chibvongodze with those of Kwon. Kwon teaches having a different number of strings in a primary (i.e., first) memory block as opposed to a second memory block. Having a different number of strings with the memory block can improve the flexibility of the memory device for different functions or spare block operations (Kwon paragraph [0062], In an embodiment of the present inventive concept, the number of string selection lines included in the spare block SBK may be N (where N is a natural number of 2 or more), and the number of string selection lines included in the main block MBK may be M (where M is a natural number greater than N). Each string selection line (e.g., extending between a second separation layer MS2 and upper separation layer SS) in the main block MBK may have a length in the second direction the same as a length in the second direction of the string selection lines in the spare blocks SBK. However, because the number of string selection lines included in the spare block SBK is smaller than the number of string selection lines included in the main blocks MBK, the spare block SBK may have a shorter length than the main block MBK in the second direction, and the main block MBK and/or peripheral circuits may be arranged in an extra space reserved by reducing a space occupied by the spare block SBK, to improve a degree of integration of the memory device. The main blocks MBK may be described as a first group of memory blocks, and the spare block SBK (or a plurality of spare blocks) may be described as a second group of memory blocks).
Chibvongodze in view of Kwon does not teach a first wafer configured to store hot data, and a second wafer, configured to store cold data; wherein a plurality of word line drivers are included in one of the first wafer and the second wafer, and are configured on a substrate of one of the first wafer and the second wafer.
However, Kim teaches a first wafer configured to store hot data, and a second wafer, configured to store cold data (Kim paragraph [0028], When the non-volatile memory 220 of the storage device 200 includes a flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, the storage device 200 may include various other types of non-volatile memories. For example, the storage device 200 may include a magnetic random access memory (MRAM), a Spin-Transfer Torque MRAM, a conductive bridging RAM (CBRAM), a ferroelectric RAM (FeRAM), a phase RAM (PRAM), a resistive RAM, and various other types of memories. The semiconductor may be a NAND vertical memory structure (also see Kim paragraph [0050]) that distinguishes data based on hot/cold classifications, see Kim paragraph [0086], The allocator 231 may allocate data to the memory regions based on the hotness information of the logical address. For example, the allocator 231 may determine data corresponding to the logical address as hot data when the hotness of the logical address exceeds a first threshold value, determine data corresponding to the logical address as warm data when the hotness of the logical address is equal to or less than the first threshold value and exceeds a second threshold value, and determine data corresponding to the logical address as cold data when the hotness of the logical address is equal to or less than the second threshold value. The allocator 231 may store the hot data in the first memory region, the warm data in the second memory region, and store the cold data in the third memory region).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Chibvongodze and Kwon with those of Kim. Kim teaches classifying the data based on different hot/cold determinations, which can allow for more efficient memory utilization and organization (Kim paragraph [0042], When data having different attributes may be divided and stored in the memory blocks having the different attributes, the non-volatile memory 220 may be efficiently used. For example, when the hot data, the frequently accessed data, is stored in the first memory blocks, an access speed of the hot data may be improved, and average performance of the storage device 200 may be improved. When the cold data, the relatively infrequently accessed data, is stored in the third memory blocks, the data stored in the third memory block may be infrequently updated, and a decrease in lifespan of the third memory blocks may be alleviated).
Chibvongodze in view of Kwon in further view of Kim does not teach wherein a plurality of word line drivers are included in one of the first wafer and the second wafer, and are configured on a substrate of one of the first wafer and the second wafer.
However, Sukekawa teaches wherein a plurality of word line drivers are included in one of the first wafer and the second wafer, and are configured on a substrate of one of the first wafer and the second wafer (Sukekawa paragraph [0004], A potential application for wafer-bonding technology pertains to the fabrication of memory. In some applications, one of the bonded wafers may comprise a memory array having conventional memory circuitry (e.g., wordlines, bitlines, etc.), and another of the bonded wafers may comprise conventional peripheral circuitry (i.e., circuitry utilized in conjunction with the memory array, but typically provided peripheral to the memory array; such as, for example, wordline-driver circuitry, sense-amplifier circuitry, input circuitry, output circuitry, etc.). The problematic misalignment encountered during wafer-bonding technology may render it difficult to couple the memory circuitry along one of the bonded wafers with the peripheral circuitry along another of the bonded wafers. It would be desirable to develop methodologies suitable for enabling coupling of the memory circuitry from a first wafer with the peripheral circuitry provided by a second wafer bonded to the first wafer. A second wafer may contain peripheral circuitry, such as a wordline driver, which can also include being mounted on a substrate, such as described in Sukekawa paragraph [0029], The semiconductor wafer 10 may comprise any suitable semiconductor material; and may, for example, comprise monocrystalline silicon. The semiconductor wafer 10 may be referred to as a semiconductor substrate. The term “semiconductor substrate” means any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductor substrates described above. In the illustrated embodiment, the wafer 10 corresponds to a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, etc. Wherein the peripheral circuit components are described as being part of the semiconductor substrate, also see Sukekawa paragraphs [0031-0032]).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Chibvongodze and Yip and Kwon with those of Sukekawa. Sukekawa teaches using a particular semiconductor wafer for storing peripheral circuitry such as wordline drivers, which can allow for more efficient and effective wafer bonding (i.e., see Sukekawa paragraphs [0003-0004], Problems may be encountered during the bonding of the wafers which may lead to misalignment of the wafers relative to one another. Substantial effort has been directed toward compensating for potential alignment errors occurring during lithographic (e.g., photolithographic) processes. However, the alignment errors incurred during wafer-bonding may be significantly larger than the alignment errors incurred during lithographic processes. Accordingly, it is desirable to develop methodologies tailored for compensating for the relatively large misalignments which may occur during wafer-bonding. A potential application for wafer-bonding technology pertains to the fabrication of memory. In some applications, one of the bonded wafers may comprise a memory array having conventional memory circuitry (e.g., wordlines, bitlines, etc.), and another of the bonded wafers may comprise conventional peripheral circuitry (i.e., circuitry utilized in conjunction with the memory array, but typically provided peripheral to the memory array; such as, for example, wordline-driver circuitry, sense-amplifier circuitry, input circuitry, output circuitry, etc.). The problematic misalignment encountered during wafer-bonding technology may render it difficult to couple the memory circuitry along one of the bonded wafers with the peripheral circuitry along another of the bonded wafers. It would be desirable to develop methodologies suitable for enabling coupling of the memory circuitry from a first wafer with the peripheral circuitry provided by a second wafer bonded to the first wafer).
Regarding claim 12, Chibvongodze in view of Kwon in further view of Kim and further in view of Sukekawa teaches The memory device according to claim 10, wherein the first wafer and the second wafer are bonded to each other (Chibvongodze paragraph [0049], The semiconductor wafers 135 may start as an ingot of monocrystalline silicon grown according to either a CZ, FZ or other process. The semiconductor wafers 135 may be cut and polished on major surfaces to provide smooth surfaces. The integrated circuits 103, 105a, 105b may be formed on and/or in the major surfaces. The dicing of the wafers 135 into semiconductor dies may occur before or after bonding. In one embodiment, the three wafers 135a, 135b, 135c are bonded together. After bonding the three wafers together, dicing is performed. Therefore, numerous integrated memory modules 100 may be formed from the three wafers 135. In another embodiment, the three wafers 135a, 135b, 135c are diced into semiconductor dies 104, 102a, 102b. Then, one of each of the semiconductor dies 104, 102a, 102b are bonded together to form an integrated memory module 100. Regardless of whether dicing occurs prior to or after bonding, it may be stated that the integrated memory module 100 contains a control semiconductor die 104, a first memory semiconductor die 102a, and a second memory semiconductor die 102b bonded together. The first and second wafers are bonded together, as shown in Figures 1B-1D).
Regarding claim 13, Chibvongodze teaches A memory system comprising: a memory device including a first wafer including a plurality of small blocks and a second wafer disposed vertically with respect to the first wafer (Chibvongodze paragraph [0039], In one embodiment, memory structure 126 comprises a three-dimensional memory array of non-volatile memory cells in which multiple memory levels are formed above a single substrate, such as a wafer. The memory structure may comprise any type of non-volatile memory that are monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon (or other type of) substrate. In one example, the non-volatile memory cells comprise vertical NAND strings with charge-trapping material. The plurality of semiconductor wafers contain flash NAND memory consisting of a plurality of memory blocks as well as word line and strings, which can be arranged in a vertical configuration) a stack number of vertically stacked word lines (Chibvongodze Fig. 4; Chibvongodze paragraph [0096], FIG. 4 is a perspective view of a portion of one example embodiment of a monolithic three dimensional memory array that can comprise memory structure 126, which includes a plurality non-volatile memory cells. For example, FIG. 4 shows a portion of one block comprising memory. The structure depicted includes a set of bit lines BL positioned above a stack of alternating dielectric layers and conductive layers with vertical columns of materials extending through the dielectric layers and conductive layers. For example purposes, one of the dielectric layers is marked as D and one of the conductive layers (also called word line layers) is marked as W. The wordlines comprised in the block may be stacked in the vertical direction).
Chibvongodze does not teach including a plurality of large blocks in which a stack number of vertically stacked word lines and a number of strings of a large block are larger than a stack number of vertically stacked word lines and a number of strings of a small block; and a controller configured to store hot data, of data received from a host, in the first wafer and to store cold data, of data received from a host, in the second wafer; wherein a plurality of word line drivers are included in one of the first wafer and the second wafer, and are configured on a substrate of one of the first wafer and the second wafer.
However, Kwon teaches including a plurality of large blocks in which a stack number of word lines and a number of strings of a large block are larger than a stack number of word lines and a number of strings of a small block; (Kwon claim 2, The memory device of claim 1, wherein at least some of the gate electrode layers comprise string selection lines, such that at least one string selection line is included in each of the memory blocks, wherein the number of the string selection lines included in each of the main blocks is greater than the number of the string selection lines included in the first spare block. The number of strings of the first memory block is larger than the corresponding number of strings in the secondary memory blocks, also see Kwon paragraph [0007], The gate electrode layers in each of the memory blocks provide at least one ground selection line, a plurality of word lines, and a plurality of string selection lines, wherein the string selection lines are separated from each other in a second direction, intersecting the first direction and parallel to the upper surface of the substrate. The numbers of the string selection lines included in each memory block of a first group of the memory blocks are different from the number of the string selection lines included in each memory block of a second group of the memory blocks).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Chibvongodze with those of Kwon. Kwon teaches having a different number of strings in a primary (i.e., first) memory block as opposed to a second memory block. Having a different number of strings with the memory block can improve the flexibility of the memory device for different functions or spare block operations (Kwon paragraph [0062], In an embodiment of the present inventive concept, the number of string selection lines included in the spare block SBK may be N (where N is a natural number of 2 or more), and the number of string selection lines included in the main block MBK may be M (where M is a natural number greater than N). Each string selection line (e.g., extending between a second separation layer MS2 and upper separation layer SS) in the main block MBK may have a length in the second direction the same as a length in the second direction of the string selection lines in the spare blocks SBK. However, because the number of string selection lines included in the spare block SBK is smaller than the number of string selection lines included in the main blocks MBK, the spare block SBK may have a shorter length than the main block MBK in the second direction, and the main block MBK and/or peripheral circuits may be arranged in an extra space reserved by reducing a space occupied by the spare block SBK, to improve a degree of integration of the memory device. The main blocks MBK may be described as a first group of memory blocks, and the spare block SBK (or a plurality of spare blocks) may be described as a second group of memory blocks).
Chibvongodze in view of Kwon does not teach a controller configured to store hot data, of data received from a host, in the first wafer and to store cold data, of data received from a host, in the second wafer; wherein a plurality of word line drivers are included in one of the first wafer and the second wafer, and are configured on a substrate of one of the first wafer and the second wafer.
However, Kim teaches a controller configured to store hot data, of data received from a host, in the first wafer and to store cold data, of data received from a host, in the second wafer (Kim paragraph [0028], When the non-volatile memory 220 of the storage device 200 includes a flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, the storage device 200 may include various other types of non-volatile memories. For example, the storage device 200 may include a magnetic random access memory (MRAM), a Spin-Transfer Torque MRAM, a conductive bridging RAM (CBRAM), a ferroelectric RAM (FeRAM), a phase RAM (PRAM), a resistive RAM, and various other types of memories. The semiconductor may be a NAND vertical memory structure (also see Kim paragraph [0050]) that distinguishes data based on hot/cold classifications, see Kim paragraph [0086], The allocator 231 may allocate data to the memory regions based on the hotness information of the logical address. For example, the allocator 231 may determine data corresponding to the logical address as hot data when the hotness of the logical address exceeds a first threshold value, determine data corresponding to the logical address as warm data when the hotness of the logical address is equal to or less than the first threshold value and exceeds a second threshold value, and determine data corresponding to the logical address as cold data when the hotness of the logical address is equal to or less than the second threshold value. The allocator 231 may store the hot data in the first memory region, the warm data in the second memory region, and store the cold data in the third memory region).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Chibvongodze and Kwon with those of Kim. Kim teaches classifying the data based on different hot/cold determinations, which can allow for more efficient memory utilization and organization (Kim paragraph [0042], When data having different attributes may be divided and stored in the memory blocks having the different attributes, the non-volatile memory 220 may be efficiently used. For example, when the hot data, the frequently accessed data, is stored in the first memory blocks, an access speed of the hot data may be improved, and average performance of the storage device 200 may be improved. When the cold data, the relatively infrequently accessed data, is stored in the third memory blocks, the data stored in the third memory block may be infrequently updated, and a decrease in lifespan of the third memory blocks may be alleviated).
Chibvongodze in view of Kwon in further view of Kim does not teach wherein a plurality of word line drivers are included in one of the first wafer and the second wafer, and are configured on a substrate of one of the first wafer and the second wafer.
However, Sukekawa teaches wherein a plurality of word line drivers are included in one of the first wafer and the second wafer, and are configured on a substrate of one of the first wafer and the second wafer (Sukekawa paragraph [0004], A potential application for wafer-bonding technology pertains to the fabrication of memory. In some applications, one of the bonded wafers may comprise a memory array having conventional memory circuitry (e.g., wordlines, bitlines, etc.), and another of the bonded wafers may comprise conventional peripheral circuitry (i.e., circuitry utilized in conjunction with the memory array, but typically provided peripheral to the memory array; such as, for example, wordline-driver circuitry, sense-amplifier circuitry, input circuitry, output circuitry, etc.). The problematic misalignment encountered during wafer-bonding technology may render it difficult to couple the memory circuitry along one of the bonded wafers with the peripheral circuitry along another of the bonded wafers. It would be desirable to develop methodologies suitable for enabling coupling of the memory circuitry from a first wafer with the peripheral circuitry provided by a second wafer bonded to the first wafer. A second wafer may contain peripheral circuitry, such as a wordline driver, which can also include being mounted on a substrate, such as described in Sukekawa paragraph [0029], The semiconductor wafer 10 may comprise any suitable semiconductor material; and may, for example, comprise monocrystalline silicon. The semiconductor wafer 10 may be referred to as a semiconductor substrate. The term “semiconductor substrate” means any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductor substrates described above. In the illustrated embodiment, the wafer 10 corresponds to a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, etc. Wherein the peripheral circuit components are described as being part of the semiconductor substrate, also see Sukekawa paragraphs [0031-0032]).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Chibvongodze and Yip and Kwon with those of Sukekawa. Sukekawa teaches using a particular semiconductor wafer for storing peripheral circuitry such as wordline drivers, which can allow for more efficient and effective wafer bonding (i.e., see Sukekawa paragraphs [0003-0004], Problems may be encountered during the bonding of the wafers which may lead to misalignment of the wafers relative to one another. Substantial effort has been directed toward compensating for potential alignment errors occurring during lithographic (e.g., photolithographic) processes. However, the alignment errors incurred during wafer-bonding may be significantly larger than the alignment errors incurred during lithographic processes. Accordingly, it is desirable to develop methodologies tailored for compensating for the relatively large misalignments which may occur during wafer-bonding. A potential application for wafer-bonding technology pertains to the fabrication of memory. In some applications, one of the bonded wafers may comprise a memory array having conventional memory circuitry (e.g., wordlines, bitlines, etc.), and another of the bonded wafers may comprise conventional peripheral circuitry (i.e., circuitry utilized in conjunction with the memory array, but typically provided peripheral to the memory array; such as, for example, wordline-driver circuitry, sense-amplifier circuitry, input circuitry, output circuitry, etc.). The problematic misalignment encountered during wafer-bonding technology may render it difficult to couple the memory circuitry along one of the bonded wafers with the peripheral circuitry along another of the bonded wafers. It would be desirable to develop methodologies suitable for enabling coupling of the memory circuitry from a first wafer with the peripheral circuitry provided by a second wafer bonded to the first wafer).
Regarding claim 18, Chibvongodze in view of Kwon in further view of Kim and further in view of Sukekawa teaches The memory system according to claim 13, wherein the first wafer and the second wafer are bonded to each other (Chibvongodze paragraph [0049], The semiconductor wafers 135 may start as an ingot of monocrystalline silicon grown according to either a CZ, FZ or other process. The semiconductor wafers 135 may be cut and polished on major surfaces to provide smooth surfaces. The integrated circuits 103, 105a, 105b may be formed on and/or in the major surfaces. The dicing of the wafers 135 into semiconductor dies may occur before or after bonding. In one embodiment, the three wafers 135a, 135b, 135c are bonded together. After bonding the three wafers together, dicing is performed. Therefore, numerous integrated memory modules 100 may be formed from the three wafers 135. In another embodiment, the three wafers 135a, 135b, 135c are diced into semiconductor dies 104, 102a, 102b. Then, one of each of the semiconductor dies 104, 102a, 102b are bonded together to form an integrated memory module 100. Regardless of whether dicing occurs prior to or after bonding, it may be stated that the integrated memory module 100 contains a control semiconductor die 104, a first memory semiconductor die 102a, and a second memory semiconductor die 102b bonded together. The first and second wafers are bonded together, as shown in Figures 1B-1D).
Claim(s) 11 and 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chibvongodze in view of Kwon in further view of Kim in further view of Sukekawa as applied to claims 10 and 13 above, and further in view of Yip.
Regarding claim 11, Chibvongodze in view of Kwon in further view of Kim in further view of Sukekawa and further in view of Yip teaches The memory device according to claim 10, wherein each of the plurality of large blocks vertically overlaps at least two small blocks (Yip paragraph [0013], A memory sub-system can include high density non-volatile memory devices where retention of data is desired when no power is supplied to the memory device. For example, NAND memory, such as 3D flash NAND memory, offers storage in the form of compact, high density configurations. A non-volatile memory device is a package of one or more die, each including one or more planes. For some types of non-volatile memory devices (e.g., NAND memory), each plane includes of a set of physical blocks. Each block includes of a set of pages. Each page includes a set of memory cells (“cells”). A cell is an electronic circuit that stores information. A data block hereinafter refers to a unit of the memory device used to store data and can include a group of memory cells, a word line group, a word line, or individual memory cells. Each data block can include a number of sub-blocks, where each sub-block is defined by a set of associated pillars (e.g., vertical conductive traces) extending from a shared bit line. Each memory block can have a different word line count resulting in a difference storage capacity and cell count, and can be vertically overlapped, see Yip paragraph [0033], In one embodiment, memory device 130 includes memory array 137 and vertical string driver (VSD) circuit 139. Memory array 137 can include a number of layers of memory cells, each arranged in a two-dimensional grid. Each layer can include columns, also referred to as bit lines (BLs), and rows, also referred to as word lines (WLs). Each word line can refer to one or more rows of memory cells of a memory device that are used with one or more bit lines to generate the address of each of the memory cells. The intersection of a bit line and a word line constitutes the address of the memory cell. In one embodiment, memory array 137 can include multiple layers stacked vertically on top of one other to form a three-dimensional memory array. A block refers to a unit of the memory device 130 used to store data and can include a group of memory cells, a word line group, a word line, or individual memory cells. One or more blocks can be grouped together to form a plane of the memory device 130 in order to allow concurrent operations to take place on each plane).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Chibvongodze, Kwon, Kim and Sukekawa with those of Yip. Yip teaches a plurality of blocks utilizing a shared word line driver, with a large block sharing with at least two small blocks. Yip teaches a flexible quantity of word lines and bit lines, resulting in flexible storage capacity for the memory blocks, while also using a shared vertical word line driver, which can improve memory function and area utilization in the memory devices (Yip paragraph [0016], Advantages of the present disclosure include, but are not limited to, improved area utilization in the memory device. With the vertical string driver circuits being positioned above the memory array, the area under the array on the substrate that would have been occupied by those drivers is available for other circuitry. In addition, as there is a decreased need for vias or other electrical connections to run through the memory array, the storage capacity is increased. Furthermore, when the semiconductor devices of the vertical string driver circuits are formed in a common layer with the select gate devices of the memory strings, the processing costs are greatly reduced, since both sets of devices can be NMOS devices, and fabricated using fewer processing steps/layers).
Regarding claim 14, Chibvongodze in view of Kwon in further view of Kim in further view of Sukekawa and further in view of Yip teaches The memory system according to claim 13, wherein each of the plurality of large blocks shares word line drivers with at least two of the plurality of small blocks (Yip paragraph [0013], A memory sub-system can include high density non-volatile memory devices where retention of data is desired when no power is supplied to the memory device. For example, NAND memory, such as 3D flash NAND memory, offers storage in the form of compact, high density configurations. A non-volatile memory device is a package of one or more die, each including one or more planes. For some types of non-volatile memory devices (e.g., NAND memory), each plane includes of a set of physical blocks. Each block includes of a set of pages. Each page includes a set of memory cells (“cells”). A cell is an electronic circuit that stores information. A data block hereinafter refers to a unit of the memory device used to store data and can include a group of memory cells, a word line group, a word line, or individual memory cells. Each data block can include a number of sub-blocks, where each sub-block is defined by a set of associated pillars (e.g., vertical conductive traces) extending from a shared bit line. The various memory blocks share a word driver line, wherein each memory block can have a different word line count resulting in a difference storage capacity and cell count).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Chibvongodze, Kwon, Kim and Sukekawa with those of Yip. Yip teaches a plurality of blocks utilizing a shared word line driver, with a large block sharing with at least two small blocks. Yip teaches a flexible quantity of word lines and bit lines, resulting in flexible storage capacity for the memory blocks, while also using a shared vertical word line driver, which can improve memory function and area utilization in the memory devices (Yip paragraph [0016], Advantages of the present disclosure include, but are not limited to, improved area utilization in the memory device. With the vertical string driver circuits being positioned above the memory array, the area under the array on the substrate that would have been occupied by those drivers is available for other circuitry. In addition, as there is a decreased need for vias or other electrical connections to run through the memory array, the storage capacity is increased. Furthermore, when the semiconductor devices of the vertical string driver circuits are formed in a common layer with the select gate devices of the memory strings, the processing costs are greatly reduced, since both sets of devices can be NMOS devices, and fabricated using fewer processing steps/layers).
Regarding claim 15, Chibvongodze in view of Kwon in further view of Kim in further view of Sukekawa and further in view of Yip teaches The memory system according to claim 14, wherein the each of the plurality of large blocks vertically overlaps the at least two of the plurality of small blocks (Yip paragraph [0013], A memory sub-system can include high density non-volatile memory devices where retention of data is desired when no power is supplied to the memory device. For example, NAND memory, such as 3D flash NAND memory, offers storage in the form of compact, high density configurations. A non-volatile memory device is a package of one or more die, each including one or more planes. For some types of non-volatile memory devices (e.g., NAND memory), each plane includes of a set of physical blocks. Each block includes of a set of pages. Each page includes a set of memory cells (“cells”). A cell is an electronic circuit that stores information. A data block hereinafter refers to a unit of the memory device used to store data and can include a group of memory cells, a word line group, a word line, or individual memory cells. Each data block can include a number of sub-blocks, where each sub-block is defined by a set of associated pillars (e.g., vertical conductive traces) extending from a shared bit line. Each memory block can have a different word line count resulting in a difference storage capacity and cell count, and can be vertically overlapped, see Yip paragraph [0033], In one embodiment, memory device 130 includes memory array 137 and vertical string driver (VSD) circuit 139. Memory array 137 can include a number of layers of memory cells, each arranged in a two-dimensional grid. Each layer can include columns, also referred to as bit lines (BLs), and rows, also referred to as word lines (WLs). Each word line can refer to one or more rows of memory cells of a memory device that are used with one or more bit lines to generate the address of each of the memory cells. The intersection of a bit line and a word line constitutes the address of the memory cell. In one embodiment, memory array 137 can include multiple layers stacked vertically on top of one other to form a three-dimensional memory array. A block refers to a unit of the memory device 130 used to store data and can include a group of memory cells, a word line group, a word line, or individual memory cells. One or more blocks can be grouped together to form a plane of the memory device 130 in order to allow concurrent operations to take place on each plane).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Chibvongodze, Kwon, Kim and Sukekawa with those of Yip. Yip teaches a particular block structure utilizing overlapping vertical blocks, which can improve the coupling and operation processes based on the particular alignment (Yip paragraph [0034], In one embodiment, one or more string driver circuits, such as vertical string driver circuit 139, are disposed above memory array 137. In one embodiment, memory device includes a substrate (illustrated in FIG. 2), with the memory array 137 being disposed above the substrate, and the vertical string driver circuit 139 being disposed above the memory array 137 (i.e., on the opposite side of the memory array 137 from the substrate, such that the memory array 137 is positioned between the substrate and the vertical string driver circuit 139.) In one embodiment each of the word lines in the memory array 137 can be coupled to one or more respective access vertical string driver circuits 139. The vertical string driver circuits 139 can be configured to condition a page of a respective block of memory array 137 for a memory access operation, such as programming data (i.e., writing data), reading data, or erasing data. Each of the vertical string driver circuits 139 can be coupled to a respective global access line. Each of the global access lines can be selectively coupled to respective local access lines within a block during a memory access operation associated with a page within the block. The vertical string driver circuits 139 can be controlled based on signals from local media controller 135. Each of the vertical string driver circuits 139 can include or be coupled to a respective power circuit, and can provide voltages to respective word lines of the memory array 137 based on voltages provided by the respective power circuit. The voltages provided by the power circuits can be based on signals received from local media controller 135 and can vary depending on the memory access operation being performed. Further details with regard to the design, position, and operation of the vertical string driver circuits 139 are described below).
Claim(s) 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chibvongodze in view of Kwon in further view of Kim in further view of Sukekawa as applied to claim 13 above, and further in view of Cernea.
Regarding claim 16, Chibvongodze in view of Kwon in further view of Kim in further view of Sukekawa and further in view of Cernea teaches The memory system according to claim 13, wherein the word line drivers are included in the first wafer, configured on a substrate, (Chibvongodze paragraphs [0052-0053], The control die 104 includes a number of word line drivers 260(1)-260(n). The word line drivers 260 are configured to provide voltages to word lines. In this example, there are “n” word lines per block of memory cells. In one embodiment, one of the blocks in each plane 220, 230 is selected at a time for a memory array operation. If the memory operation is a program or read, one word line within the selected block is selected for the memory operation, in one embodiment. If the memory operation is an erase, all of the word lines within the selected block are selected for the erase, in one embodiment. The word line drivers 260 provide voltages to the word lines in a first selected block (e.g., Block 2) in memory die 102a, and also for the word lines in a second selected block (e.g., Block 2) in memory die 102b. In some embodiments, a single word line driver concurrently provides the voltage for a first word line in memory die 102a and a second word line in memory die 102b. Therefore, the number of word line drivers 260 can be reduced. The control die 104 may also include charge pumps, voltage generators, and the like, which may be used to provide voltages for the word line drivers 260 and/or the bit line drivers. The architecture in FIG. 2A permits such charge pumps, voltage generators and the like to generate voltages that are concurrently delivered to both memory die 102a, 102b) and arranged to vertically overlap the plurality of small blocks (Cernea paragraph [0220], In one 3D architecture shown in FIG. 8, the global bit lines GBLs are at the bottom of the memory layer and therefore are formed as one of these metal layers, such as metal layer-1 or metal layer-2. The vertical switch layer 1 then contains the LBL to GBL switches connecting the GBLs to the vertical local bit lines in the memory layer. Access to the word line are via the top metal layer from the top side the memory layer and therefore the word line drivers are implemented in the vertical switch layer 2 connecting each word line to a metal pad at top metal layer. Cernea teaches a vertical alignment for the word line drivers).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Chibvongodze, Kwon, Kim and Sukekawa with those of Cernea. Cernea teaches a structure with the word line driver components vertically overlapping and configuring with other components. This vertical configuration allows for more diverse access lines and greater flexibility with the overall 3D structure (Cernea paragraph [0186], The word line driver 350 can then switch between an exposed word line segment and a word line power source (not shown). The word line driver can have a width as wide as the segment of a word line. FIG. 18 shows two adjacent word line drivers 350-Even and 350-Odd, respectively switching two adjacent segments 312-Even and 312-Odd from two adjacent word lines across the y-direction. It will be seen that the even WL access line 355-Even along the y-direction accesses the even banks of word lines along the y-direction. Similarly, the odd WL access line 355-Odd along the y-direction accesses the odd banks of word lines along the y-direction. Each of these access lines only access alternate word line segment because these segments are not isolated by an oxide layer 404).
Regarding claim 17, Chibvongodze in view of Kwon in further view of Kim in further view of Sukekawa and further in view of Cernea teaches The memory system according to claim 13, wherein the word line drivers are included in the second wafer, are configured on a substrate, (Chibvongodze paragraphs [0052-0053], The control die 104 includes a number of word line drivers 260(1)-260(n). The word line drivers 260 are configured to provide voltages to word lines. In this example, there are “n” word lines per block of memory cells. In one embodiment, one of the blocks in each plane 220, 230 is selected at a time for a memory array operation. If the memory operation is a program or read, one word line within the selected block is selected for the memory operation, in one embodiment. If the memory operation is an erase, all of the word lines within the selected block are selected for the erase, in one embodiment. The word line drivers 260 provide voltages to the word lines in a first selected block (e.g., Block 2) in memory die 102a, and also for the word lines in a second selected block (e.g., Block 2) in memory die 102b. In some embodiments, a single word line driver concurrently provides the voltage for a first word line in memory die 102a and a second word line in memory die 102b. Therefore, the number of word line drivers 260 can be reduced. The control die 104 may also include charge pumps, voltage generators, and the like, which may be used to provide voltages for the word line drivers 260 and/or the bit line drivers. The architecture in FIG. 2A permits such charge pumps, voltage generators and the like to generate voltages that are concurrently delivered to both memory die 102a, 102b) and are arranged to vertically overlap the plurality of large blocks (Cernea paragraph [0220], In one 3D architecture shown in FIG. 8, the global bit lines GBLs are at the bottom of the memory layer and therefore are formed as one of these metal layers, such as metal layer-1 or metal layer-2. The vertical switch layer 1 then contains the LBL to GBL switches connecting the GBLs to the vertical local bit lines in the memory layer. Access to the word line are via the top metal layer from the top side the memory layer and therefore the word line drivers are implemented in the vertical switch layer 2 connecting each word line to a metal pad at top metal layer. Cernea teaches a vertical alignment for the word line drivers).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Chibvongodze, Kwon, Kim and Sukekawa with those of Cernea. Cernea teaches a structure with the word line driver components vertically overlapping and configuring with other components. This vertical configuration allows for more diverse access lines and greater flexibility with the overall 3D structure (Cernea paragraph [0186], The word line driver 350 can then switch between an exposed word line segment and a word line power source (not shown). The word line driver can have a width as wide as the segment of a word line. FIG. 18 shows two adjacent word line drivers 350-Even and 350-Odd, respectively switching two adjacent segments 312-Even and 312-Odd from two adjacent word lines across the y-direction. It will be seen that the even WL access line 355-Even along the y-direction accesses the even banks of word lines along the y-direction. Similarly, the odd WL access line 355-Odd along the y-direction accesses the odd banks of word lines along the y-direction. Each of these access lines only access alternate word line segment because these segments are not isolated by an oxide layer 404).
Allowable Subject Matter
Claims 19-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claims 19 and 20 recite further details regarding the physical orientation of the memory device, describing a memory device including a plurality of wafers with small and large memory blocks containing a larger number of vertically stacked word lines and strings. The newly added dependent claims 19 and 20 recite a number of n first word lines included in each of the large memory blocks corresponding one-to-one to n number of word lines in the small blocks, coupled in common to a word line driver, as well as a second set of word lines, that do not share word line drivers with one of the small blocks, corresponding on a one-to-one basis to an n number of word lines included in another small block, couped in common to one word line driver coupled to one of the n number of word lines of the another small block. The memory device structure specifically describing the word line driver mapping n word lines coupled to a plurality of common word line drivers is not taught in the technological field and is allowable over the existing prior art.
Response to Arguments
Applicant’s arguments, see pages 1-4 (numbered pages 6-9), filed October 16th, 2025, with respect to the rejection(s) of claim(s) 1-20 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Chibvongodze et al. (US Publication No. 2020/0365210 -- "Chibvongodze") in view of Yip et al. (US Publication No. 2022/0076751 -- "Yip") in further view of Kwon et al. (US Publication No. 2022/0130849 -- "Kwon") and further in view of Sukekawa (US Publication No. 2020/0286859 – “Sukekawa”).
The Sukekawa reference has been added to the 35 USC 103 Rejection of independent claims 1, 10 and 13 to disclose the concept of word line drivers being contained in a semiconductor wafer as well as on a substrate. Further details regarding the Sukekawa reference are cited in the rejection above. Independent claims 10 and 13 similarly have had the teachings of Sukekawa added as a new reference. In light of the newly added reference, the 35 USC 103 Rejection is maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Mohammadzadeh et al. (US Publication No. 2018/0349029) is relevant to the newly added subject matter claimed in the independent claims. The reference discloses vertically stacked word lines (i.e., paragraph [0041], For example, a plurality of word lines per bus 342 may be oriented vertically (e.g., stacked) in each block 341 of each plane 343 to form a multiple of the number of buses) which can be different for different memory blocks based on the number of rows contained in said memory block (i.e., see paragraph [0042], Each block may include a number of physical rows of memory cells that can each be coupled to a respective word line (e.g., access line). The number of rows in each block can be 32, 64, or 128, but embodiments are not limited to a particular number of rows, which can be referred to collectively as rows per block).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.C.K./ Examiner, Art Unit 2136
/KENNETH M LO/Supervisory Patent Examiner, Art Unit 2116