DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/14/2025 has been entered.
Response to Argument
Claims 1-3, 5-13, and 15-20 were previously pending, independent claims 1, and 10, are amended. Claims 4 and 14 are canceled.
In light of the amendments, a new ground(s) of rejection is made in view of U.S.C. 112(a) for claims 1-3, 5-13, and 15-20.
Applicant’s arguments on pages 1-6, filed 11/27/2025 with respect to U.S.C. 103 rejection of claims 1-3, 5-13, and 15-20 have been fully considered but they are not considered persuasive.
Applicant argues that Chiba does not disclose the following: a test method, only configured to use a test system to test a chip of a circuit under test, wherein the circuit under test further comprises a DC-DC converter.
Examiner respectfully disagrees. Regarding the following statement: a test method, only configured to use a test system to test a chip of a circuit under test, wherein the circuit under test further comprises a DC-DC converter, such property (as described in the preamble of claim 1) was considered not a limitation but an inherent property of the structure defined by the body of the claim. It has been held that a preamble is denied the effect of a limitation where the claim is drawn to a structure and the portion of the claim following the preamble is a self-contained description of the structure not depending for completeness upon the introductory clause. Kropa v. Robie, 187 F.2d at 152, 88 USPQ2d at 480-81. Limitations that are not claimed outside of the preamble are not considered further limiting. For at least these reason, Applicant’s argument is unpersuasive.
Applicant argues that a test method, only configured to use a test system to test a chip of a circuit under test, wherein the circuit under test further comprises a DC-DC converter is a meaningful limitation of the claim.
Examiner respectfully disagrees and reiterates, it has been held that a preamble is denied the effect of a limitation where the claim is drawn to a structure and the portion of the claim following the preamble is a self-contained description of the structure not depending for completeness upon the introductory clause. Kropa v. Robie, 187 F.2d at 152, 88 USPQ2d at 480-81. Limitations that are not claimed outside of the preamble are not considered further limiting. For at least these reason, Applicant’s argument is unpersuasive.
Applicant argues that Tarng does not teach in a calibration stage of the test method, …in a test stage after the calibration stage, because the calibration path differs from the test path, as seen in Tarng Fig. 2 and therefore that the calibration path 204 does not pass through the system under test 203; therefore, it cannot obtain the calibrated signal during the test stage.
Examiner respectfully disagrees. Tarng states in col 3 lines 20-31, “Calibration path 204 is used to identify losses created by the test hardware and software. After these losses are identified, they can be used to compensate for hardware and software effects in the measurements of the system under test 203. In one embodiment, data is first passed through calibration path 204 from chirp generator 201. The output of the calibration path 204 is captured as the baseline. Then, system under test 203 is switched into the signal path and input signal data from chirp generator 201 is applied. The output data is captured from the system under test 203 and is divided by the calibration data to get the true system response for system under test 203.” It is because of this paragraph that the examiner believes that the system in test passes through the calibration and the test stage and thus is capable of removing the effects caused by variations between the circuits under test like current applications claim 1 is intended to do. For at least these reason, Applicant’s argument is unpersuasive.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 1-3, 5-13, and 15-20 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The disclosure as originally filed does not support the amendments found in independent claims 1 and 10. The amendment alleges that the test method is only configured to use a test system to test a chip of a circuit under test, however the disclose as originally filed makes no mention or indication that said test method is only to be used for this reason. Thus, independent claims 1 and 10 are rejected, and dependent claims 2-3, 5-9, 11-13, and 15-20 are also rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 6, 9, 10, 15, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiba (JP 2008224247 A) in view of Chang et al. (US 2010/0277214 A1) hereinafter Chang and further in view of Tarng (US 9081053 B2).
Regarding Claim 1, Chiba teaches, a DC-DC converter (“constitutes a DC-DC converter”, [0009]) of the circuit under test (Fig. 4 the DC-DC converter is a part of circuit 4, which is the semiconductor chip, which includes test circuit 49.), a processor of the test system ([0058] “the above-described semiconductor circuit chip (integrated circuit) 4 is a test in an integrated circuit including the functional circuit FC including the elements 41 to 48 and the test circuit 49 for inspecting the functional circuit FC” where [0058] “flash memory 49E is illustrated for simplification of description, but this includes a simple processor that performs the above-described operation in addition to the memory, and functions as a control circuit.”; obtaining a correspondence of the DC-DC converter ([0013] “a DC-DC converter comprising:… a control circuit which inputs an inspection signal to the functional circuit based on the control signal detected by the signal detection circuit” where the control signal and the inspection signal are correspondences of the DC-DC converter); filtering, by a filter circuit of the test system, the test pulse signal to generate a first test DC voltage to the circuit under test, [0029] “A (chip) coil 2 is connected in series to the subsequent stage of the output terminal SW, a load Z is connected to the subsequent stage of the coil 2, and a capacitor 5 is connected in parallel to the coil 2 between both ends of the load Therefore, the square wave pulse is smoothed by the low-pass filter (i.e., filter circuit of the test system) including the coil 2 and the capacitor 5, and a DC voltage corresponding to the duty ratio of the pulse is applied to the load Z. Examples of the load Z include a microprocessor (i.e., to the circuit under test).”); and extracting an output signal of the chip to determine a performance of the chip ([0007], where “If the functional circuit is normal, the value of the monitor signal will be a signal that is expected when the functional circuit is normal, and if there is an abnormality, the value will differ from the normal signal (i.e., performance of the chip will be shown on the monitor signal).”).
Chiba does not teach, a calibration stage of the test method, a test stage after the calibration stage; generating a test pulse signal, receives and converts the first test DC voltage into a second DC voltage according to the correspondence and transmits the second test DC voltage to the chip, wherein the correspondence represents a function of a duty cycle of the test pulse signal and the second test DC voltage, and wherein the chip generates the output signal according to the second test DC voltage.
Chang teaches, generating a test pulse signal (“ a first pulse signal P1 [0046]); receives and converting the first test DC voltage into a second DC voltage according to the correspondence ([0048] “a process of generating the first pulse width signal W1 may be divided into: first, the first pulse signal conversion unit 302 receives the first pulse signal P1 and converts the first pulse signal P1 to the second pulse width signal W2.”), and transmits the second test DC voltage ([0048], “the multiplication unit 304 receives the second pulse width signal W2”), and wherein the chip generates the output signal according to the second test DC voltage ([0048], “[the multiplication unit] multiplies the second pulse width signal W2 and the second pulse signal P2 to generate the third pulse signal P3”) wherein the correspondence represents a function of a duty cycle of the test pulse signal and the second test DC voltage ([0052] “It should be noted that a ratio of a voltage level of the second pulse width signal W2 in FIG. 5A to a voltage level of a peak of the first pulse signal P1 is equal to the duty ratio Ra of the first pulse signal P1. For example, if the duty ratio Ra of the first pulse signal P1 is 80%, and the voltage level of the peak of the first pulse signal P1 is VH1, then the voltage level of the second pulse width signal W2 which is generated after filtering of the second low pass filter 404 is equal to 0.8VH1.” where [0051] “the second pulse width signal W2 is a direct current (DC) signal”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, changing voltage values from the voltage regulator as discussed in Chang to the DC-DC converter under test and chip test methods discussed in Chang for the purpose of interchanging the type of voltage regulator provided in the circuit under test to control the voltage. This is advantageous because in order reliably have a test that inspects the functional circuit of the system and provide critical feedback of its operation.
Chiba and Chang do not teach a calibration stage of the test method, a test stage after the calibration stage.
Tarng teaches a calibration stage of the test method, (col 3 line 20-24) “ Calibration path (i.e., calibration stage) 204 is used to identify losses created by the test hardware and software. After these losses are identified, they can be used to compensate for hardware and software effects in the measurements of the system under test 203”; a test stage after the calibration stage (col 3 line 24-31 “In one embodiment, data is first passed through calibration path 204 from chirp generator 201. The output of the calibration path 204 is captured as the baseline. Then, system under test 203 is switched into the signal path and input signal data from chirp generator 201 is applied (i.e., test stage). The output data is captured from the system under test 203 and is divided by the calibration data to get the true system response for system under test 203.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the calibration stage before the test stage as discussed in Tarng to the test method discussed in Chiba and Chang in order to calibrate the test system of the DUT before testing begins. It is advantageous because the calibration stage can be utilized to identify losses created by the test hardware and software. After these losses are identified, they can be used to compensate for hardware and software effects in the measurements of the system under test (e.g., col 3 line 20-24, Tarng).
Regarding Claim 10, Chiba teaches, a DC-DC converter (“constitutes a DC-DC converter”, [0009]) of the circuit under test (Fig. 4 the DC-DC converter is a part of circuit 4, which is the semiconductor chip, which includes test circuit 49.), a control interface (“control terminal” [0009]), configured to extract an output signal of the chip to determine a performance of the chip (specifically, “extracting an output signal of the chip to determine a performance of the chip” is implicitly taught in [0007], where “If the functional circuit is normal, the value of the monitor signal will be a signal that is expected when the functional circuit is normal, and if there is an abnormality, the value will differ from the normal signal.” Implies that there is an output, “monitor signal” that is being extracted from the test system to determine the performance of the chip, abnormal or normal); obtaining a correspondence of the DC-DC converter ([0013] “a DC-DC converter comprising:… a control circuit which inputs an inspection signal to the functional circuit based on the control signal detected by the signal detection circuit” where the control signal and the inspection signal are correspondences of the DC-DC converter); filtering, by a filter circuit of the test system, the test pulse signal to generate a first test DC voltage to the circuit under test, [0029] “A (chip) coil 2 is connected in series to the subsequent stage of the output terminal SW, a load Z is connected to the subsequent stage of the coil 2, and a capacitor 5 is connected in parallel to the coil 2 between both ends of the load Z. Therefore, the square wave pulse is smoothed by the low-pass filter (i.e., filter circuit of the test system) including the coil 2 and the capacitor 5, and a DC voltage corresponding to the duty ratio of the pulse is applied to the load Z. Examples of the load Z include a microprocessor (i.e., to the circuit under test).”)
Chiba does not teach, a calibration stage of the test method, a test stage after the calibration stage; a processor, configured to generate a test pulse signal; receives the first test DC voltage, generates a second test DC voltage according to the first DC voltage and the correspondence, and transmits the second test DC voltage to the chip, and wherein the chip generates the output signal according to the second test DC voltage, wherein the correspondence represents a function of a duty cycle of the test pulse signal and the second test DC voltage.
Chang teaches, a processor (“control processor” [0080]), configured to generate a test pulse signal [0080]; wherein the circuit under test receives and converts the first test DC voltage into a second DC voltage according to the first DC voltage and the correspondence ([0048] “a process of generating the first pulse width signal W1 may be divided into: first, the first pulse signal conversion unit 302 receives the first pulse signal P1 and converts the first pulse signal P1 to the second pulse width signal W2.”,) and transmits the second test DC voltage to the chip ([0048], “the multiplication unit 304 receives the second pulse width signal W2”), and wherein the chip generates the output signal according to the second test DC voltage ([0048], “[the multiplication unit] multiplies the second pulse width signal W2 and the second pulse signal P2 to generate the third pulse signal P3”); wherein the correspondence represents a function of a duty cycle of the test pulse signal and the second test DC voltage ([0052] “It should be noted that a ratio of a voltage level of the second pulse width signal W2 in FIG. 5A to a voltage level of a peak of the first pulse signal P1 is equal to the duty ratio Ra of the first pulse signal P1. For example, if the duty ratio Ra of the first pulse signal P1 is 80%, and the voltage level of the peak of the first pulse signal P1 is VH1, then the voltage level of the second pulse width signal W2 which is generated after filtering of the second low pass filter 404 is equal to 0.8VH1.” where [0051] “the second pulse width signal W2 is a direct current (DC) signal”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the chip undertest with changing voltage values from the voltage regulator as discussed in Chang to the DC-DC converter and chip test methods discussed in Chang for the purpose of interchanging the type of voltage regulator provided in the circuit under test to control the voltage. This is advantageous because in order reliably have a test that inspects the functional circuit of the system and provide critical feedback of its operation.
Chiba and Chang do not teach a calibration stage of the test method, a test stage after the calibration stage.
Tarng teaches a calibration stage of the test method, (col 3 line 20-24) “ Calibration path (i.e., calibration stage) 204 is used to identify losses created by the test hardware and software. After these losses are identified, they can be used to compensate for hardware and software effects in the measurements of the system under test 203”; a test stage after the calibration stage (col 3 line 24-31 “In one embodiment, data is first passed through calibration path 204 from chirp generator 201. The output of the calibration path 204 is captured as the baseline. Then, system under test 203 is switched into the signal path and input signal data from chirp generator 201 is applied (i.e., test stage). The output data is captured from the system under test 203 and is divided by the calibration data to get the true system response for system under test 203.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the calibration stage before the test stage as discussed in Tarng to the test method discussed in Chiba and Chang in order to calibrate the test system of the DUT before testing begins. It is advantageous because the calibration stage can be utilized to identify losses created by the test hardware and software. After these losses are identified, they can be used to compensate for hardware and software effects in the measurements of the system under test (e.g., col 3 line 20-24, Tarng).
Regarding Claim 9 and 18, Chiba, Chang and Tarng teach the limitations of Claims 1 and 10, respectively.
Chiba fails to teach, wherein the DC-DC converter is a core voltage DC-DC converter, a central processing unit DC-DC converter or a dual-channel dynamic random access memory DC-DC converter.
Chang teaches, wherein the DC-DC converter is a core voltage DC-DC converter (a core- voltage DC-DC converter is known in the art as a specific type of DC-DC converter that is designed to precisely regulate the voltage supplied directly to the core of a processor, like a CPU, ensuring it receives the optimal voltage needed for efficient operation, often with fine-tuned adjustments based on the workload and operating conditions; essentially, it is a specialized power converter that manages the critical voltage level for the central processing unit of a device), a central processing unit DC-DC converter or a dual-channel dynamic random access memory DC-DC converter (specifically “wherein the DC-DC converter is a core voltage DC-DC converter” is implicitly taught in [0013]. “When the main chip works at a low temperature, the operating voltage is increased and the clock frequency is increased to ensure the computing power of the processor,” teaches of a processor that directly relies on the regulation of the voltage being supplied to the circuit to keep the processor at the correct temperature, implying the DC-DC regulator used in the circuitry is a core-voltage converter.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the DC-DC converter and chip test methods discussed in Chiba to the pulse generation method in Chang in order to reliably inspect the functional circuit of the system and provide critical feedback of its operation.
Regarding Claim 6 and 15, Chiba and Chang teach the limitations of claim 1 and 10, respectively.
Chiba fails to teach, wherein the test pulse signal is generated according to the correspondence.
Chang teaches, wherein the test pulse signal is generated according to the correspondence ([0053], “the multiplication unit 304 receives the second pulse width signal W2 and the second pulse signal P2, and multiplies the second pulse width signal W2 and the second pulse signal P2 (i.e., an analog signal) to generate the third pulse signal P3”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the DC-DC converter and chip test methods discussed in Chiba to the pulse generation method in Chang in order to reliably inspect the functional circuit of the system and provide critical feedback of its operation.
Claim(s) 2, 5, 11, and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiba, Chang and Tarng and further in view of Takahashi et al. (US 2011/0285372 A1, Herein Takahashi).
Regarding Claim 2 and 11, Chiba, Chang and Tarng teach the limitations of claim 1 and 10, respectively.
Chiba teaches, the filter circuit (“generating circuit” [0010]), and the DC power converter [0009].
Chiba does not teach, the processor, is further configured to generate a first pulse signal and a second pulse signal, wherein the first pulse signal and the second pulse signal respectively have a first duty cycle and a second duty cycle; to filter the first pulse signal and the second pulse signal to generate a first DC voltage and a second DC voltage; the processor, is further configured to extract a voltage wherein the DC-DC converter generates said voltage, wherein the correspondence is obtained according to the first duty cycle, the second duty cycle, and a third DC voltage and a fourth DC voltage.
Chang teaches, the processor(“control processor” [0080]) is further configured to generate a first pulse signal (“first pulse signal P1” [0048]) and a second pulse signal (“second pulse signal” [0048]), wherein the first pulse signal and the second pulse signal respectively have a first duty cycle and a second duty cycle (“a duty ratio of the first pulse signal and a duty ratio of the second pulse signal”, [0008], where duty ratio and duty cycle are seen as interchangeable in the art); to filter the first pulse signal and the second pulse signal to generate a first DC voltage (“the first pulse width signal is a DC signal,” [0014] where a DC signal inherently has a DC voltage) and a second DC voltage (“the second pulse width signal is a DC signal,” [0016] where a DC signal inherently has a DC voltage); the processor (“control processor” [0080]), is further configured to extract a voltage wherein the DC-DC converter generates said voltage (extracting a signal is taught implicitly in Fig. 4 [0050] “the block diagram illustrating a signal generator” because the signals being generated go to a “comparison unit 408”, therefore if any output from the DC-DC converter that goes a processor (or processing unit) is interpreted as extracting), wherein the correspondence is obtained according to the first duty cycle, the second duty cycle ([0027], “generates the signal having multiplication information of the duty ratios of a plurality of pulse signals through extracting information of the duty ratios of the pulse signals.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the DC-DC converter and chip test methods discussed in Chiba to the pulse generation method in Chang in order to reliably inspect the functional circuit of the system and provide critical feedback of its operation.
Chiba, Chang, and Tarng does not teach a third DC voltage and a fourth DC voltage.
Takahashi implicitly teaches a third and fourth DC voltage [0002]. This is because if a DC-DC converter is capable of generating multiple/plurality voltages, then having a third and fourth is arbitrary since one can use different referencing techniques for labeling outputs.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the multiple/plurality of voltages taught in Takahashi and apply them the combined test method taught by Chiba, Chang, and Tarng because a DC-DC converter is used in a variety of electronic devices when a stable power supply voltage is generated from a voltage with large fluctuation or when a plurality of different power supply voltages is needed.
Regarding Claim 5 and 13, Chiba, Chang, Tarng and Takahashi and teach the limitations of claim 2 and 11, respectively.
Chiba does not teach, wherein the processor, performs an interpolation on a difference between the first duty cycle and the second duty cycle, and a difference between a DC voltage and another DC voltage, and obtains the correspondence according to a result of the interpolation, and a third DC voltage and a fourth DC voltage,
Chang teaches, wherein the processor (“control processor” [0080]) performs an interpolation on a difference between the first duty cycle and the second duty cycle ([0052]), and a difference between a DC voltage and another DC voltage ([0053]) and obtains the correspondence according to a result of the interpolation ([0055]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the DC-DC converter and chip test methods discussed in Chiba to the pulse generation method in Chang in order to reliably inspect the functional circuit of the system and provide critical feedback of its operation.
Chiba, Chang, and Tarng does not teach a third DC voltage and a fourth DC voltage.
Takahashi implicitly teaches a third and fourth DC voltage [0002]. This is because if a DC-DC converter is capable of generating multiple/plurality voltages, then having a third and fourth is arbitrary since one can use different referencing techniques for labeling outputs.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the multiple/plurality of voltages taught in Takahashi and apply them the combined test method taught by Chiba, Chang, and Tarng because a DC-DC converter is used in a variety of electronic devices when a stable power supply voltage is generated from a voltage with large fluctuation or when a plurality of different power supply voltages is needed.
Claim(s) 3,12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiba, Chang, Tarng, Takahashi, and further in view of Muehlenbrock (DE 102006056785 A1).
Regarding Claim 3 and 12, Chiba, Chang, Tarng and Takahashi teach the limitations of claims 2 and 11 respectively.
Chiba, Chang, Tarng and Takahashi fail to teach, wherein the first duty cycle is 10%, and the second duty cycle is 20%.
Muehlenbrock teaches, wherein the first duty cycle is 10%, and the second duty cycle is 20% ([0028], the signal curve can also be read in such a way that four first control signal sections, each with a duty cycle of 10%, are followed by a second control signal section with a duty cycle of 20%”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the duty cycle percents discussed in Muehlenbrock to the test method discussed in Chiba, Chang, Tarng and Takahashi in order to generate a control signal for a circuit breaker and a corresponding device, which enable a high temporal resolution of the setting accuracy of the control signal, ([0003], Muehlenbrock).
Claim(s) 7, 8, 19, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiba, Chang, Tarng and further in view of Ma (CN 110687952 A).
Regarding Claim 7, Chiba, Chang and Tarng teach the limitations of claim 1.
Chiba, Chang and Tarng fails to teach, wherein a voltage value of the second test DC voltage is an upper limit of an operating voltage of the chip.
Ma teaches, wherein a voltage value of the second test DC voltage is an upper limit of an operating voltage of the chip [0054].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, combine the voltage regulation discussed in Ma to the test method discussed by Chiba, Chang and Tarng in order to ensure the reliability of working voltage regulation, it is necessary to reasonably set the circuit parameters of the voltage regulation module so that the working voltage can be adjusted between the maximum working voltage and the minimum working voltage, thereby ensuring the reliability of the main chip performance, ([0015], Ma).
Regarding Claim 8, Chiba, Chang and Tarng teach the limitations of claim 1.
Chiba, Chang and Tarng fails to teach, wherein a voltage value of the second test DC voltage is a lower limit of an operating voltage of the chip.
Ma teaches, wherein a voltage value of the second test DC voltage is a lower limit of an operating voltage of the chip [0054].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, combine the voltage regulation discussed in Ma to the test method discussed by Chiba, Chang and Tarng in order to ensure the reliability of working voltage regulation, it is necessary to reasonably set the circuit parameters of the voltage regulation module so that the working voltage can be adjusted between the maximum working voltage and the minimum working voltage, thereby ensuring the reliability of the main chip performance, ([0015], Ma).
Regarding Claim 19, Chiba, Chang and Tarng teach the limitations of claim 10.
Chiba, Chang and Tarng fail to teach, a power resistor configured to provide a reference voltage to the circuit under test.
Ma teaches, a power resistor configured to provide a reference voltage to the circuit under test (specifically a power resistor is found implicitly in [0013] “a voltage regulation module”, because a power resistor is known in the art to be a component in an electrical circuit that converts excess energy into heat to protect technology and maintain stable performance).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, combine the voltage regulation discussed in Ma to the test method discussed by Chiba, Chang and Tarng in order to ensure the reliability of working voltage regulation, it is necessary to reasonably set the circuit parameters of the voltage regulation module so that the working voltage can be adjusted between the maximum working voltage and the minimum working voltage, thereby ensuring the reliability of the main chip performance, ([0015], Ma).
Regarding Claim 20, Chiba, Chang and Tarng teach the limitations of claim 1.
Chiba, Chang and Tarng fail to teach, wherein the filter circuit comprises: a first resistor; a second resistor; a third resistor, wherein a first terminal of the first resistor is connected to the ground, a second terminal of the first resistor is coupled to a first terminal the second resistor, a second terminal of the second resistor is coupled to a first terminal of the third resistor, wherein the second terminal of the first resistor and the first terminal of the second resistor is configured to receive the test pulse signal; and a capacitor, wherein a first terminal of the capacitor is coupled to the second terminal of the second resistor and the first terminal of the third resistor, and a second terminal of the capacitor is connected to the ground, wherein a second terminal of the third resistor is configured to output the first test DC voltage.
Ma explicitly teaches, a first resistor (“a first resistor”; [0016]); a second resistor (“a second resistor”; [0016]); a third resistor (“a third resistor”; [0023]), a second terminal of the first resistor is coupled to a first terminal the second resistor [0016] , a second terminal of the second resistor is coupled to a first terminal of the third resistor (Fig. 2 R2 and R3), wherein the second terminal of the first resistor and the first terminal of the second resistor is configured to receive the test pulse signal ([0016]); and a capacitor (“a filter capacitor,” [0023]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, combine the voltage regulation discussed in Ma to the test method discussed by Chiba, Chang and Tarng in order to ensure the reliability of working voltage regulation, it is necessary to reasonably set the circuit parameters of the voltage regulation module so that the working voltage can be adjusted between the maximum working voltage and the minimum working voltage, thereby ensuring the reliability of the main chip performance, ([0015], Ma).
Ma fails to explicitly teach, a first terminal of the first resistor is connected to the ground, and wherein a first terminal of the capacitor is coupled to the second terminal of the second resistor and the first terminal of the third resistor, and a second terminal of the capacitor is connected to the ground; wherein a second terminal of the third resistor is configured to output the first test DC voltage.
It would have been obvious to one of ordinary skill in the art before the filing of the invention to arrive at a first terminal of the first resistor is connected to the ground ([0023], “the second end of the second resistor is grounded”), a first terminal of the capacitor is coupled to the second terminal of the second resistor and the first terminal of the third resistor” ([0023]), and a second terminal of the capacitor is connected to the ground ([0023]), and wherein a second terminal of the third resistor is configured to output the first test DC voltage ([0023], “other end of the sixth resistor is connected to the pulse pin of the main chip”), where it would appear that the specific arrangement of elements provided by the applicant only involves routing skill in the art and therefore one of ordinary skill in the art would have the knowledge to rearrange the resistors, or labels to get the desired effect.
Claim(s) 16, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiba, Chang, Tarng, Takahashi, and Ma.
Regarding Claim 16, Chiba, Chang, Tarng and Takahashi teach the limitations of claim 11.
Chiba, Chang, Tarng and Takahashi fails to teach, wherein a voltage value of the second test DC voltage is an upper limit of an operating voltage of the chip.
Ma teaches, wherein a voltage value of the second test DC voltage is an upper limit of an operating voltage of the chip [0054].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, combine the voltage regulation discussed in Ma to the test method discussed by Chiba, Chang, Tarng and Takahashi in order to ensure the reliability of working voltage regulation, it is necessary to reasonably set the circuit parameters of the voltage regulation module so that the working voltage can be adjusted between the maximum working voltage and the minimum working voltage, thereby ensuring the reliability of the main chip performance, ([0015], Ma).
Regarding Claim 17, Chiba, Chang, Tarng and Takahashi teach the limitations of claim 11.
Chiba, Chang, Tarng and Takahashi i fails to teach, wherein a voltage value of the second test DC voltage is a lower limit of an operating voltage of the chip.
Ma teaches, wherein a voltage value of the second test DC voltage is a lower limit of an operating voltage of the chip [0054].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, combine the voltage regulation discussed in Ma to the test method discussed by Chiba, Chang, Tarng and Takahashi in order to ensure the reliability of working voltage regulation, it is necessary to reasonably set the circuit parameters of the voltage regulation module so that the working voltage can be adjusted between the maximum working voltage and the minimum working voltage, thereby ensuring the reliability of the main chip performance, ([0015], Ma).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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/EMMA ALEXANDER/Patent Examiner, Art Unit 2863
/Catherine T. Rastovski/Supervisory Primary Examiner, Art Unit 2863