Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of the information disclosure statements filed on 23 January 2026, U.S. patents and Foreign Patents have been considered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 7 and 9 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over US20180348645A1 (Ravensbergen) in view of US20180292326A1 (Manassen).
In regards to claim 1, (Ravensbergen) shows :
A method of correcting a design layout of a semiconductor device, the method comprising: Ravensbergen [0034] teaches lithographic apparatus configured to perform a lithographic process where the lithographic apparatus may be configured to use the result of a measurement by the metrology apparatus of a structure formed by the lithographic process when performing a subsequently lithographic process to improve the subsequent lithographic process.
measuring misaligned values of a portion of points of a target pattern of each of a plurality of regions of interest in a semiconductor device fabricated based on an original layout; Ravensbergen [0064] teaches that target asymmetry makes a contribution to zeroth order reflected beams and novel interferometry can be used to measure the asymmetry contribution with high sensitivity. Ravensbergen [0061] teaches targets may include four gratings positioned closely together within a measurement scene formed by the metrology radiation illumination beam.
generating a target layout of the semiconductor device using the estimated misaligned values; Ravensbergen [0120] teaches the lithographic system comprises a lithographic apparatus that performs a lithographic process where the lithographic apparatus may be configured to use the result of a measurement by the metrology apparatus when performing a subsequently lithographic process.
Ravensbergen differs from the claimed invention in that it does not explicitly disclose estimating misaligned values of unmeasured points of the target pattern using an artificial neural network trained based on the measured misaligned values of the portion of points;
Manassen teaches estimating misaligned values of unmeasured points of the target pattern using an artificial neural network trained based on previously measured misaligned values of the portion of points; Manassen [0080] teaches neural networks, support-vector machines, dimensionality-reduction algorithms including principal component analysis, independent component analysis, local-linear embedding for data analysis and fitting.
The motivation to combine Ravensbergen and Manassen at the effective filing date of the invention is to improve semiconductor metrology accuracy by applying advanced machine learning techniques to traditional interferometric measurement systems, as both references address semiconductor manufacturing quality control and a person of ordinary skill would be motivated to enhance measurement precision using neural networks for better defect detection and pattern correction.
In regards to claim 2, (Ravensbergen) shows the method of claim 1:
further comprising fabricating the semiconductor device based on the original layout before performing the measuring misaligned values; Ravensbergen [0034] teaches lithographic apparatus configured to perform a lithographic process where substrates that are exposed by the lithographic apparatus are exposed correctly and consistently.
wherein the measuring misaligned values of the portion of points comprises: selecting the plurality of regions of interest in the semiconductor device; Ravensbergen [0061] teaches target selection where targets may include four gratings positioned closely together so that they will all be within a measurement scene or measurement spot formed by the metrology radiation illumination beam.
measuring the misaligned values of the portion of points of the target pattern using a measuring device; Ravensbergen [0053] teaches metrology apparatus is used to determine the properties of the substrates and how the properties of different substrates or different layers of the same substrate vary from layer to layer.
In regards to claim 3, (Ravensbergen) shows the method of claim 2:
wherein the selecting the plurality of regions of interest comprises: inputting coordinate values of each of a first corner and a second corner in a diagonal direction of a respective rectangle representing each of the plurality of regions of interest; Ravensbergen [0045] teaches position sensor for accurate positioning where the substrate table can be moved accurately so as to position different target portions in the path of the radiation beam.
In regards to claim 4, (Ravensbergen) shows the method of claim 2:
wherein the measuring device comprises a scanning electronic microscope or a Nano Geometry Research (NGR) device; Ravensbergen [0030] teaches reference measurement source is another metrology tool capable of highly accurate measurements of a target structure including TEM, SEM, X-Ray scatterometer.
In regards to claim 5, (Ravensbergen) does not show the method of claim 1: wherein the estimating misaligned values of the unmeasured points comprises: training the artificial neural network with the measured misaligned values; estimating the misaligned values of the unmeasured points of the target pattern using the trained artificial neural network; determining whether the estimated misaligned values are correct;
Manassen teaches wherein the estimating misaligned values of the unmeasured points comprises: training the artificial neural network with the measured misaligned values; Manassen [0080] teaches neural networks training for data collection and fitting performed by algorithms that include modeling, optimization and fitting.
Manassen teaches estimating the misaligned values of the unmeasured points of the target pattern using the trained artificial neural network; Manassen [0080] teaches neural networks application where data collection and fitting may be performed by the Signal Response Metrology software product.
Manassen teaches determining whether the estimated misaligned values are correct; Manassen [0068] teaches image quality metrics may include image brightness, image contrast, image noise where images of features may be captured within selected tolerance to provide images having an image quality metric within a selected tolerance.
The motivation to combine Ravensbergen and Manassen at the effective filing date of the invention is to enhance neural network training for semiconductor metrology by providing validation mechanisms for estimated values, as both references address metrology accuracy and a person of ordinary skill would recognize the need to verify machine learning outputs before implementing layout corrections.
In regards to claim 6, (Ravensbergen) shows the method of claim 5: wherein determining whether the estimated misaligned values are correct comprises: performing k-fold cross-validation on the estimated misaligned values, wherein k is a natural number greater than two;
Manassen teaches wherein determining whether the estimated misaligned values are correct comprises: performing k-fold cross-validation on the estimated misaligned values, wherein k is a natural number greater than two; Manassen [0080] teaches machine-learning algorithms such as neural networks, support-vector machines, dimensionality-reduction algorithms for validation and analysis. Manassen [0076] teaches layer-specific imaging configurations may be selected by simulating images of sample layers of interest and selecting the imaging configurations providing a desired set of image quality metrics for each sample layer of interest where step 402 may include simulating one or more metrology measurements based on images of sample layers.
The motivation to combine Ravensbergen and Manassen at the effective filing date of the invention is to implement robust validation techniques for machine learning algorithms in semiconductor metrology, as both references emphasize measurement accuracy and a person of ordinary skill would be motivated to use standard cross-validation methods to ensure neural network reliability in critical manufacturing processes.
In regards to claim 7, (Ravensbergen) shows the method of claim 6: wherein the performing k-fold cross-validation comprises: randomly classifying the estimated misaligned values into k-fold sets; and using k-1 number of sets of the k-fold sets as training sets and a single remaining set of the k-fold sets as a testing set;
Manassen teaches wherein the performing k-fold cross-validation comprises: randomly classifying the estimated misaligned values into k-fold sets; and using k-1 number of sets of the k-fold sets as training sets and a single remaining set of the k-fold sets as a testing set; Manassen [0080] teaches algorithms that include modeling, optimization and fitting with machine-learning algorithms for data analysis including training and testing procedures.
The motivation to combine Ravensbergen and Manassen at the effective filing date of the invention is to apply established machine learning validation protocols to semiconductor measurement systems, as both references focus on measurement precision and a person of ordinary skill would recognize the importance of proper training/testing procedures for neural networks used in manufacturing quality control.
In regards to claim 9, (Ravensbergen) does not show the method of claim 1: wherein the artificial neural network comprises: a plurality of input nodes; a plurality of output nodes; a plurality of hidden nodes connected between the plurality of input nodes and the plurality of output nodes; wherein a portion of the plurality of output nodes correspond to the estimated misaligned values;
Manassen teaches wherein the artificial neural network comprises: a plurality of input nodes; a plurality of output nodes; a plurality of hidden nodes connected between the plurality of input nodes and the plurality of output nodes; Manassen [0080] teaches neural networks architecture for data analysis and fitting. Manassen [0035] teaches controller includes one or more processors configured to execute program instructions maintained on a memory medium where the one or more processors may include any microprocessor-type device configured to execute algorithms and instructions including desktop computer, mainframe computer system, workstation, image computer, parallel processor configured to operate the imaging device.
Manassen teaches wherein a portion of the plurality of output nodes correspond to the estimated misaligned values; Manassen [0083] teaches metrology measurements based on images generated by the imaging device where metrology measurements may include overlay measurements, feature size measurements.
The motivation to combine Ravensbergen and Manassen at the effective filing date of the invention is to define detailed neural network architectures for semiconductor metrology applications, as both references address computational analysis of measurement data and a person of ordinary skill would be motivated to specify network structures that map measurement inputs to misalignment predictions for layout correction.
In regards to claim 10, (Ravensbergen) does not show the method of claim 1, further comprising: training the artificial neural network using a Random Forest algorithm;
Manassen teaches training the artificial neural network using a Random Forest algorithm; Manassen [0080] teaches machine-learning algorithms such as neural networks for data analysis where various implementations of algorithms may be performed by the controller. Manassen [0081] teaches computational algorithms performed by the controller may be tailored for metrology applications through the use of parallelization, distributed computation, load-balancing, multi-service support, design and implementation of computational hardware, or dynamic load optimization where various implementations of algorithms may be performed by the controller through firmware, software, or field-programmable gate arrays.
The motivation to combine Ravensbergen and Manassen at the effective filing date of the invention is to apply ensemble learning methods to semiconductor measurement analysis, as both references address data analysis algorithms for metrology and a person of ordinary skill would be motivated to use Random Forest techniques to improve prediction accuracy and robustness in manufacturing environments.
In regards to claim 11, (Ravensbergen) shows the method of claim 1, further comprising:
wherein the semiconductor device comprises: a first semiconductor layer comprising: an upper substrate comprising a plurality of word-lines extending in a first horizontal direction, at least one string selection line, at least one ground selection line, and a plurality of bit-lines extending in a second horizontal direction substantially perpendicular to the first horizontal direction; Ravensbergen [0122] teaches lithographic apparatus described herein may have applications in the manufacture of integrated circuits, integrated optical systems, guidance and detection patterns for magnetic domain memories where the substrate may be processed more than once to create a multi-layer integrated circuit. Ravensbergen [0063] teaches wafer generally refers to substrates formed of a semiconductor or non-semiconductor material where examples include monocrystalline silicon, gallium arsenide, and indium phosphide found in semiconductor fabrication facilities.
a memory cell array comprising at least one memory block on the upper substrate; Ravensbergen [0065] teaches wafer may include a plurality of dies having repeatable pattern features where formation and processing of such layers of material may ultimately result in completed devices.
a second semiconductor layer under the first semiconductor layer in a direction substantially perpendicular to the first and second horizontal directions, wherein the second semiconductor layer comprises a lower substrate and a peripheral circuit configured to control the memory cell array, wherein the peripheral circuit is on the lower substrate; Ravensbergen [0065] teaches one or more layers formed on a wafer may be patterned or unpatterned where a wafer may include a plurality of dies each having repeatable pattern features.
wherein the at least one memory block comprises a cell array region comprising a plurality of memory cells and a cell extension region on a side of the cell region in the first horizontal direction; Ravensbergen [0061] teaches targets may include four gratings positioned closely together so that they will all be within a measurement scene where gratings may have differently biased overlay offsets to facilitate measurement of overlay between the layers.
In regards to claim 12, (Ravensbergen) shows the method of claim 11, further comprising:
wherein the plurality of regions of interest comprises; a first region of interest that comprises a first target pattern adjacent to a boundary between the cell array region and the cell extension region; Ravensbergen [0061] teaches gratings may be X-direction gratings with biases or Y-direction gratings with offsets where separate images of these gratings can be identified in the image captured by sensor.
a second region of interest that comprises at least one of a plurality of second target patterns which are repeated in the cell extension region; Ravensbergen [0061] teaches target comprises four gratings positioned closely together where gratings may have differently biased overlay offsets in order to facilitate measurement of overlay between the layers.
In regards to claim 13, (Ravensbergen) shows the method of claim 12, wherein:
a progressive misalignment occurs in the target pattern due to a fabrication process of the semiconductor device; Ravensbergen [0064] teaches target asymmetry makes a contribution to zeroth order reflected beams where the inventors have recognized that novel interferometry can be used to measure the asymmetry contribution to the zeroth order reflected beams with high sensitivity.
the progressive misalignment is corrected using the estimated misaligned values; Ravensbergen [0093] teaches applying a known bias to the asymmetry where the applied bias is indicated and changes in intensity due to the asymmetry to be measured are much larger for the same amount of asymmetry.
In regards to claim 14, (Ravensbergen) shows the method of claim 12, wherein:
a local misalignment occurs in each of the second target patterns due to a shape of each of the second target patterns; Ravensbergen [0064] teaches measuring asymmetry in a target structure comprising a layered structure having a first component in a first layer and a second component in a second layer where asymmetry due to overlay can be measured for high resolution structures.
a same misaligned value is applied to the local misalignment based on pattern matching; Ravensbergen [0093] teaches applying a known bias to the asymmetry where typically the bias will be larger than the asymmetry that it is desired to measure to provide higher sensitivity measurements.
In regards to claim 15, (Ravensbergen) shows the method of claim 1:
wherein the semiconductor device comprises: a semiconductor layer that comprises a cell array region and a cell extension region on a side of the cell array region in a first horizontal direction; Ravensbergen [0065] teaches wafer may include a plurality of dies having repeatable pattern features where one or more layers formed on a wafer may be patterned or unpatterned.
a plurality of first structures on the cell array region and extending in a direction perpendicular to a top surface of the semiconductor layer; Ravensbergen [0065] teaches formation and processing of such layers of material may ultimately result in completed devices where many different types of devices may be formed on a wafer.
a plurality of second structures on the second region and extending in the direction; Ravensbergen [0065] teaches the term wafer as used herein is intended to encompass a wafer on which any type of device known in the art is being fabricated.
wherein each of the first structures comprises: a semiconductor pattern extending in the direction and contacting the semiconductor layer; and a first data storage pattern extending around a periphery of the semiconductor pattern; Ravensbergen [0119] teaches the targets described above may be metrology targets specifically designed and formed for the purposes of measurement where many devices have regular, grating-like structures.
wherein each of the second structures comprises: an insulation structure extending in the direction and contacting the semiconductor layer; and a second data storage pattern extending around a periphery of the insulation structure; Ravensbergen [0119] teaches the ability to measure high resolution targets means the embodiments may also be applied to targets that are functional parts of devices formed on the substrate.
In regards to claim 16, (Ravensbergen) shows the method of claim 15:
wherein the plurality of regions of interest comprise; a first region of interest that comprises a semiconductor pattern and a first data storage pattern which are adjacent to a boundary between the cell array region and the cell extension region; Ravensbergen [0061] teaches target comprises four gratings positioned closely together so that they will all be within a measurement scene or measurement spot formed by the metrology radiation illumination beam.
a second region of interest that comprises at least one of a plurality of second target patterns repeated in the cell extension region; Ravensbergen [0061] teaches gratings may have differently biased overlay offsets in order to facilitate measurement of overlay between the layers in which the different parts of the composite gratings are formed.
In regards to claim 17, (Ravensbergen) does not show a computing device comprising: a plurality of processors, at least one processor of the plurality of processors configured to perform a method of correcting a design layout of a semiconductor device, the method comprising: measuring misaligned values of a portion of points of a target pattern of each of a plurality of regions of interest in a semiconductor device fabricated based on an original layout; estimating misaligned values of unmeasured points of the target pattern using an artificial neural network trained based on the measured misaligned values of the portion of points; generating a target layout of the semiconductor device using the estimated misaligned values;
Manassen teaches a plurality of processors, at least one processor of the plurality of processors configured to perform a method of correcting a design layout of a semiconductor device, the method comprising: Manassen [0035] teaches controller includes one or more processors configured to execute program instructions maintained on a memory medium where the one or more processors of controller may execute any of the various process steps described. Manassen [0036] teaches the one or more processors may include any processing element known in the art including any microprocessor-type device configured to execute algorithms and instructions where the controller may include one or more controllers housed in a common housing or within multiple housings.
Manassen teaches measuring misaligned values of a portion of points of a target pattern of each of a plurality of regions of interest in a semiconductor device fabricated based on an original layout; Manassen [0083] teaches metrology measurements associated with metrology target elements on layers of the sample may include overlay measurements, critical dimension measurements, sidewall angles, film thicknesses.
Manassen teaches estimating misaligned values of unmeasured points of the target pattern using an artificial neural network trained based on previously measured misaligned values of the portion of points; Manassen [0080] teaches neural networks, support-vector machines, dimensionality-reduction algorithms including principal component analysis, independent component analysis, local-linear embedding for data analysis and fitting.
Manassen teaches generating a target layout of the semiconductor device using the estimated misaligned values; Manassen [0067] teaches determining layer-specific imaging configurations of an imaging device to image metrology target elements on two or more sample layers of a sample within a selected image quality tolerance. Manassen [0083] teaches metrology measurements associated with metrology target elements on layers of the sample may include overlay measurements, critical dimension measurements, sidewall angles, and film thicknesses.
The motivation to combine Ravensbergen and Manassen at the effective filing date of the invention is to implement neural network-based semiconductor correction on computing platforms, as both references address computational metrology systems and a person of ordinary skill would be motivated to execute machine learning algorithms on processors for real-time layout correction in manufacturing environments.
In regards to claim 18, (Ravensbergen) does not show the computing device of claim 17, further comprising: a random access memory; wherein at least one processor of the plurality of processors is configured to load program codes of the artificial neural network to the random access memory and to execute the loaded program codes;
Manassen teaches a random access memory; wherein at least one processor of the plurality of processors is configured to load program codes of the artificial neural network to the random access memory and to execute the loaded program codes; Manassen [0037] teaches memory medium may include any storage medium known in the art suitable for storing program instructions executable by the associated one or more processors including read-only memory, random access memory, magnetic or optical memory device.
The motivation to combine Ravensbergen and Manassen at the effective filing date of the invention is to optimize memory usage for neural network execution in semiconductor metrology systems, as both references address computational implementation of measurement algorithms and a person of ordinary skill would be motivated to efficiently load and execute neural network code for real-time manufacturing applications.
In regards to claim 19, (Ravensbergen) shows:
A method of fabricating a semiconductor device, the method comprising: generating an original layout associated with a design of a semiconductor device; Ravensbergen [0034] teaches lithographic apparatus includes an illumination system configured to condition a radiation beam, a support structure constructed to support a patterning device configured to impart a pattern to the radiation beam.
generating a first corrected layout by estimating misaligned values of patterns of the semiconductor device fabricated based on the original layout; Ravensbergen [0052] teaches in order that the substrates that are exposed by the lithographic apparatus are exposed correctly and consistently, it is desirable to inspect exposed substrates to measure properties such as overlay errors between subsequent layers.
generating a second corrected layout by performing optical proximity correction and position correction on the first corrected layout; Ravensbergen [0037] teaches the pattern imparted to the radiation beam may not exactly correspond to the desired pattern in the target portion of the substrate if the pattern includes phase-shifting features or assist features.
generating a mask using the second corrected layout; and fabricating a target semiconductor device using the mask; Ravensbergen [0036] teaches the support structure supports the patterning device and holds the patterning device in a manner that depends on the orientation of the patterning device and the design of the lithographic apparatus. Ravensbergen [0034] teaches projection system configured to project a pattern imparted to the radiation beam by patterning device onto a target portion of the substrate.
Ravensbergen differs from the claimed invention in that it does not explicitly disclose wherein an artificial neural network trained based on previously measured misaligned values of patterns is used to estimate the misaligned values of the patterns of the semiconductor device;
Manassen teaches wherein an artificial neural network trained based on previously measured misaligned values of patterns is used to estimate the misaligned values of the patterns of the semiconductor device; Manassen [0080] teaches neural networks and machine-learning algorithms for data collection and fitting performed by algorithms that include modeling, optimization, and fitting.
The motivation to combine Ravensbergen and Manassen at the effective filing date of the invention is to integrate neural network-based estimation into complete semiconductor fabrication workflows, as both references address metrology within manufacturing processes and a person of ordinary skill in the art would be motivated to incorporate machine learning predictions into the design-fabrication loop for improved manufacturing yield and quality control.
In regards to claim 20, (Ravensbergen) shows the method of claim 19:
wherein the generating the first corrected layout comprises: measuring misaligned values of a portion of points of a target pattern of each of a plurality of regions of interest in the semiconductor device fabricated based on the original layout; Ravensbergen [0052] teaches metrology apparatus is used to determine the properties of the substrates and in particular how the properties of different substrates or different layers of the same substrate vary from layer to layer.
providing the first corrected layout using the estimated misaligned values; Ravensbergen [0120] teaches the lithographic apparatus may be configured to use the result of a measurement by the metrology apparatus of a structure formed by the lithographic process when performing a subsequently lithographic process to improve the subsequent lithographic process.
Ravensbergen differs from the claimed invention in that it does not explicitly disclose estimating misaligned values of unmeasured points of the target pattern using an artificial neural network trained based on the measured misaligned values of the portion of points;
Manassen teaches estimating misaligned values of unmeasured points of the target pattern using an artificial neural network trained based on the measured misaligned values of the portion of points; Manassen [0080] teaches neural networks, support-vector machines, dimensionality-reduction algorithms including principal component analysis for data analysis and fitting where data collection and fitting may be performed by algorithms that include modeling, optimization and fitting.
The motivation to combine Ravensbergen and Manassen at the effective filing date of the invention is to integrate neural network-based estimation into complete semiconductor fabrication workflows, as both references address metrology within manufacturing processes and a person of ordinary skill would be motivated to incorporate machine learning predictions into the design-fabrication loop for improved manufacturing yield and quality control.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over US20180348645A1 (Ravensbergen) in view of US20180292326A1 (Manassen) as applied in claim 1 above, respectively, and further in view of US20130304408A1 (Pandev).
In regards to claim 8, (Ravensbergen modified by Manassen) does not show the method of claim 1: wherein, in response to the estimated misaligned values being correct, the generating the target layout comprises: generating a corrected layout by correcting the original layout based on the estimated misaligned values; determining whether the corrected layout is correct based on values measured in the semiconductor device; in response to the corrected layout being correct, providing the corrected layout as the target layout;
Pandev teaches wherein, in response to the estimated misaligned values being correct, the generating the target layout comprises: generating a corrected layout by correcting the original layout based on the estimated misaligned values; Pandev [0022] teaches an optimized measurement recipe is determined by reducing the set of measurement technologies and ranges of machine parameters required to achieve a satisfactory measurement result.
Pandev teaches determining whether the corrected layout is correct based on values measured in the semiconductor device; Pandev [0053] teaches the results of the subsequent measurement analysis are compared with reference measurement results to determine if a difference between the estimated parameter values and the parameter values derived from the reference measurement is within a predetermined threshold.
Pandev teaches in response to the corrected layout being correct, providing the corrected layout as the target layout; Pandev [0054] teaches if the difference is less than a threshold value an optimized measurement recipe is provided including the reduced set of measurement technologies and machine parameter values.
The motivation to combine Ravensbergen, Manassen, and Pandev at the effective filing date of the invention is to create a complete feedback loop for semiconductor layout optimization, where Ravensbergen provides measurement capabilities, Manassen provides neural network processing, and Pandev provides validation and optimization techniques, as all three references address semiconductor manufacturing improvement and a person of ordinary skill would be motivated to combine measurement, analysis, and optimization for comprehensive layout correction.
Response to Argument
Applicant's arguments filed on February 27, 2026 have been fully considered but they are not persuasive.
Applicant argues that Ravensbergen does not measure misaligned values of a portion of points of a target pattern because Ravensbergen measures overlay via interferometric intensity rather than point-by-point spatial deviation. The examiner respectfully disagrees. Ravensbergen [0052] explicitly teaches measuring overlay errors between subsequent layers of exposed substrates. Overlay error is a misaligned value under the broadest reasonable interpretation of the claim. The claim does not require a specific measurement mechanism, only that misaligned values are measured. The underlying optical method Ravensbergen uses to obtain that measurement does not remove it from the scope of the claimed limitation.
Applicant further argues that Manassen's neural network is not trained on previously measured misaligned values of a portion of points. The examiner respectfully disagrees. The word "previously" adds no structural or functional limitation that distinguishes the claimed invention from the prior art. In any neural network training workflow, measurement data must be collected before training occurs. This temporal ordering is inherent to the claimed method itself, as the measuring step necessarily precedes the estimating step. Manassen [0080] teaches neural networks and machine-learning algorithms for data collection and fitting performed by algorithms that include modeling, optimization, and fitting, which directly corresponds to a neural network trained on measurement data collected prior to training.
With respect to claim 13, the amendment corrects only a typographical error and introduces no new limitation. With respect to claims 17 and 19, the amendments mirror the same "previously measured" language added to claim 1 and fail to distinguish over the prior art for the same reasons set forth above.
Therefore, the amended claims remain unpatentable over the cited prior art combination of Ravensbergen and Manassen, and the rejections are maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANWER AHMED ALAWDI whose telephone number is (703)756-1018. The examiner can normally be reached Monday - Friday 8:00 am - 5:30 pm.
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/ANWER AHMED ALAWDI/Examiner, Art Unit 2851
/JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851