DETAILED ACTION
This Action is responsive to Claims filed 02/25/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/15/2025 was filed after the mailing date of the first Action on the merits on 11/26/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Status of the Claims
Claims 1, 3, 10, and 12 have been amended. Claims 2, 4, 11, and 13 have been cancelled. Claims 1, 3, 5-10, 12, and 14-17 are currently pending.
Response to Arguments
Applicant’s arguments, see Pages 7-9, filed 02/25/2026, with respect to Claims 1-17 have been fully considered and are persuasive. The 35 U.S.C. 101 Rejection of Claims 1-17 has been withdrawn.
Applicant’s arguments, see Page 9, filed 02/25/2026, with respect to the rejection(s) of claim(s) 1, 5-10, and 14-17 under 35 U.S.C. 102(a)(2) have been fully considered and are persuasive by the inclusion of limitations previously found in Claim 4. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made under 35 U.S.C. 103.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 3, 5-10, 12, and 14-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki et al. (US 2022/0375033 A1), hereinafter Suzuki; Alonso et al. (Elastic-DF: Scaling Performance of DNN Inference in FPGA Clouds through Automatic Partitioning, 2021), hereinafter Alonso; and Song et al. (AccPar: Tensor Partitioning for Heterogeneous Deep Learning Accelerators, 2020), hereinafter Song.
In regards to claim 1: The present invention claims: “A device for partitioning an input neural network, the device comprising:” Suzuki teaches an image processing method ([0014]) with a similarity degree estimation unit ([0066]) that partitions a network ([0067]).
“an interposing circuit configured to determine a partitioning position at which the input neural network is to be partitioned, to interpose a partitioning layer in the input neural network at the partitioning position, and to output an entire neural network that is obtained by interposing the partitioning layer in the input neural network, the input neural network including a plurality of layers;” Suzuki teaches “Next, in step S102, the similarity degree estimation unit 81 adds another layer downstream of a predetermined layer (m-th layer 22 shown in FIG. 2) in the multi-layer neural network determined according to the parameters obtained in step Sl0l. This other layer is a layer corresponding to the Network In Network (NIN). The NIN is filtering processing corresponding to I xl convolution. The NIN is known to provide a large weight to filters that extract similar features (see also NPL 4). The NIN can output a plurality of channel images, and the number of channels can be set as appropriate. It is envisioned that this number of channels is, for example, about the same as the number of split layers (here, m). However, the number of output channels does not necessarily need to be the same as the number of such layers, and the same effect is obtained in that case as well. Note that the similarity degree estimation unit 81 may randomly initialize the above-described NIN architecture based on a Gaussian distribution or the like.” ([0067]).
“a training circuit configured to train the entire neural network;” Suzuki teaches “Next, in step S52, the similarity degree estimation unit 81 performs training processing using a configuration in which a Network In Network (NIN) is provided downstream of the output layer (m-th layer 22) of the neural network in the deep feature generation unit 20 of FIG. 2.” ([0063]). Paragraphs [0068]-[0069] delve further into the training before and after the partition. See also “By doing so, the sequence determined by the pre-training unit 80 is shared by a transmission-side apparatus 2 (FIG. 2) and a reception-side apparatus 3 (FIG. 2).” ([0040]).
“and a partitioning circuit configured to divide the entire neural network into a plurality of neural network partitions by partitioning the partitioning layer.” See Figure 2 for the network being partitioned according to the above interposing of a layer between an m and m+1 layer. See also “That is, a neural network that is different from the above-described neural network is connected downstream of the intermediate layer (corresponds to them-th layer 22 in FIG. 2), and the rearrangement sequence is determined in advance based on the weights of the different neural network, which are obtained as a result of performing training processing using training data. This "different neural network" is the above-described NIN. That is, the "different neural network" performs lxl convolution processing.” ([0043]).
While Suzuki may read on an interposing circuit or unit as detailed above, Suzuki fails to explicitly teach “wherein the interposing circuit selects one of a plurality of partitioning cases to determine the partitioning position, the plurality of partitioning cases respectively corresponding to a plurality of candidate positions where the partitioning layer is to be placed,” However, Alonso, in a similar field of endeavor of partitioning execution of a NN, teaches an algorithm (Algorithm 1, Page 15:16) that optimizes different partitioning states among accelerators. See also “To support compression, the Elastic-DF partitioner must allow multiple possible implementations for each node in the DF graph, from which exactly one can be instantiated in the final design.” (Page 15:13).
“wherein the interposing circuit calculates, for each of the plurality of partitioning cases, an evaluation value using execution times of a plurality of accelerators respectively corresponding to the plurality of neural network partitions,” Page 15:13 of Alonso also goes into detail regarding the need to account for congestion and throughput between accelerators, which the examiner submits reads on the broadly-recited execution times.
“and wherein the interposing circuit selects the one of the plurality of partitioning cases based on evaluation values calculated for the plurality of partitioning cases, a candidate position corresponding the selected partitioning case being determined to be the partitioning position.” The output of the aforementioned Algorithm 1 is a tile size. Sections 4.2.2 and 4.2.3 detail how this tile size is used in solving the optimal ILP problem, and therefore partitioning scheme, using the tile size output by Algorithm 1.
Alonso highlights the benefits of their partitioning algorithm on page 15:3, including improved throughput and resource usage. It would have been obvious to one of ordinary skill in the art at the time of the Applicant’s filing to combine the beneficial algorithm of Alonso with the method of Suzuki in order to better find partitioning schemes between the encoder and decoder.
While the Examiner submits a combination of Suzuki and Alonso reads on partitioning layers between accelerators based on execution and communication, the combination fails to explicitly teach: “wherein the evaluation value is determined by summing differences between a maximum execution time among the execution times of the plurality of accelerators and each execution time as follows:
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where En indicates an evaluation value of an n-th partitioning case among the plurality of partitioning cases, k indicates a number of the accelerators, execi indicates an execution time of an i-th accelerator, and execj indicates a maximum execution time among the execution times of the plurality of accelerators.” However, Song, in a similar field of endeavor of partitioning neural network execution, teaches determining a partition point for a network based on layer wise computation of the cost at each layer (Pages 8-9, Section 5.1, Equation 9, mapping to the summation of the computational cost) as well as “ACCPAR allows the partition ratio to be adjusted for heterogeneous accelerators to balance the communication and computation costs of the individual accelerators For an accelerator with a partitioning ratio a, the computation and communication cost are both a function of a and a partitioning pi;l , i.e., Ecp(a; pi;l) and Ecm(a; pi;l). To calculate the partition ratio for achieving the best performance, we need to find the ratio to balance the sum of computation cost and communication cost among two accelerator groups.” (Page 9, Section 5.3). Section 5.2 (Page 9) also delves into this computation regarding multiple paths between layers, further indicating a minimization of the cost of computing at a specific layer. Song teaches “…our method can avoid the drawbacks of existing approaches that use communication as a proxy of the performance. The enhanced flexibility of tensor partitioning in ACCPAR allows the flexible ratio of computations to be distributed among accelerators with different performances. The proposed search algorithm is also applicable to the emerging multi-path patterns in modern DNNs such as ResNet.” (Abstract). It would have been obvious to one of ordinary skill in the art at the time of the Applicant’s filing to incorporate the evaluation of a partition point from Song into a combination of Suzuki and Alonso for the enhanced flexibility of partitioning between accelerators provided by Song.
In regards to claim 3: The present invention claims: “wherein each of the execution times includes a computation time at a corresponding accelerator and a data transmission time at the corresponding accelerator.” See above where Alonso factors throughput (which the Examiner submits necessarily contains execution time for a given accelerator) and data congestion (data transmission time).
In regards to claim 5: The present invention claims: “wherein the partitioning layer includes an encoding layer to encode input data and output encoded data and a decoding layer to decode the encoded data, and wherein a size of the encoded data is smaller than a size of the input data.” See Suzuki Figure 2 for the encoding and decoding (items 41 and 42) occurring at the partition. See also “The coding unit 41 compresses and codes the plurality of frame images rearranged in the second sequence using a compression coding method based on a correlation between the frames. In other words, the coding unit 41 regards the above-described intermediate output value as a frame, and compresses and codes a plurality of the intermediate output values rearranged in the second sequence using a compression coding method based on the correlation between the frames.” ([0051], mapping to smaller than the input).
In regards to claim 6: The present invention claims: “wherein the partitioning circuit divides the entire neural network so that the encoding layer and the decoding layer are included in different neural network partitions.” See Suzuki Figure 2 for the encoder and decoder being in different partitions. See also “The image transmission unit 40 includes the coding unit 41 and a decoding unit 42. It is envisioned that the coding unit 41 and the decoding unit 42 are at locations that are remote from each other.” ([0050]).
In regards to claim 7: The present invention claims: “wherein each of the encoding layer and the decoding layer is a fully connected neural network or a convolutional neural network.” Suzuki teaches “In the first embodiment, the rearrangement unit 30 performed rearrangement and the coding unit 41 performed coding using each channel of the deep features generated by the deep feature generation unit 20 as one frame (see FIG. 11B).” ([0109], mapping to fully-connected if the encoder uses every channel).
In regards to claim 8: The present invention claims: “wherein when the input neural network is a pre-trained neural network, the training circuit performs first phase training by adjusting weights of the partitioning layer with weights of the pre-trained input neural network.” Suzuki teaches “In the configuration of FIG. 1, the rearrangement sequence estimated by the pre-training unit 80 through training is used during inference ( during image processing). That is, in the configuration of FIG. 1, the timing at which the pre-training unit 80 operates and the timing at which the other parts in the image processing system 1 operate are different from each other. The functions of the units are as follows.” ([0038]).
In regards to claim 9: The present invention claims: “wherein the training circuit further performs second phase training by adjusting weights of the entire neural network after the first phase training is completed.” Suzuki teaches “As will be described later, the similarity degree estimation unit 81 provides a Network In Network (NIN) downstream of the layer that is the output from the deep feature generation unit 20. The similarity degree estimation unit 81 performs machine learning processing using the multi-layer neural network in which this NIN is introduced and the above-described training data.” ([0041], this is machine learning processing separate from the aforementioned pretraining, and pertains to the entire network, including over the partitioning layer).
In regards to claims 10, 12, and 14-17: Claims 10, 12, and 14-17 recite similar limitations to claims 1, 3, 5-6, and 8-9, with the exception of “A method for partitioning an input neural network, the method comprising:” of claim 10; therefore, both sets of claims are similarly rejected.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GRIFFIN T BEAN whose telephone number is (703)756-1473. The examiner can normally be reached M - F 7:30 - 4:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Li Zhen can be reached at (571) 272-3768. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GRIFFIN TANNER BEAN/ Examiner, Art Unit 2121
/Li B. Zhen/ Supervisory Patent Examiner, Art Unit 2121
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