DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 lacks proper antecedent basis for “the area of the connection surface”.
Claim 3 lack proper antecedent basis for “the same ceramic material”.
Claim 4 lacks proper antecedent basis for “the area of the upper surface” and “the area of the lower surface”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4 and 5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ito (JP 2001-230306).
With respect to claim 1, Ito discloses a structure of the wafer placement table claimed including a ceramic substrate (12) having a wafer placement surface, a first electrically conductive layer (18) embedded in the ceramic substrate, an electrically conductive via (shown by holes 14/26 having a columnar shape; para 0019) having a conductive material (para 0027) which includes a plurality of columnar members (as illustrated in Figure 2) connected together in a vertical direction wherein an area of a connection surface of one of two columnar members connected to each other is a larger than the area of the connection surface of the other. Also, see annotated drawing below.
PNG
media_image1.png
246
638
media_image1.png
Greyscale
With respect to claim 2, Ito disclose the ceramic structure that is a multilayer structure shown by a plurality of ceramic sheets/layers (L1-L6) with a connection surface of each of the columnar members located between the corresponding layers.
With respect to claim 4, Ito discloses a structure of the wafer placement table claimed including a ceramic substrate (12) having a wafer placement surface, a first electrically conductive layer (18) embedded in the ceramic substrate, an electrically conductive via (shown by holes 14/26 having a columnar shape; para 0019) having a conductive material (para 0027) which includes a plurality of columnar members (as illustrated in Figure 2), an intermediate member having an upper surface and a lower surface wherein an area of the upper surface and an area of the lower surface are larger than an area of connection surface of the columnar members that are joined to the respective upper and lower surface of the intermediate member, and Ito shows a ceramic layer having a thickness about .1 to 5 mm (para 0032) wherein the intermediate that is formed in a via of the ceramic layer would also have a thickness of .1 to 5 mm that encompasses the claimed range of .1 mm or more. Also, see annotated drawing below.
PNG
media_image2.png
245
604
media_image2.png
Greyscale
With respect to claim 5, Ito discloses that the ceramic substrate is a multilayer structure wherein the intermediate member is located between layers of the multilayer structure body.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ito (JP 2001-230306) in view of Fukuzono et al (US 2021/0066180).
With respect to claim 3, Ito discloses the wafer placement table claimed including the plurality of columnar members but does not disclose the columnar members containing a same ceramic material wherein a content of the ceramic material in one of the columnar members having the larger connection surface is larger than the other that has a smaller area of the connection surface as claimed.
Fukuzono discloses a ceramic substrate (1) having a plurality of columnar members shown by via conductors (12 and 13) wherein the columnar members contain a same ceramic material wherein one (13) of the via conductors having a larger connection surface has as a ceramic content ratio that is higher than the other via conductor having a smaller connection area (para 0046). Fukuzono discloses that a resistance difference between the one (13) of the via conductor and the other via conductor is reduced which also reduces any stress when an external force is applied to the substrate (1). Also, see para 0044 and 0046.
In view of Fukuzono, it would have been obvious to one of ordinary skill in the art to adapt Ito with the columnar member having a larger connection surface area to contain a larger amount/content of a ceramic material than the columnar member with a smaller connection surface area so that any external force or stress on the ceramic substrate of the wafer placement table can be reduced by dispersing the stress thru the larger connection surface area.
With respect to claim 6, Ito discloses the plurality of columnar members with an intermediate layer having the larger upper and lower connection surface wherein as Fukuzono discloses an intermediate member (13) having a larger connection surface area with a higher content of the ceramic material, it would have been obvious to one of ordinary skill in the art to adapt Ito with the intermediate member having a larger amount/content of a ceramic material than the columnar member so that any external force or stress on the ceramic substrate of the wafer placement table can be reduced by dispersing the stress thru the intermediate member.
Claim(s) 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ito (JP 2001-230306) in view of Takebayashi (US 2017/0280509).
Ito discloses the wafer placement table claimed including the first electrically conductive layer (18) as a heater electrode but does not show a second electrically conductive layer located on a lower side of the first electrically conductive layer wherein the electrically conductive via is connected at the other end to the second electrically conductive layer.
Takebayashi discloses a first electrically conductive layer such as a heater electrode (34) and a second electrically conductive layer such as a jumper (36) wherein an electrically conductive via (V1) is connected therebetween as illustrated in Figure 3.
In view of Takebayashi, it would have been obvious to one of ordinary skill in the art to adapt Ito with a second electrically conductive layer as a jumper that provides for an electrical power route or connection that connects the first electrically conductive layer such as a heater electrode to a power source via the second electrically conductive layer such a jumper layer as known in the art.
Claim(s) 9 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ito in view of Fukuzono as applied to claim 6 and further in view of Takebayashi (US 2017/0280509).
Ito in view of Fukuzono discloses the wafer placement table claimed including the first electrically conductive layer (18) as a heater electrode but does not show a second electrically conductive layer located on a lower side of the first electrically conductive layer wherein the electrically conductive via is connected at the other end to the second electrically conductive layer.
Takebayashi discloses a first electrically conductive layer such as a heater electrode (34) and a second electrically conductive layer such as a jumper (36) wherein an electrically conductive via (V1) is connected therebetween as illustrated in Figure 3.
In view of Takebayashi, it would have been obvious to one of ordinary skill in the art to adapt Ito, as modified by Fukuzono, with a second electrically conductive layer as a jumper that provides for an electrical power route or connection that connects the first electrically conductive layer such as a heater electrode to a power source via the second electrically conductive layer such a jumper layer as known in the art.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANG Y PAIK whose telephone number is (571)272-4783. The examiner can normally be reached 9:00-5:30; M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Helena Kosanovic can be reached at 571-272-9059. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SANG Y PAIK/Primary Examiner, Art Unit 3761