DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to claims filed 10/24/2022.
Claims 1, 3-11, and 13-20 are pending. Claims 2 and 12 are cancelled.
Response to Arguments
Regarding 35 U.S.C. 112:
Applicant’s amendments and arguments regarding the rejection of claims 7, 16, and 20 under 35 U.S.C. 112(b) have been fully considered and are found to be persuasive. The rejections of claims 7, 16, and 20 under 35 U.S.C. 112(b) are withdrawn.
Regarding: Prior Art Rejections:
Applicant’s amendments and arguments regarding the rejection of claims 1-20 under 35 U.S.C. 103 have been fully considered and are moot due to new grounds of rejection necessitated by amendment. The rejections of claims 2 and 12 are withdrawn due to claim cancellation.
Regarding Double Patenting:
Applicant’s amendments and arguments regarding the rejection of claims under Double patenting have been fully considered and are found to be persuasive. Applicant’s amended claims are found to be distinct from Reference Patent US 11481206 B2.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6, 7, 10, 11, 12, 15, 16, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Marr et al. US 9176752 B1 in view of Kato US 20050193260 A1 in view of Lee et al. US 20130205298 A1.
Marr is cited in a previous office action.
Regarding claim 1, Marr teaches the invention substantially as claimed including:
A computing device comprising:
memory including a system management memory region (the memory of the server accessible only during the update operation, such as system management random access memory (SMRAM), Col 2 30-32); and
a processor system including a plurality of processor threads (all processor threads, Col 3 48-49), wherein the processor system is configured to:
suspend execution of one or more processor threads of the plurality of processor threads (suspend all processor threads, Col 3 48-49);
store one or more respective processor thread contexts of the one or more processor threads in the memory (temporary storage of the state of the processor immediately prior to suspension of instruction execution, Col 2 27-28; storing a “snapshot” state of the processor just prior to entering SMM, Col 4 4);
enter a system management mode (SMM) (placing the processor in SMM, Col 3 49);
execute an update query system management interrupt (SMI) handler to determine that the system management memory region includes a code update instruction (upon entering SMM, the processor is then configured to execute the code associated with the interrupt handler (e.g., SMI handler) of the firmware 112. The code associated with the interrupt handler may include, … routines to retrieve and/or invoke update code stored remotely or in local memory, routines to directly modify and/or overwrite data storage locations, whether logical or physical, containing the code to be updated, and the like., Col 3 65- Col 4 9);
perform a code update based on the code update instruction (Upon successful application of the update code, Col 5 6-7; updating the portion of the trusted computing base using the authenticated update, Claim 1),
exit the SMM; retrieve the one or more processor thread contexts from the memory; and resume execution of the one or more processor threads without rebooting the computing device (the SMI handler may execute and/or issue an instruction to the processor to resume execution from the point where all the processor threads were interrupted, Col 5 7-9; a state corresponding to that of the entire processor may be generated and stored within SMRAM so as to both protect the state from external tampering or corruption, as well as to provide for a seamless resumption of normal operation after SMM is exited, Col 4 24-29).
Marr does not explicitly teach: determine that the system management memory region includes a code update instruction at least in part by querying a lookup table indicating a respective location in the memory of each of a plurality of SMI handlers included in an SMI handler list;
wherein performing the code update includes: modifying the SMI handler list; and executing the plurality of SMI handlers in the modified SMI handler list;
wherein the code update instruction includes an instruction to modify the SMI handler list at least in part by adding an additional SMI handler to the SMI handler list or removing an SMI handler included among the plurality of SMI handlers from the SMI handler list;
However, Kato teaches determine that the system management memory region includes a code update instruction at least in part by querying a lookup table indicating a respective location in the memory of each of a plurality of SMI handlers included in an SMI handler list (Fig 3 interrupt level correspondence table; Fig 4 interrupt handler table; [0079] The interrupt handling task 140 obtains, from the interrupt handler table 170, the address of the interrupt handler 150 that is supposed to handle the interrupt that occurred);
wherein performing the code update includes: modifying the SMI handler list ([0060] The interrupt initialization unit 110 initializes the interrupt control program; and more specifically, it initializes the interrupt level correspondence table 160 and creates the interrupt handling tasks 140); and executing the plurality of SMI handlers in the modified SMI handler list ([0064] Each of the interrupt handlers 150 are a processing unit that is invoked by the interrupt task 140 and actually performs interrupt handling. The interrupt handlers 150 are created by a developer of a device driver and are previously stored in the OS);
wherein: the code update instruction includes an instruction to modify the SMI handler list at least in part by adding an additional SMI handler to the SMI handler list or removing an SMI handler included among the plurality of SMI handlers from the SMI handler list ([0063] The interrupt handling tasks 140 are created by the interrupt initialization unit 110 and the number of interrupt handling tasks 140 corresponds to that of causes of interrupts, and the interrupt handler tasks 140 each activate one of the interrupt handlers 150 corresponding to the causes of interrupts, respectively, to perform interrupt handling);
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined Kato’s interrupt handler system with the system of Marr. A person of ordinary skill in the art would have been motivated to make this combination to provide Marr’s system with the advantage of organizing managing interruption handlers for faster recovery (see Kato [0002] an interrupt control method, such that the interrupt handling is fast, and a number of modifications in the interrupt control program, required for adapting to a different interrupt controller, are less).
Marr and Kato do not explicitly teach the modified SMI handler list includes a handler override indicating the modification of the SMI handler list by the adding of the additional SMI handler or the removing of the SMI handler.
However, Lee teaches the modified SMI handler list includes a handler override indicating the modification of the SMI handler list by the adding of the additional SMI handler or the removing of the SMI handler (Claim 1 an internal memory comprising a dirty bit indicating a changed memory area).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined Lee’s dirty bit with the system of Marr and Kato. A person of ordinary skill in the art would have been motivated to make this combination to provide Marr and Kato’s system with the advantage of indicating changed memory for improved runtime memory management (see Lee [0049] a dirty bit indicating a changed memory area so that only the data actually being used by the task is stored or restored, and may store only a portion which is changed during the overlay in an external memory.).
Regarding claim 6, Marr, Kato, and Lee teach the computing device of claim 1.
Marr further teaches wherein the processor system is further configured to execute one or more virtual machines concurrently with the SMM (numerous technological advantages are achieved, such as the ability to update hypervisors without evicting or otherwise shutting down virtual machines or applications operating on computer hardware, Col 5 14-17).
Regarding claim 7, Marr, Kato, and Lee teach the computing device of claim 1.
Kato further teaches wherein during execution of the update query SMI handler, the processor system queries the lookup table for the code update instruction from the lookup table ([0084] The interrupt acceptance unit 120 masks the interrupt that occurred (step S143), obtains the corresponding interrupt handling task ID from the interrupt level correspondence table 160 (step S144), and activates the interrupt handling task 140 with the interrupt handling task ID obtained (step S145)).
Regarding claim 10, Marr, Kato, and Lee teach the computing device of claim 1.
Marr further teaches wherein the execution of the one or more processor threads is resumed without receiving the one or more processor thread contexts from an additional computing device (just prior to or in the process of entering SMM, a state corresponding to that of the entire processor may be generated and stored within SMRAM so as to both protect the state from external tampering or corruption, as well as to provide for a seamless resumption of normal operation after SMM is exited, Col 4 24-29).
Regarding claims 11, 15, 16, and 19, they are the methods of claims 1, 6, 7, and 10 respectively. Therefore, they are rejected for the same reasons as claims 1, 6, 7, and 10 respectively.
Claims 3 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Marr et al. US 9176752 B1 in view of Kato US 20050193260 A1 in view of Lee et al. US 20130205298 A1 in further view of Ebsen et al. US 20030217310 A1.
Regarding claim 3, Marr, Kato, and Lee teach the computing device of claim 1.
Marr, Kato, and Lee do not explicitly teach wherein the code update instruction includes an instruction to reinitialize at least a part of a memory controller of the memory.
However, Ebsen teaches the code update instruction includes an instruction to reinitialize at least a part of a memory controller of the memory (A method for reinitializing firmware in the event of a fault in a storage area network comprising at least one storage controller having programmable memory and random access memory (RAM), said at least one storage controller for controlling data access between at least one host server and a storage device, Claim 1).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined Ebsen’s method of reinitializing of a storage controller following a fault with the system of Marr, Kato, and Lee. A person of ordinary skill in the art would have been motivated to make this combination to provide Marr, Kato, and Lee’s system with the advantage of reducing downtime following a system fault improving system recovery (see Ebsen [0013] the inventive method and apparatus reduce the downtime for repair and maintenance when a fault is detected. Furthermore, in one embodiment, failure tracking is also provided by identifying and recording the types of faults detected, which may be subsequently used as reference information and fault tracking. In another embodiment, the reinstalled version of firmware may be an upgrade version, thereby resolving the detected fault, as well as providing a firmware upgrade).
Regarding claim 13, it is the method of claim 3. Therefore, it is rejected for the same reasons as claim 3.
Claims 4, 8, 9, 14, 17, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Marr et al. US 9176752 B1 in view of Kato US 20050193260 A1 in view of Lee et al. US 20130205298 A1 in further view of Jayakumar et al. US 9311138 B2.
Regarding claim 4, Marr, Kato, and Lee teach the computing device of claim 1.
Marr, Kato, and Lee do not explicitly teach wherein the code update instruction includes an instruction to: change a multithreading setting of the processor system; or enable or disable a core of the processor system.
However, Jayakumar teaches wherein the code update instruction includes an instruction to: change a multithreading setting of the processor system; or enable or disable a core of the processor system (Upon acquiring the master thread lock 210, the master thread 204 may set the in-progress flag 208, Col 6 2-3; The SMI handler 212 is configured to handle SMI interrupts. As described in detail below, the SMI handler 212 manages the in-progress flag 208, Col 6 7-9; A processor core entering SMM may immediately resume normal execution upon determining the in-progress flag is not set and the service pending flag is not set, to detect and mitigate spurious SMIs, Abstract).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined Jayakumar’s control of processing cores with the system of Marr, Kato, and Lee. A person of ordinary skill in the art would have been motivated to make this combination to provide Marr, Kato, and Lee’s system with the advantage of improved core synchronization during interrupts of multi-core processors (see Jayakumar Col 1 32-43, Certain multi-core processors may handle an SMI by broadcasting the SMI to all processor cores. Upon receiving the SMI and entering SMM, each processor core may race to become the master core responsible for handling the SMI. Such master core is often called the “monarch” or the “boot strap processor.” The master core waits for the other, subordinate cores (sometimes called “application processors”) to enter SMM before handling the SMI. While the master core handles the SMI, the subordinate cores idle in a wait loop. Thus, SMI handler code may be single-threaded even when executed on multi-core processors.).
Regarding claim 8, Marr, Kato, and Lee teach the computing device of claim 1.
Marr, Kato, and Lee do not explicitly teach wherein the processor system is further configured to: designate a processor thread selected from among the plurality of processor threads as a monarch thread; and execute the plurality of SMI handlers at the monarch thread.
However, Jayakumar teaches wherein the processor system is further configured to: designate a processor thread selected from among the plurality of processor threads as a monarch thread (The master thread lock 210 is a synchronization mechanism used to select one of the threads 202 as the master thread 204. As described in detail below, upon entering SMM, the threads 202 may race to acquire the master thread lock 210, with the winner of the race becoming the master thread 204, Col 5 64 - Col 6 1); and execute the plurality of SMI handlers at the monarch thread (The master thread 204 may handle such SMIs by calling appropriate sub-handlers (not illustrated), Col 8 30-31).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined Jayakumar’s master thread’s coordinating of SMI handling with the system of Marr, Kato, and Lee. A person of ordinary skill in the art would have been motivated to make this combination to provide Marr, Kato, and Lee’s system with the advantage of improving SMI handling latency and scalability with number of processing cores (see Jayakumar Col 3 42-52, By initiating handling of the SMI without waiting for other processor cores to enter SMM, the processor 102 reduces latency for handling SMIs and increases scalability of SMI handling with increased core count. Directing the other processor cores to handle SMIs allows for handling SMIs originating from particular processor cores, because information relating to such SMIs is available only in the processor core that originated the SMI. Detecting spurious SMIs further reduces latency and improves scalability of SMI handling. Such improved latency and scalability may allow SMI-based handling of machine check exceptions).
Regarding claim 9, Marr, Kato, Lee, and Jayakumar teach the computing device of claim 8.
Jayakumar further teaches wherein by executing the monarch thread, the processor system is further configured to assign the plurality of SMI handlers to respective processor threads of the plurality of processor threads (The master SMI handler may direct the subordinate SMI handlers to handle core-specific SMIs, Abstract).
Regarding claims 14, 17, and 18, they are the methods of claims 4, 8, and 9 respectively. Therefore, they are rejected for the same reasons as claims 4, 8, and 9 respectively.
Regarding claim 20, it is the computing device of claim 1 reciting elements from claims 8. Therefore, it is rejected for the same reasons as claims 1 and 8.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Marr et al. US 9176752 B1 in view of Kato US 20050193260 A1 in view of Lee et al. US 20130205298 A1 in view of Ramgarajan et al. US 20080222449 A1.
Regarding claim 5, Marr, Kato, and Lee teach the computing device of claim 1.
Marr, Kato, and Lee do not explicitly teach the code update instruction includes an instruction to modify a memory usage model of the memory; and the modification to the memory usage model includes a modification to a size and/or a location of a mirrored address range in the memory.
However, Ramgarajan teaches the code update instruction includes an instruction to modify a memory usage model of the memory; and the modification to the memory usage model includes a modification to a size and/or a location of a mirrored address range in the memory ([0005] the SMI handler uses logged errors to initiate error handling functions such as spare memory copy and memory RAID/mirroring. For example, spare memory copy, also known as sparing, switches to a spare rank of memory when a threshold number of correctable errors are detected. Sparing helps prevent uncorrectable errors that will hang the information handling system by relying on memory within the system that is not associated with logged errors).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined Ramgarajan’s error handling functions with the system of Marr, Kato, and Lee. A person of ordinary skill in the art would have been motivated to make this combination to provide Marr, Kato, and Lee’s system with the advantage of preventing preventable memory errors through a variety of interrupt methods (see Ramgarajan [0005] an SMI handler running in BIOS on a server information handling system chipset typically maintains logs of correctable memory errors, uncorrectable memory errors, PCI and PCI-E errors and chipset errors. Typically, multiple correctable errors in a system are a precursor to uncorrectable errors, so the SMI handler uses logged errors to initiate error handling functions such as spare memory copy and memory RAID/mirroring.).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/H.L./
Examiner, Art Unit 2195
/Aimee Li/Supervisory Patent Examiner, Art Unit 2195
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