DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The prior art documents submitted by applicant in the Information Disclosure Statements filed 05/08/2023 and 01/21/2026 have all been considered and made of record.
Joint Inventors
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Response to Amendments
Applicant’s amendment filed 12/29/2025 has been considered and entered.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Doyle (US 8995801 B2) in view of Vernooy (US 8588558 B2).
With regards to claim 1, Doyle discloses a parallel optical interconnect, comprising:
a first transceiver (Doyle/Fig2/First transceiver 234);
a second transceiver (Fig2/Second transceiver 238);
a flexible substrate comprised of a laminate of dielectric layers and metallic layers (Fig1/Laminate of dielectric layers and metallic layers 100; Column 2/Lines 49-50 [ “…flexible…” ]), at least one of the metallic layers patterned to form electrical transmission lines between the first transceiver and the second transceiver (Figs1&2/Electrical transmission lines 210); and
a plurality of waveguides in the flexible substrate, the waveguides being part of an optical link between the first transceiver and the second transceiver (Figs1&2/Waveguides 206):
wherein the waveguides form two or more layers of waveguides (Fig3/Two or more layers of waveguides [First and second waveguide layers on the top and bottom of element 336 respectively]);
wherein at least two of the layers of waveguides are separated by a one of the metallic layers patterned to form electrical transmission lines (Fig3/Electrical transmission line 336).
Doyle is silent regarding
the first transceiver including a plurality of first microLEDs and a plurality of first photodetectors, the first photodetectors monolithically integrated on a first silicon integrated circuit and the first microLEDs on the first silicon integrated circuit; and
the second transceiver including a plurality of second microLEDs and a plurality of second photodetectors, the second photodetectors monolithically integrated on a second silicon integrated circuit and the second microLEDs on the second silicon integrated circuit.
However, the practice of linking an optical interconnect to first and second transceivers inclusive of the above structural characteristics exists in the art as exemplified by Vernooy.
Doyle and Vernooy are considered to be analogous in the field of optical interconnects. Doyle discloses a parallel optical interconnect with a first and second transceiver. Vernooy discloses a first transceiver including a plurality of first microLEDs and a plurality of first photodetectors, the first photodetectors monolithically integrated on a first silicon integrated circuit and the first microLEDs on the first silicon integrated circuit and a plurality of second microLEDs and a plurality of second photodetectors, the second photodetectors monolithically integrated on a second silicon integrated circuit and the second microLEDs on the second silicon integrated circuit (Vernooy/Figs2&3/First and second silicon integrated circuits 56 and 60; Pluralities of first and second microLEDs and pluralities of first and second photodetectors 30 and 50 respectively; Column 7/Lines 14-23 and Lines 45-48). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the parallel optical interconnect of Doyle such that it interfaced with transceivers each comprising a plurality of microLEDs and a plurality of photodetectors as suggested by Vernooy since doing so would facilitate two-way transmission of optical signals through the interconnect.
With regards to claim 2, Doyle and Vernooy together disclose the parallel optical interconnect of claim 1, wherein the waveguides comprise waveguide cores on cladding (Doyle/Fig3/Cladding 320 and 355).
With regards to claim 11, Doyle and Vernooy together disclose the parallel optical interconnect of claim 1, wherein the first silicon integrated circuit includes first drivers for the first microLEDs and first electrical receiver circuitry for the first photodetectors, and the second silicon integrated circuit includes second drivers for the second microLEDs and second electrical receiver circuitry for the second photodetectors (Vernooy/First and second drivers 64; Column 6/Lines 30-37).
Claims 5 is rejected under 35 U.S.C. 103 as being unpatentable over Doyle (US 8995801 B2) and Vernooy (US 8588558 B2) as applied to claim 1 above, in further view of Li (US 20190391345 A1).
With regards to claim 5, Doyle and Vernooy together disclose the parallel optical interconnect of claim 1, but are silent regarding the waveguides having a numerical aperture between 0.2 and 0.7. However, the practice of configuring a waveguide to have a numerical aperture between 0.2 and 0.7 exists in the art as exemplified by Li.
Doyle, Vernooy, and Li are considered to be analogous in the field of optoelectronic assemblies. Li teaches waveguides having a numerical aperture of 0.2+/−0.015 (Paragraph 48/"...optical fiber, with a numerical aperture (NA) of 0.2+/−0.015."). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make use of the numerical aperture value taught by Li since a high numerical aperture with a large index difference between the core and the cladding is desired for short reach interconnects. Furthermore, considering the claimed numerical aperture range of 0.2 to 0.7 to be prima facie obvious over the numerical aperture of 0.2 taught by Li is consistent with legal precedent; “In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Claims 6 is rejected under 35 U.S.C. 103 as being unpatentable over Doyle (US 8995801 B2) and Vernooy (US 8588558 B2) as applied to claim 1 above, in further view of Nishikawa (US 20140064668 A1).
With regards to claim 6, Doyle and Vernooy together disclose the parallel optical interconnect of claim 1, but are silent regarding the waveguides being multimode waveguides for wavelengths between 400nm to 500nm. However, the practice of configuring waveguides to be multimode waveguides for wavelengths between 400nm to 500nm exists in the art as exemplified by Nishikawa.
Doyle, Vernooy, and Nishikawa are considered to be analogous in the field of optoelectronic assemblies. Nishikawa teaches that optical waveguides may be single mode or multimode in parallel optical interconnect devices (Nishikawa/Paragraph 32/Lines 1-3/“Further, the transmission mode of the optical waveguide may be any mode such as a single mode, multimode, step index mode or the like…”). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use multimode waveguides for wavelengths between 400nm to 500nm for the purpose of obtaining desired optical transmission results since multimode waveguides were known alternatives to single mode waveguides in the prior art and one of ordinary skill could have combined the elements by known coupling methods with no change in their respective functions to yield predictable results (KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007)").
Examiners Note: Additionally, the examiner notes that transmitting light of a particular wavelength, i.e.. 400 to 500 nm, is an intended use of the optical fiber unit. It has been held that “apparatus claims cover what a device is, not what a device does” (Hewlett-Packard Co. v. Bausch & Lomb Inc. 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990)); that a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all of the structural limitations of the claim (Ex parte Masham, 2 USPQ 2d 1647 (Bd. Pat. App. & Inter. 1987)); and that if a prior art structure is capable of performing the intended use as recited in the preamble, then it meets the claim (In re Schreiber, 128 F.3d 1473, 1477, 44 USPQ2d 1429, 1431 (Fed. Cir. 1997). See MPEP § 2111.02, II and MPEP § 2114, II).
Claims 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Doyle (US 8995801 B2) and Vernooy (US 8588558 B2) as applied to claim 1 above, in further view of Hung (US 20130279860 A1).
With regards to claim 12, Doyle and Vernooy together disclose the parallel optical interconnect of claim 1, but are silent regarding a first end of the waveguides being in a first connector housing, the first connector housing including a first alignment feature, wherein a second end of the waveguides is in a second connector housing, the second connector housing including a second alignment feature. However the practice of incorporating the above features into an interconnect exist in the art as exemplified by Hung.
Doyle, Vernooy, and Hung are considered analogous in the field of optoelectronic assemblies. Hung teaches a first end of a waveguide array in a first connector housing (Hung/Figure 9/elements 201 [lens cover], 210 [fiber cover], and 203 [Fiber alignment structures]), the first connector housing including a first alignment feature (Hung/Figure 7/elements 208 [Alignment pins]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply a alignment feature inclusive housing to the parallel optical interconnect taught by Doyle and Vernooy as suggested by Hung since doing so would allow for the end of the waveguide array to be substantially protected and removably alignable to the respective integrated circuit connection.
Hung does not teach a second end of a waveguide array in a second connector housing where the second connector housing includes a second alignment feature. However, the addition of a second housing to the second end of the waveguide array is a duplication of an essential working part. It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to add a second housing to the second end of the waveguide array since it has been held that duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
With regards to claim 13, Doyle, Vernooy, and Hung together disclose the parallel optical interconnect of claim 12, but do not teach the first alignment feature comprising a first connector alignment hole and the second alignment feature comprising a second connector alignment hole.
Hung does teach a first alignment feature comprising a first connector alignment pin. Since Hung also discloses an alignment hole (Hung/Figure 7/elements 102 [Alignment feature]) on the attachment surface designed to be linked to the housing (Hung/Figure 9/elements 201 [lens cover], 210 [fiber cover], and 203 [Fiber alignment structures]), it would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to invert the positions of the pins and holes with respect to the housing and attachment surface since it has been held that a reversal of the essential working parts of a device involves only routine skill in the art. In re Einstein, 8 USPQ 16.
Furthermore, the addition of a second alignment feature comprising a second connector alignment pin is a duplication of an essential working part. It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to add a second alignment feature comprising a second connector alignment pin to the second connector housing since it has been held that duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
With regards to claim 14, Doyle, Vernooy, and Hung together disclose the parallel optical interconnect of claim 13, wherein a first connector housing (Hung/Figure 9/elements 201 [lens cover], 210 [fiber cover], and 203 [Fiber alignment structures]) is on a first standoff (Hung/Figure 2/elements 301 [optoelectronic interface IC], 302 [Plurality of optoelectronic components], and 100 [Holder disposed on the substrate]) on a first silicon integrated circuit (Doyle/First silicon integrated circuit 56) and a second silicon integrated circuit (Doyle/Second silicon integrated circuit 60).
Doyle, Vernooy, and Hung are silent regarding a second connector housing on a second standoff on the second silicon integrated circuit. However, the addition of second housing and second standoff features to the second integrated circuit is a duplication of essential working parts. It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to apply second housing and second standoff to the parallel optical interconnect taught by Doyle, Vernooy, and Hung, since it has been held that duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
With regards to claim 15, Doyle, Vernooy, and Hung together disclose the parallel optical interconnect of claim 14 wherein the first standoff (Hung/Figure 2/elements 301 [optoelectronic interface IC], 302 [Plurality of optoelectronic components], and 100 [Holder disposed on the substrate]) includes a first standoff alignment hole (Figure 7/element 102 [Alignment feature]), and a first alignment pin in the first standoff alignment hole, but do not disclose first and second connector alignment holes, a second standoff including a second standoff alignment hole, or a second alignment pin in a second connector alignment hole.
However, Hung does disclose a housing-integrated alignment pin (Hung/Figure 7/element 208 [Alignment pin]) which is identical in function to the claimed first alignment pin and connector alignment hole in that it is designed to interface with a first standoff alignment hole to align and secure a housing to a standoff feature of an integrated circuit. It would have been an obvious matter of design choice to make the pins independent components rather than integrating them into the housing, since the applicant has not disclosed that the pins being removable from both the housing and standoff solves any stated problem or is for any particular purpose. It appears that the invention would perform equally well if the pins were integrated into the housing. Furthermore, the addition of second alignment pins and second standoff alignment holes is a duplication of essential working parts and precedent dictates that the duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the alignment pin and standoff alignment hole taught by Hung to both standoffs of the parallel optical interconnect taught by Doyle, Vernooy, and Hung.
Claims 1-2, 6, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Pezeshki (US 20210080664 A1) in view of Uchiumi (JP 2012209655 A).
With regards to claim 1, Pezeshki discloses a parallel optical interconnect, comprising:
a first transceiver (Pezeshki/Fig1/First transceiver 111a) including a plurality of first microLEDs and a plurality of first photodetectors (Fig2a/MicroLEDs 213a and Photodetectors 215a), the first photodetectors monolithically integrated on a first silicon integrated circuit (Fig3; Paragraph 47/Lines 9-10) and the first microLEDs on the first silicon integrated circuit (Fig3; Paragraph 47/Lines 9-10);
a second transceiver (Fig1/Second transceiver 111b) including a plurality of second microLEDs and a plurality of second photodetectors (Fig2a/MicroLEDs 213n and Photodetectors 215n), the second photodetectors monolithically integrated on a second silicon integrated circuit and the second microLEDs on the second silicon integrated circuit (Fig3; Paragraph 47/Lines 9-10);
a flexible substrate (Paragraph 81/Lines 13-14) between the first transceiver and the second transceiver; and a plurality of waveguides in the flexible substrate (Paragraph 81; “…more layers of waveguides…”), the waveguides being part of an optical link between the first transceiver and the second transceiver: wherein the waveguides form two or more layers of waveguides (Paragraph 81; “…one or more layers of waveguides…”).
Pezeshki is silent regarding the substrate comprising a laminate of dielectric layers and metallic layers, at least one of the metallic layers patterned to form electrical transmission lines, and at least two of the layers of waveguides being separated by a one of the metallic layers patterned to form electrical transmission lines. However, the practice of configuring a substrate to comprise a laminate of dielectric layers and metallic layers, at least one of the metallic layers patterned to form electrical transmission lines, wherein at least two layers of waveguides are separated by a one of the metallic layers patterned to form electrical transmission lines exists in the art as exemplified by Uchiumi.
Pezeshki and Uchiumi are considered to be analogous in the field of optoelectronic assemblies. Pezeshki discloses a parallel optical interconnect comprising a flexible substrate as previously discussed. Uchiumi teaches a laminate of dielectric layers and metallic layers, at least one of the metallic layers patterned to form electrical transmission lines (Uchiumi/Fig3; Paragraph 53/Lines 4-5), and wherein at least two layers of waveguides are separated by a one of the metallic layers patterned to form electrical transmission lines (Uchiumi/Fig3/Waveguide layers 102 and 103). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the optical interconnect of Pezeshki such that the substrate comprised a laminate of dielectric layers and metallic layers, at least one of the metallic layers patterned to form electrical transmission lines, wherein at least two of the layers of waveguides are separated by a one of the metallic layers patterned to form electrical transmission lines as suggested by Uchiumi since doing so would simultaneously allow for an insulated electrical connection between the transceivers of Pezeshki while also increasing the density of optical communication within the interconnect.
With regards to claim 2, Pezeshki and Uchiumi together disclose the parallel optical interconnect of claim 1, wherein the waveguides comprise waveguide cores on cladding (Fig6a/Core 615 and Cladding 617).
With regards to claim 6, Pezeshki and Uchiumi together disclose the parallel optical interconnect of claim 1, wherein the waveguides are multimode waveguides for wavelengths between 400 nm to 500 nm (Paragraph 47/Lines 1-7).
With regards to claim 11, Pezeshki and Uchiumi together disclose the parallel optical interconnect of claim 1, wherein the first silicon integrated circuit includes first drivers for the first microLEDs and first electrical receiver circuitry for the first photodetectors, and the second silicon integrated circuit includes second drivers for the second microLEDs and second electrical receiver circuitry for the second photodetectors (Figs2a&2b/Drivers 221; Figs2a&2c/Receiver circuitry 233).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Pezeshki (US 20210080664 A1) and Uchiumi (JP 2012209655 A) as applied to claim 1 above, in further view of Li (US 20190391345 A1).
With regards to claim 5, Pezeshki and Uchiumi together disclose the parallel optical interconnect of claim 1, but are silent regarding the waveguides having a numerical aperture between 0.2 and 0.7. However, the practice of configuring a waveguide to have a numerical aperture between 0.2 and 0.7 exists in the art as exemplified by Li.
Pezeshki, Uchiumi, and Li are considered to be analogous in the field of optoelectronic assemblies. Pezeshki and Uchiumi disclose an interconnect comprising waveguides as previously discussed. Li teaches waveguides having a numerical aperture of 0.2+/−0.015 (Paragraph 48/"...optical fiber, with a numerical aperture (NA) of 0.2+/−0.015."). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make use of the numerical aperture value taught by Li since a high numerical aperture with a large index difference between the core and the cladding is desired for short reach interconnects. Furthermore, considering the claimed numerical aperture range of 0.2 to 0.7 to be prima facie obvious over the numerical aperture of 0.2 taught by Li is consistent with legal precedent; “In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.)” (MPEP 2144.05 II A/Lines 3 and 4).
Claims 12-15 is rejected under 35 U.S.C. 103 as being unpatentable over Pezeshki (US 20210080664 A1) and Uchiumi (JP 2012209655 A) as applied to claim 1 above, in further view of Hung (US 20130279860 A1).
With regards to claim 12, Pezeshki and Uchiumi together disclose the parallel optical interconnect of claim 1. Pezeshki and Uchiumi do not explicitly disclose a first end of the waveguides is in a first connector housing, the first connector housing including a first alignment feature, and wherein a second end of the waveguides is in a second connector housing, the second connector housing including a second alignment feature. However, the practice of configuring an interconnect such that a first end of a waveguides is in a first connector housing, the first connector housing including a first alignment feature, and wherein a second end of the waveguides is in a second connector housing, the second connector housing including a second alignment feature exists in the art as exemplified by Hung.
Pezeshki, Uchiumi, and Hung are considered analogous in the field of optoelectronic assemblies. Hung teaches a first end of a waveguide array in a first connector housing (Hung/Figure 9/elements 201 [lens cover], 210 [fiber cover], and 203 [Fiber alignment structures]), the first connector housing including a first alignment feature (Hung/Figure 7/elements 208 [Alignment pins]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the alignment feature inclusive housing taught by Hung to the parallel optical interconnect taught by Pezeshki and Uchiumi since doing so would allow for the end of the waveguide array to be substantially protected and removably alignable to the respective integrated circuit connection.
Hung does not teach a second end of a waveguide array in a second connector housing where the second connector housing includes a second alignment feature. However, the addition of a second housing to the second end of the waveguide array is a duplication of an essential working part. It has been held that it has been held that duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to add a second housing to the second end of the waveguide array since doing so would allow for the second end of the waveguide array disclosed by Pezeshki, Uchiumi, and Hung to be securely attached in the same manner as the first end.
With regards to claim 13, Pezeshki, Uchiumi, and Hung together disclose the parallel optical interconnect of claim 12 as previously discussed, but do not teach the first alignment feature comprising a first connector alignment hole and the second alignment feature comprising a second connector alignment hole.
Hung does teach a first alignment feature comprising a first connector alignment pin. Since Hung also discloses an alignment hole (Hung/Figure 7/elements 102 [Alignment feature]) on the attachment surface designed to be linked to the housing (Hung/Figure 9/elements 201 [lens cover], 210 [fiber cover], and 203 [Fiber alignment structures]), it would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to invert the positions of the pins and holes of the device disclosed by Pezeshki, Uchiumi, and Hung with respect to the housing and attachment surface since it has been held that a reversal of the essential working parts of a device involves only routine skill in the art. In re Einstein, 8 USPQ 16.
Furthermore, the addition of a second alignment feature comprising a second connector alignment pin is a duplication of an essential working part. It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to add a second alignment feature comprising a second connector alignment pin to the second connector housing of the device disclosed by Pezeshki, Uchiumi, and Hung since it has been held that duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
With regards to claim 14, Pezeshki, Uchiumi, and Hung together disclose the parallel optical interconnect of claim 13, wherein the first connector housing is on a first standoff on the first silicon integrated circuit (Hung/Fig1&2/Standoff feature 100 [First standoff feature 100]). Pezeshki, Uchiumi, and Hung do not explicitly disclose a second standoff on the second silicon integrated circuit. However, the addition of a second standoff is a duplication of an essential working part. It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to add a second standoff to the second connector housing of the device disclosed by Pezeshki, Uchiumi, and Hung since it has been held that duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
With regards to claim 15, Pezeshki, Uchiumi, and Hung together disclose the parallel optical interconnect of claim 14 wherein the first standoff (Hung/Figure 2/elements 301 [optoelectronic interface IC], 302 [Plurality of optoelectronic components], and 100 [Holder disposed on the substrate]) includes a first standoff alignment hole (Hung/Figure 7/element 102 [Alignment feature]), and a first alignment pin in the first standoff alignment hole. Pezeshki, Uchiumi, and Hung are silent regarding first and second connector alignment holes, a second standoff including a second standoff alignment hole, or a second alignment pin in a second connector alignment hole. However, Hung does disclose a housing-integrated alignment pin (Hung/Figure 7/element 208 [Alignment pin]) which is identical in function to the claimed first alignment pin and connector alignment hole in that it is designed to interface with a first standoff alignment hole to align and secure a housing to a standoff feature of an integrated circuit. It would have been an obvious matter of design choice to make the pins independent components rather than integrating them into the housing, since the applicant has not disclosed that the pins being removable from both the housing and standoff solves any stated problem or is for any particular purpose. It appears that the invention would perform equally well if the pins were integrated into the housing. Furthermore, the addition of second alignment pins and second standoff alignment holes is a duplication of essential working parts and precedent dictates that the duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the alignment pin and standoff alignment hole taught by Hung to both standoffs of the parallel optical interconnect taught by Pezeshki, Uchiumi, and Hung.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Marc E Manheim whose telephone number is (703)756-1873. The examiner can normally be reached 6:30am - 5pm E.T., Monday - Tuesday and Thursday - Friday.
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/MARC E MANHEIM/Examiner, Art Unit 2874
/THOMAS A HOLLWEG/Supervisory Patent Examiner, Art Unit 2874