Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 2, and 4 are currently amended. Claims 5 and 6 are newly added. No claims have been canceled. Claims 1-6 are currently pending for examination.
Response to Arguments
As per the applicant’s arguments, pg.4, regarding the Claim Interpretation under 35 USC 112(f) and rejection of claims 1-4 under 35 USC 112(a), the examiner has considered the arguments in light of the amendment. It is believed that the amendments to the terminology reflect only the functionality of the objects, and that the terms are supported by the disclosure. As such, the claim interpretation under 35 USC 112(f) and rejection under 112(a) are withdrawn.
As per the applicant’s arguments, pgs.4-5, regarding the rejection of the application under 35 USC 103, the examiner has considered these arguments in light of the amendments. Regarding the argument that Bollu does not disclose a timer which supplies a clock signal to both hypervisor and the ‘software watchdog counter’, Bollu is only relied upon to teach a timer which supplies a clock signal to an abnormality detection function, or ‘software watchdog counter’ as amended. Bollu discloses a hardware counter, or timer, which is used to decrement the counts of both the global watchdog (monitoring the hypervisor) and local watchdogs (monitoring the individual virtual machines) ; “the subject-matter of any of Examples 1 to 7 may optionally further include a timer for providing the clock signal providing the counted pulses”, 0102 ; “Example 1 is a watchdog circuit for monitoring a plurality of virtual machines provided by one core of a plurality of cores. The watchdog circuit may include a first memory portion, a second memory portion, and a control logic configured to count a number of pulses, to, when starting the watchdog circuit, store a global watchdog counter value in the first memory portion, and to store a local counter value for each virtual machine of the one or more virtual machines in the second memory portion, and, after a predefined number of pulses, to modify the global watchdog counter value and the local counter values, and, if the global watchdog counter value fulfills a predefined global watchdog reference criterion or any of the local watchdog counter values fulfills a predefined local watchdog reference criterion, to output an error signal.”, 0095. The global watchdog Timer of Bollu monitors the clock supply of the separate hardware timer. As such, the examiner respectfully disagrees with the applicant’s arguments regarding Bollu, and the rejection of the relevant limitations under Bollu is maintained.
As per the applicant’s arguments that Kashtan does not disclose a timer which supplies a clock signal to both a hypervisor and a software watchdog timer, Kashtan is only relied upon to disclose a timer which supplies a clock signal to a hypervisor. It is agreed upon that Kashtan discloses a real-time clock device that supplies a clock to a hypervisor, and this is all that Kashtan has been claimed to disclose. As such, the rejection relying upon Kashtan is maintained.
The combination of Bollu in view of Kashtan would provide a system capable of providing a clock signal from a hardware timer to both a hypervisor and a separate, independent watchdog timer. Thus, the rejection of claims 1 and 4 under Bollu in view of Kashtan is maintained.
Additionally, a claim objection has been added for the amended language of “detecting abnormality of the plurality of virtual machines”, which should be plural “abnormalities”.
Claim Objections
Claims 1-6 are objected to because of the following informalities:
As per claims 1 and 4:
“detecting abnormality of the plurality of virtual machines” is grammatically incorrect; abnormality should be plural in the context of the sentence. Appropriate correction is required.
Any claims not mentioned above are objected to for their dependency upon an objected claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 5, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Bollu (US 20210406111 A1) in view of Kashtan (US 20220137995 A1).
As per claim 1, Bollu discloses:
the processor configured to implement a hypervisor to generate and execute a plurality of virtual machines, the hypervisor being configured to implement a software watchdog timer for detecting abnormality for the plurality of virtual machines; (“A hypervisor that may be configured to run the virtual machines may also be configured to service the watchdog system 100, in other words, to reset the hardware counter. Furthermore, the hypervisor may be configured to decrement the counters of the active virtual machine counters. Each of the virtual machines may be configured to call the hypervisor, e.g. its application programming interface, to service the software virtual machine watchdog, in other words, to reset the software counters. Furthermore, it may be the hypervisor that monitors the software watchdog counters 110 and takes appropriate action, for example if one of the counters 110 is decremented to zero.”, 0005 ; Examiner Note: monitoring the software watchdog counters and taking appropriate action equates to implementing a software watchdog timer)
a timer configured to supply a clock signal to both the hypervisor and the software watchdog timer; and (“What is referred to above as a “watchdog cycle” may mean that the control logic 220 may further be configured to perform further actions after a predefined number of pulses of a provided clock signal. The clock signal may in various embodiments be provided by a free-running timer 108, which may be part of the watchdog circuit 200, e.g. decoupled from a system clock.”, 0034 ; “the subject-matter of any of Examples 1 to 7 may optionally further include a timer for providing the clock signal providing the counted pulses”, 0102 ; “Example 1 is a watchdog circuit for monitoring a plurality of virtual machines provided by one core of a plurality of cores. The watchdog circuit may include a first memory portion, a second memory portion, and a control logic configured to count a number of pulses, to, when starting the watchdog circuit, store a global watchdog counter value in the first memory portion, and to store a local counter value for each virtual machine of the one or more virtual machines in the second memory portion.”, 0095 ; Examiner Note: the free-running timer equates to a timer)
a watchdog timer configured to detect an abnormality in the hypervisor by monitoring supply of the clock signal by the timer. (“Counters for monitoring when each of the virtual machines and the hypervisor last provided an indication that they are up and running properly may be stored in hardware memory, for example in dedicated registers.”, 0019 ; “The watchdog circuit may include a first memory portion, a second memory portion, and a control logic configured to count a number of pulses, to, when starting the watchdog circuit, store a global watchdog counter value in the first memory portion, and to store a local counter value for each virtual machine of the one or more virtual machines in the second memory portion, and, after a predefined number of pulses, to modify the global watchdog counter value and the local counter values, and, if the global watchdog counter value fulfills a predefined global watchdog reference criterion or any of the local watchdog counter values fulfills a predefined local watchdog reference criterion, to output an error signal.”, 0007 ; “In various embodiments, the storing of the global watchdog counter value and the modifying of the global watchdog counter value may be provided by a hypervisor software”, 0050 ; Examiner Note: the hypervisor providing an indication that it is up and running properly the control logic within the watchdog circuit equates to an abnormality detector which monitors pulses from free running timer, and will output an error signal – i.e., detect an anomaly in the hypervisor, when the global counter managed by the hypervisor fulfills a criterion)
Bollu discloses the above limitations of claim 1, but does not teach a clock generator configured to supply a clock signal to a virtual machine management function, nor does Bollu explicitly disclose an information processing system comprising a memory and processor.
However, Kashtan discloses:
a timer configured to supply a clock signal to both the hypervisor and the software watchdog timer; (see fig.2- RTC device 125 provides clock signal to clock component 240 of hypervisor 232)
An information processing device comprising: a memory; a processor coupled to the memory, (“A hypervisor may abstract the physical resources of a computing device such as physical processing devices (e.g., processors, CPUs, etc.) and physical memory (e.g., RAM) into virtual devices (e.g., virtual resources) which can be utilized to deploy multiple VMs.”, 0003) Kashtan
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to combine the abnormality detection for the hypervisor and VMs of a virtualized system of Bollu, with the clock signal provided to the hypervisor of Kashtan, in order to provide a system which utilizes a more reliable external hardware clock to drive the anomaly detection systems of the virtualized system, thereby removing processing burden from the virtualized system and increasing reliability.
As per claim 4, Bollu discloses:
a hypervisor configured to generate and execute a plurality of virtual machines and implement a software watchdog timer for detecting abnormality of the plurality of virtual machines (“A hypervisor that may be configured to run the virtual machines may also be configured to service the watchdog system 100, in other words, to reset the hardware counter. Furthermore, the hypervisor may be configured to decrement the counters of the active virtual machine counters. Each of the virtual machines may be configured to call the hypervisor, e.g. its application programming interface, to service the software virtual machine watchdog, in other words, to reset the software counters. Furthermore, it may be the hypervisor that monitors the software watchdog counters 110 and takes appropriate action, for example if one of the counters 110 is decremented to zero.”, 0005 ; Examiner Note: monitoring the software watchdog counters and taking appropriate action equates to implementing an abnormality detection function)
supplying, by a timer, a clock signal both to a hypervisor … and to the software watchdog timer; and (“What is referred to above as a “watchdog cycle” may mean that the control logic 220 may further be configured to perform further actions after a predefined number of pulses of a provided clock signal. The clock signal may in various embodiments be provided by a free-running timer 108, which may be part of the watchdog circuit 200, e.g. decoupled from a system clock.”, 0034 ; Examiner Note: the free-running timer equates to a clock generator)
detecting, by a watchdog timer, an abnormality in the hypervisor by monitoring supply of the clock signal by the timer. (“The watchdog circuit may include a first memory portion, a second memory portion, and a control logic configured to count a number of pulses, to, when starting the watchdog circuit, store a global watchdog counter value in the first memory portion, and to store a local counter value for each virtual machine of the one or more virtual machines in the second memory portion, and, after a predefined number of pulses, to modify the global watchdog counter value and the local counter values, and, if the global watchdog counter value fulfills a predefined global watchdog reference criterion or any of the local watchdog counter values fulfills a predefined local watchdog reference criterion, to output an error signal.”, 0007 ; “In various embodiments, the storing of the global watchdog counter value and the modifying of the global watchdog counter value may be provided by a hypervisor software”, 0050 ; Examiner Note: the control logic within the watchdog circuit equates to an abnormality detector which monitors pulses from the free running timer (108), and will output an error signal – i.e., detect an anomaly, when the global counter managed by the hypervisor fulfills a criterion)
Bollu may disclose the above limitations of claim 4, but does not teach supplying a clock signal to the virtual machine management section, or hypervisor.
However, Kashtan discloses:
supplying, by a timer, a clock signal … to a hypervisor (see fig.2 – RTC device 125 is supplying clock signal to clock component 240 of hypervisor 232 ;)
The system of Bollu in view of Kashtan would provide a clock signal to both the hypervisor which provides abnormality detection for the VMs as well as a separate software watchdog timer.
As per claim 5, Bollu in view of Kashtan fully discloses the limitations of claim 1.
Furthermore, Bollu discloses:
the timer and the watchdog timer are provided external to the hypervisor (see fig.2A- both timer 108 and control logic 220 are external to virtualized system ; “The control logic 220 may further be configured to execute the predefined action if the global watchdog counter value fulfills the predefined global watchdog reference criterion.”, 0041 ; Examiner Note: the control logic equates to a watchdog timer, as executing the predefined action if the counter reaches the reference criterion equates to implementing a watchdog timer)
As per claim 6, Bollu in view of Kashtan fully discloses the limitations of claim 1.
Furthermore, Bollu discloses:
the timer and the watchdog timer are provided as hardware structures (“The clock signal may in various embodiments be provided by a free-running timer 108, which may be part of the watchdog circuit 200, e.g. decoupled from a system clock.”, 0034 ; “In various embodiments, a faster response to watchdog events may be achieved. This means that a real time behavior may be achieved, since the virtual machine watchdog timer (e.g., the counters) is being handled by the hardware.”, 0022)
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Bollu (US 20210406111 A1) in view of Kashtan (US 20220137995 A1) in further view of De Oliveira (US 20160314057 A1) in further view of Kaltenegger (US 20140009166 A1).
As per claim 2, Bollu in view of Kashtan fully discloses the limitations of claim 1, but does not disclose the limitations of claim 2.
However, De Oliveira discloses:
The information processing device of claim 1, wherein the watchdog timer comprises: a first watchdog timer of a timeout mode to output a reset signal in a case in which the clock signal is not input from the hypervisor within a predetermined duration;(“ For fault detection purposes, the component monitors execution of hypervisor and of replicas (e.g. timeout expiration, watchdog). At this end, it provides an interface to ping, at a regular interval, the watchdog to notify it which all is operating correctly. In the absence of such ping call at the end of a predefined time period, the watchdog resets the core (or respectively the processor) executing the Computing Element CE #x (or respectively the Hypervisor #4) software.”, 0104)
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to combine the abnormality detection for the hypervisor and VMs of a virtualized system of Bollu, and the clock signal provided to the hypervisor of Kashtan, with the timeout mode of abnormality detection of De Oliveira in order to provide an additional means with which to determine that the hypervisor has entered a fault state, thereby increasing the reliability of the abnormality detector.
Bollu in view of Kashtan in further view of De Oliveira discloses a timeout mode of an abnormality detector for a virtual machine management section, or hypervisor, but does not disclose a window or Q&A mode for the abnormality detector.
However, Kaltenegger discloses:
a second watchdog timer of a window mode to output a reset signal in a case in which the clock signal is not input from the hypervisor within a predetermined duration or in a case in which a plurality of clock signals are input within a predetermined duration; (“Referring to the explanation above, there are different possible operation modes of the window watchdog 20”, 0078 ; “A pass pulse is generated each time a trigger command is received in an open window period. Optionally, a fail pulse is generated each time a trigger command is received in a closed window period, and each time an open window period expires without having received a trigger command.”, 0079 ; Examiner Note : the watchdog timer operating in pass/fail pulse mode equates to a second watchdog timer)
or a third watchdog timer of a Q&A mode to output a reset signal in a case in which a predetermined signal is not input from the hypervisor. (“A second operation mode in which each of the trigger commands is a window-defining trigger command that includes time information for only one window sequence. In this operation mode, a window sequence starts each time a trigger command is received. A pass pulse is generated each time a trigger command is received in an open window as defined by a previous trigger command. Optionally, a fail pulse is generated Optionally, a fail pulse is generated each time a trigger command is received in a closed window period, and each time an open window period expires without having received a trigger command.”, 0080 ; Examiner Note: the watchdog timer operating in the second operation mode, being configured differently from the second watchdog timer, equates to a third watchdog timer)
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to combine the abnormality detection for the hypervisor and VMs of a virtualized system of Bollu, the clock signal provided to the hypervisor of Kashtan, and the timeout mode of abnormality detection of De Oliveira with the window mode and Q&A mode of abnormality detection of Kaltenegger in order to provide further additional means with which to determine that the hypervisor has entered a fault state, thereby further increasing the reliability of the abnormality detector.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Bollu (US 20210406111 A1) in view of Kashtan (US 20220137995 A1) in further view of Streif (US 20240192978 A1).
As per claim 3, Bollu in view of Kashtan fully discloses the limitations of claim 1, but does not disclose the method being performed within a vehicle.
However, Streif discloses:
A vehicle installed with the information processing device of claim 1. (“Within such a vehicle controller, functionality equivalent to several standalone ECUs may be hosted in virtual machines (VMs) running on a hypervisor, the operating software, on the vehicle controller”, 0004)
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to combine the abnormality detection for the hypervisor and VMs of a virtualized system of Bollu and the clock signal provided to the hypervisor of Kashtan with the use of VMs within a vehicle of Streif, in order to provide the abnormality detection method to the virtualized computing system of a vehicle, thereby increasing the reliability, and consequently safety, of the on-board computing system.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Johnson (US 11481258 B1) – discloses a method for utilizing a clock monitor that allows an application to determine whether clock loss was due to an external source and whether it is of an amount of time that may be naturally recovered from by the application.
Corrie (US 20250077252 A1) – discloses a method for automatically deploying a containerized application; includes booting device with corresponding operating system, booting a virtual machine, and obtaining state configuration files defining control plane configuration ; hypervisor may include infravisor daemon which may be watchdog configured to monitor infravisor services.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/R.M.V./
Examiner, Art Unit 2196
/APRIL Y BLAIR/Supervisory Patent Examiner, Art Unit 2196