DETAILED ACTION
This office action is in response to the application and claims filed on October 27, 2022. Claims 1-15 are pending, with claim 1 as the sole independent claim.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The prior art documents submitted by Applicant in the Information Disclosure Statements filed on November 14, 2025, July 31, 2025, and July 10, 2024, have been considered and made of record (note attached copy of forms PTO-1449).
Drawings
The original drawings (nine (9) pages) were received on October 27, 2022. These drawings are acknowledged.
Claim Objections
Claims 8, 9, and 13 are objected to because of the following informalities: regarding claim 8, this claim should read that the “optoelectronic substrate comprises silicon”, or “the optoelectronic substrate is made from silicon”, and not the added “silicon substrate” language, because the substrate is described in Applicant’s specification as being from silicon (paragraphs [0009], [0029], [0037]). There is no indication that multiple distinct substrates are formed as part of the optoelectronic substrate, one of such being silicon. Accordingly, the following language in claims 8-9 should read “the silicon optoelectronic substrate” after such silicon language is defined (one instance each in claims 8-9). Note the language of claims 10-11 as a comparison for “made from” with the material chosen. Regarding claim 13, the term “the lenses” should read “the two lenses” for consistency of terminology. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-15 are rejected under 35 U.S.C. 103 as being unpatentable over Pezeshki et al. US 2021/0080664 A1, and further in view of Yim et al. U.S. Patent No. 10,727,368 B and Pezeshki et al. US 2021/0208337 A1.
Regarding sole examined independent claim 1, Pezeshki et al. US 2021/0080664 A1 teaches (ABS; Figs. 1-3, 11; corresponding text, in particular paragraphs [0007], [0035] – [0052], [0086] – [0087]; Claims) a transceiver array 211 (Fig. 2a) which is capable being used for a parallel optical interconnect (para [0040], noting that parallel functions can be envisioned, “a parallel microLED interconnect”), comprising: transceiver electronics comprising a plurality of transmitter circuits (para [0007] “transmitter circuitry”) and a plurality of receiver circuits (para [0007] “receiver circuitry”), noting in particular that the transceiver array (Fig. 2a) includes at least a plurality of optical transmitters 213 a-n and a plurality of optical receivers 215 a-n (paras [0042] – [0044]); a plurality of microLEDs (para [0040], “microLED as a light source” give as example transmitter(s)), each of the microLEDs being connected to a corresponding transmitter circuit in the transceiver electronics (para [0040], for the microLED features of Pezeshki ‘664, there is integrated circuit chip and drivers which are included on/with a common substrate); a plurality of photodetectors, each of these photodetectors are being connected to photodetector circuitry which is integrated in design with the overall control circuit chip (for both transceiver functions (emitting and receiving), in the design of Pezeshki ‘664; para [0040]).
Regarding independent claim 1, Pezeshki ‘664 does not expressly and exactly teach that (1) the “transceiver electronics” includes a (distinct) substrate; and when there is a separate substrate (to the “transceiver electronics” substrate) for the optoelectronics, this separate substrate being connected to the transceiver electronics substrate by inter-substrate interconnects; that (2) that each microLED of the transmission function is bonded to a pad on a first surface of the optoelectronic substrate; and that (3) the features of the photodetectors are also found (either integrated or “on” that optoelectronic substrate) on the second substrate. Therefore, the missing features of claim 1 from Pezeshki ‘664 are essentially that there are two separate substrates, one substrate for the actual transceiver (transmitter or receiver) element, and a second substrate for the control circuits / electronics thereof.
Note that for the above missing limitations, the “transceiver electronics substrate” of the claim is the lower substrate 319 (see Applicant’s Fig. 3), while the “optoelectronics substrate” of the claim is the upper substrate 315 (see Fig. 3). Such frame-of-reference is provided for context of the analysis of these missing limitations.
Regarding missing limitation (1), Pezeshki et al. US 2021/0208337 A1 teaches (ABS; Figs. 1-3, 5, 11; corresponding text, in particular paragraphs [0031] – [0038], [0042], [0058], and [0062]; Claims) a similar packaging and chip circuitry design for microLEDs, in which a bonding pad is used as a common approach to attach and secure the microLEDs on a substrate (para [0042]; Fig. 5A).
Regarding missing limitations (2) – (3), Pezeshki ‘337 also teaches (paras [0031] – [0038]; Figs. 1-3) features for which an optical interposer would be used, and known to separate transceiver componentry, in which an optical waveguide 323 / electrical contacts could be used for the features to direct optical and/or electrical signals from the transmitter and/or photoreceiver elements. Further, para [0031] and Fig. 2 of Pezeshki ‘337 teaches that componentry such as “The Tx blocks include microLEDs for generating the optical signals based on electrical signals, and the Rx blocks include photodetectors for generating electrical signals based on received optical signals.” Additionally, Fig. 3 of Pezeshki ‘337 teaches (para [0033]) that there may be through vias through the interposer substrate 351 (“through-chip-vias” TCVs) for both powering and signal contact and communication of opto-electronics, in which it is implied by this construct that arranging a plurality of transmitter circuits and a plurality of receiver circuits on a separate transceiver electronics substrate (separate from the location of the actual microLEDs and the actual photodetectors themselves).
Further regarding the missing limitations (2) and (3), in a similar vein to Pezeshki ‘337, the prior art of Yim et al. U.S. Patent No. 10,727,368 B2 also teaches (ABS; Figs. 1, 2, 4, 8; corresponding text, see column 2, line 20 through column 4, line 67; Claims) teaches an optoelectronic device which uses a silicon interposer feature 104 (Fig. 4), in which the Tx elements are found elsewhere (at the upper Tx die feature 102), and there is separation of these elements, with electrical contacts 410 on the interposer, and intervening interconnect elements 116 that separate such function of the transceiver from the electrical connection / control thereof. Note in particular in Yim Fig. 4 and the text of the abstract, the motivation and improvement of design is noted in that the substrate element 108 (lower-most feature in Fig. 4) can include electrical control and that such separation, or features formed on different substrates, include the improvement for reduction of the likelihood of damage of optical componentry, because formation of the control circuitry can be separate and not interfere with the operation of different opto-electronics on different levels. Through-vias 416 / 418 are shown in Yim Fig. 4, which will electrically contact features in the lower substrate (for circuit control)
Since Pezeshki ‘664 and Yim US ’368 / Pezeshki ‘337 are all from the same field of endeavor, the purposes disclosed by Yim US ’368 / Pezeshki ‘337 would have been recognized in the pertinent art of Pezeshki ‘664.
A person having ordinary skill in the art at a time before the effective filing date of the current application would have recognized the teachings of Yim US ’368 / Pezeshki ‘337, to use a bonding pad, and to recognize that separation of design may be used to have the transmit/receive optical elements on different substrates to the control circuity of such same features, into the base design of the packing chip for microLEDs as found in Pezeshki ‘664, to recognize the motivations of teaching such separation of design in both Yim US ’368 and Pezeshki ‘337. This secondary prior art teaches that separation of design of the control circuitry to be placed at different locations of the overall package / chip would improve optical and/or electrical operation because optical damage will be decreased by such separation. Therefore, the control circuitry for the Tx / Rx operations can be located at/on a different substrate. Further, it would have required no undue burden or unnecessary experimentation to arrive at such feature of having two separate substrates in an overall design, based on the clear motivations and rationales for doing so in the secondary prior art of Yim / Pezeshki ‘337. See KSR v. Teleflex, 127 S.Ct. 1727 (2007). For these reasons, independent claim 1 is found obvious over Pezeshki ‘664 and further in view of Yim US ’368 and Pezeshki ‘337 (henceforth “COMBO”).
Regarding dependent claim 2, the inter-substrate interconnects are located between separated features in at least Yim, see Fig. 4, at 116, and are located on a surface of the lower (electronics / control) substrate feature. Such features are also implied in Pezeshki ‘337 in Fig. 3 and para [0033]. Therefore, claim 2 would have been obvious based on the hypothetical combination in COMBO above. KSR.
Regarding claim 3, a plurality of vias / through-via contacts are shown in both Pezeshki ‘337 (with interposer 351) and Yim ‘368 (with 116 to 104 to 416/418) secondary prior art, which imply the same formation with the separated substrate design as in claim 1 above. KSR.
Regarding claims 4-7, which is dependent upon claim 3, the specifics of the structure of each microLED would have been an obvious design choice for the type of microLED selected. Choice of which microLED to use and employ in operation for transceiver function would have been recognized by one having ordinary skill in the transmit / receive art. For these reasons, the features of claims 4-7 are considered obvious design choices of the microLED, which is already outlined by Pezeshki ‘664 in Figs. 2a-2c and paragraph [0044]. Therefore, claims 4-7 do not present any patentable distinction over COMBO and are found obvious herein. KSR.
Regarding claims 8-9, the integration of the secondary features on a separate control circuity substrate would have been obvious as “silicon” – based, because using silicon for a substrate is common and imputes no distinguishable features over COMBO, as listed above for claim 1. Further, integrating and bonding photodetectors to such substrate does not improve the operation thereof, and would have been an obvious means for attached / securing photodetectors to this substrate. KSR. Therefore, the features of claims 8-9 would have been obvious over COMBO.
Regarding claims 10-11, the selection of a usable material for the O/E substrate (as either organic laminate (claim 10) or glass (claim 11)) would have been an obvious design choice and does not impute any structure features that would improve the operation of COMBO. One having ordinary skill in the art at the time of the effective filing date would have recognized choosing glass or organic laminate as substrates readily available with predictable results for mounting the microLED and/or photodetector features. KSR.
Regarding claims 12-15, using an optical coupling system (note the breadth of “coupling”, which could be optical lenses, waveguides, mirrors, gratings, etc. anything that couples optical signals) being mounted to the O/E substrate, and also at least the primary reference to Pezeshki ‘664 teaches (Fig. 11 and para [0087]) two lens assemblies and a turning mirror, those formed for “coupling” to the on-chip design of the Tx/Rx communication. Such lenses and reflectors would be recognized by the normally skilled artisan to improve optical coupling to/from the package chip in COMBO. Therefore, features of claim 12, and further dependent claims 13-15, would have been obvious at the time of the effective filing date of the current application. KSR. In particular, the 4f imaging with magnification (in claims 14-15) are known designs for optical lenses for coupling to a package chip.
Additionally, the Examiner fully incorporates, and agrees with, the logic and rationale found regarding claims 1-15 in the Annex to the European Search Report, and Extended (Supplemental) Search Report for EP 22 88 8184. The text is found in “Inventive Step” in sections 2.1 through 2.2, noting the IDS filed on July 31, 2025.
Inventorship
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: PTO-892 form references B-E, which pertain to the state of the art of opto-electronic package devices that include transceiver componentry in an integrated design for the optical and electronic sub-components thereof. Note Youn US ‘219 (B) Figs. 1-2 and element 100 / 200; Thacker US ‘804 (C) chip package 100 of Fig. 1 and Figs. 8 and 13; Zarbock US ‘639 (D) Figs. 5, 11, and 12d; and Uemura US ‘463 (E) Figs. 1a, 3, and 7b. Such prior art references integrate both transmitter and receiver functions into package designs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Daniel Petkovsek whose telephone number is (571) 272-4174. The examiner can normally be reached M-F 7:30 - 6 PM.
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/DANIEL PETKOVSEK/Primary Examiner, Art Unit 2874 December 5, 2025