Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 5, 11-13, 19, 21-22 and 24-25 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bahr (US 11,303,288).
Regarding claim 1, Bahr discloses an apparatus (FIG 1), comprising:
an oscillator circuit (116) having an oscillator output (124), the oscillator circuit including a compensation circuit (104) having a resonator (106) and a resonator delay analyzing circuit (DPLL inherently comprising resonator or in the VCO analyzing loop delay by a phase detector) coupled to an output of the resonator (VCO connected to PD by feedback loop); and
a clock generation circuit (Column 1, lines 12-13 implies) having an input (necessarily present at the stage in which 124 feeds) coupled to the oscillator output (124).
Regarding claim 2|1, Bahr discloses the apparatus wherein:
the resonator is a first resonator (106);
the oscillator circuit includes a second resonator (114); and
the oscillator circuit includes an oscillator control circuit (102) having an input (102B), a first output (connection to 114), and a second output (102A), the input of the oscillator control circuit coupled to an output of the resonator delay analyzing circuit (DPLL 106), the first output of the oscillator control circuit coupled to the second resonator, and the second output of the oscillator control circuit coupled to the oscillator output.
Regarding claim 5|2|1, Bahr discloses the apparatus wherein the resonator delay analyzing circuit is configured to provide a signal representing a group delay of the first resonator (feedback loop in the DPLL).
Regarding claim 11|2|1, Bahr discloses/implies the apparatus wherein the second resonator has second-order frequency variation as a function of temperature, and the first resonator has first-order frequency variation as a function of temperature (it is noted that all resonators have some degree of frequency variation as a function of temperature).
Regarding claim 12, Bahr discloses an apparatus (FIG 1), comprising:
an oscillator circuit (116) including a first resonator (114), an oscillator control circuit (102) coupled to the first resonator and having an oscillator output (102A or 124), and a temperature compensation circuit (104) coupled to the oscillator output and including a second resonator (106, resonator in DPLL); and
a clock generation circuit (Column 1, lines 12-13 implies) having an input coupled to the oscillator output (124).
Regarding claim 13|12, Bahr discloses the apparatus wherein the oscillator circuit includes a controller (108) configured to determine a temperature (110) based on a property of the second resonator (resonator in DPLL) and provide a control signal (108B and 102B) based on the temperature to the oscillator control circuit.
Regarding claim 19|12, Bahr discloses/implies the apparatus wherein the first resonator has second-order frequency variation as a function of temperature, and the second resonator has first-order frequency variation as a function of temperature (it is noted that all resonators have some degree of frequency variation as a function of temperature).
Regarding claim 21|1, Bahr implies the apparatus further comprising a circuitry (Column 1, lines 12-13 implies) coupled to an output of the clock generation circuit (124).
Regarding claim 22|21|1, Bahr implies the apparatus wherein the circuitry includes at least one of: a microprocessor, a memory, or a programmable logic circuit (Column 1, lines 12-13 implies).
Regarding claim 24|21|1, Bahr discloses the apparatus wherein the resonator includes an electroacoustic resonator (MEMS resonator).
Regarding claim 25|1, Bahr implies the apparatus wherein the resonator has positive and negative peaks of group delay at two different frequencies (MEMS resonator).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 16, 20 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bahr.
Regarding claim 16, Bahr discloses the apparatus except further comprising a divider circuit coupled between the oscillator output and an input of the temperature compensation circuit. As known in the art, such divider circuit is used in PLL circuit for frequency adjustment and therefore it would have been obvious to one of ordinary skill in the art to use such divider circuit because such a modification would have been a mere substitution of art recognized equivalent feedback scheme in PLL.
Regarding claim 20, Bahr discloses the apparatus except wherein the oscillator control circuit includes a transimpedance amplifier (TIA) coupled across the first resonator. As known in the art, TIA is used in oscillator circuit for frequency signal enhancement and therefore it would have been obvious to one of ordinary skill in the art to use such device because such a modification would have been a mere substitution of art recognized equivalent amplifier in oscillators.
Regarding claim 23, Bahr discloses the apparatus except wherein the oscillator circuit, the clock generation circuit, and the circuitry are within an integrated circuit package. As known in the art, IC is used to integrate circuits to save space and therefore it would have been obvious to one of ordinary skill in the art to integrate the circuitry because such a modification would have been a mere substitution of art recognized equivalent IC.
Allowable Subject Matter
Claims 3-4, 6-10, 14-15 and 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Bahr does not disclose nor suggest the claimed invention including “an amplitude modulation circuit” recited in claims 3 and 17; “a mixer circuit …” recited in claims 4 and 18; “a second resonator delay analyzing circuit” recited in claims 6-10; “at least one of a group delay amplitude or a phase delay sign” recited in claims 14 and 15.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Nelson (US 2019/0007055) discloses clock synchronization and compensation of signal path delay variation showing a system clock PLL, output distribution and system clock compensation.
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/JOSEPH CHANG/Primary Examiner, Art Unit 2849